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Sun, 24 Nov 2024 00:59:20 -0800 (PST) Received: from fshao-p620.tpe.corp.google.com ([2401:fa00:1:10:f699:9cb9:f928:9a14]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7fbcbfc4c28sm4465890a12.3.2024.11.24.00.59.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 00:59:20 -0800 (PST) From: Fei Shao To: AngeloGioacchino Del Regno , Matthias Brugger Cc: Fei Shao , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 1/2] dt-bindings: arm: mediatek: Add MT8188 Lenovo Chromebook Duet (11", 9) Date: Sun, 24 Nov 2024 16:52:37 +0800 Message-ID: <20241124085739.290556-2-fshao@chromium.org> X-Mailer: git-send-email 2.47.0.371.ga323438b13-goog In-Reply-To: <20241124085739.290556-1-fshao@chromium.org> References: <20241124085739.290556-1-fshao@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add entries for the MT8188-based Chromebook "Ciri", also known as Lenovo Chromebook Duet (11", 9). This device features a detachable design with touchscreen, detachable keyboard and USI 2.0 Stylus support, and has 8 SKUs to accommodate the combinations of second-source components. Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Fei Shao --- (no changes since v1) Documentation/devicetree/bindings/arm/mediatek.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Document= ation/devicetree/bindings/arm/mediatek.yaml index 1d4bb50fcd8d..4b68f0baf010 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -307,6 +307,19 @@ properties: - enum: - mediatek,mt8186-evb - const: mediatek,mt8186 + - description: Google Ciri (Lenovo Chromebook Duet (11", 9)) + items: + - enum: + - google,ciri-sku0 + - google,ciri-sku1 + - google,ciri-sku2 + - google,ciri-sku3 + - google,ciri-sku4 + - google,ciri-sku5 + - google,ciri-sku6 + - google,ciri-sku7 + - const: google,ciri + - const: mediatek,mt8188 - items: - enum: - mediatek,mt8188-evb --=20 2.47.0.371.ga323438b13-goog From nobody Sun Nov 24 14:23:07 2024 Received: from mail-pg1-f170.google.com (mail-pg1-f170.google.com [209.85.215.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D599E18787A for ; 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Sun, 24 Nov 2024 00:59:22 -0800 (PST) Received: from fshao-p620.tpe.corp.google.com ([2401:fa00:1:10:f699:9cb9:f928:9a14]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7fbcbfc4c28sm4465890a12.3.2024.11.24.00.59.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Nov 2024 00:59:22 -0800 (PST) From: Fei Shao To: AngeloGioacchino Del Regno , Matthias Brugger Cc: Fei Shao , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 2/2] arm64: dts: mediatek: Introduce MT8188 Geralt platform based Ciri Date: Sun, 24 Nov 2024 16:52:38 +0800 Message-ID: <20241124085739.290556-3-fshao@chromium.org> X-Mailer: git-send-email 2.47.0.371.ga323438b13-goog In-Reply-To: <20241124085739.290556-1-fshao@chromium.org> References: <20241124085739.290556-1-fshao@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce MT8188-based Chromebook Ciri, also known commercially as Lenovo Chromebook Duet (11", 9). Ciri is a detachable device based on the Geralt design, where Geralt is the codename for the MT8188 platform. Ciri offers 8 SKUs to accommodate different combinations of second-source components, including: - audio codecs (RT5682S and ES8326) - speaker amps (TAS2563 and MAX98390) - MIPI-DSI panels (BOE nv110wum-l60 and IVO t109nw41) Signed-off-by: Fei Shao --- Changes in v3: - drop scp_mem, scp_pins and SCP declaration per discussion in v2 - drop unused (for now) dual-SCP reserved memory range - drop unused touchscreen pinctrl - drop unused HID-I2C touchscreen node in I2C-2 - drop unused AP-SAR sensor node in I2C-3 - drop trackpad node in I2C-4 (only work with downstream CBAS) - drop mmc1 (unused in public product) - drop eDP panel path (unused in public product) - declare DSI panel compatibles in individual board .dts files - declare CPU TDP target in -geralt.dtsi instead - move spi1 default and sleep pinctrl to -geralt.dtsi - leave memory@40000000 size empty (filled by bootloader) - consolidate audio codec/amplifier, DAI link declaration and audio-routing property - stop sourcing `arm/cros-ec-sbs.dtsi` in -geralt.dtsi, because all that does is to declare sbs-battery at address 0xb, which doesn't align with the final design at 0xf. This saves us a /delete-node/. - minor format fix Changes in v2: - remove invalid or undocumented properties e.g. mediatek,dai-link, maxim,dsm_param_name etc. - remove touchscreen as the driver is not yet accepted in upstream - update sound DAI link node name to match the binding - add missing pinctrls in audio codec nodes arch/arm64/boot/dts/mediatek/Makefile | 8 + .../dts/mediatek/mt8188-geralt-ciri-sku0.dts | 32 + .../dts/mediatek/mt8188-geralt-ciri-sku1.dts | 59 + .../dts/mediatek/mt8188-geralt-ciri-sku2.dts | 59 + .../dts/mediatek/mt8188-geralt-ciri-sku3.dts | 32 + .../dts/mediatek/mt8188-geralt-ciri-sku4.dts | 48 + .../dts/mediatek/mt8188-geralt-ciri-sku5.dts | 72 + .../dts/mediatek/mt8188-geralt-ciri-sku6.dts | 72 + .../dts/mediatek/mt8188-geralt-ciri-sku7.dts | 48 + .../boot/dts/mediatek/mt8188-geralt-ciri.dtsi | 316 +++++ .../boot/dts/mediatek/mt8188-geralt.dtsi | 1156 +++++++++++++++++ 11 files changed, 1902 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku0.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku1.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku2.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku3.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku4.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku5.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku6.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku7.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri.dtsi create mode 100644 arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index 8fd7b2bb7a15..c6c34d99316b 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -69,6 +69,14 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8186-corsola-voltorb-= sku589824.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8186-corsola-voltorb-sku589825.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8186-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8188-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8188-geralt-ciri-sku0.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8188-geralt-ciri-sku1.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8188-geralt-ciri-sku2.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8188-geralt-ciri-sku3.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8188-geralt-ciri-sku4.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8188-geralt-ciri-sku5.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8188-geralt-ciri-sku6.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8188-geralt-ciri-sku7.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8192-asurada-hayato-r1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8192-asurada-hayato-r5-sku2.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8192-asurada-spherion-r0.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku0.dts b/arc= h/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku0.dts new file mode 100644 index 000000000000..79d6d12394b9 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku0.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2023 Google LLC + */ +/dts-v1/; +#include "mt8188-geralt-ciri.dtsi" + +/ { + model =3D "Google Ciri sku0 board"; + compatible =3D "google,ciri-sku0", "google,ciri", "mediatek,mt8188"; +}; + +&dsi_panel { + compatible =3D "boe,nv110wum-l60", "himax,hx83102"; +}; + +&sound { + compatible =3D "mediatek,mt8188-rt5682s"; + model =3D "mt8188_m98390_5682"; + + audio-routing =3D + "ETDM1_OUT", "ETDM_SPK_PIN", + "ETDM2_OUT", "ETDM_HP_PIN", + "ETDM1_IN", "ETDM_SPK_PIN", + "ETDM2_IN", "ETDM_HP_PIN", + "ADDA Capture", "MTKAIF_PIN", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "IN1P", "Headset Mic", + "Left Spk", "Front Left BE_OUT", + "Right Spk", "Front Right BE_OUT"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku1.dts b/arc= h/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku1.dts new file mode 100644 index 000000000000..ef5ea9d12b1d --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku1.dts @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2023 Google LLC + */ +/dts-v1/; +#include "mt8188-geralt-ciri.dtsi" + +/ { + model =3D "Google Ciri sku1 board"; + compatible =3D "google,ciri-sku1", "google,ciri", "mediatek,mt8188"; +}; + +&dsi_panel { + compatible =3D "ivo,t109nw41", "himax,hx83102"; +}; + +&i2c0 { + /delete-node/ audio-codec@1a; + + es8326: audio-codec@19 { + compatible =3D "everest,es8326"; + reg =3D <0x19>; + interrupts-extended =3D <&pio 108 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&audio_codec_pins>; + #sound-dai-cells =3D <0>; + everest,jack-pol =3D [0e]; + everest,interrupt-clk =3D [00]; + }; +}; + +&sound { + compatible =3D "mediatek,mt8188-es8326"; + model =3D "mt8188_m98390_8326"; + + audio-routing =3D + "ETDM1_OUT", "ETDM_SPK_PIN", + "ETDM2_OUT", "ETDM_HP_PIN", + "ETDM1_IN", "ETDM_SPK_PIN", + "ETDM2_IN", "ETDM_HP_PIN", + "ADDA Capture", "MTKAIF_PIN", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "MIC1", "Headset Mic", + "Left Spk", "Front Left BE_OUT", + "Right Spk", "Front Right BE_OUT"; + + dai-link-2 { + codec { + sound-dai =3D <&es8326>; + }; + }; + + dai-link-3 { + codec { + sound-dai =3D <&es8326>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku2.dts b/arc= h/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku2.dts new file mode 100644 index 000000000000..ef56786fc2be --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku2.dts @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2024 Google LLC + */ +/dts-v1/; +#include "mt8188-geralt-ciri.dtsi" + +/ { + model =3D "Google Ciri sku2 board"; + compatible =3D "google,ciri-sku2", "google,ciri", "mediatek,mt8188"; +}; + +&dsi_panel { + compatible =3D "boe,nv110wum-l60", "himax,hx83102"; +}; + +&i2c0 { + /delete-node/ audio-codec@1a; + + es8326: audio-codec@19 { + compatible =3D "everest,es8326"; + reg =3D <0x19>; + interrupts-extended =3D <&pio 108 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&audio_codec_pins>; + #sound-dai-cells =3D <0>; + everest,jack-pol =3D [0e]; + everest,interrupt-clk =3D [00]; + }; +}; + +&sound { + compatible =3D "mediatek,mt8188-es8326"; + model =3D "mt8188_m98390_8326"; + + audio-routing =3D + "ETDM1_OUT", "ETDM_SPK_PIN", + "ETDM2_OUT", "ETDM_HP_PIN", + "ETDM1_IN", "ETDM_SPK_PIN", + "ETDM2_IN", "ETDM_HP_PIN", + "ADDA Capture", "MTKAIF_PIN", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "MIC1", "Headset Mic", + "Left Spk", "Front Left BE_OUT", + "Right Spk", "Front Right BE_OUT"; + + dai-link-2 { + codec { + sound-dai =3D <&es8326>; + }; + }; + + dai-link-3 { + codec { + sound-dai =3D <&es8326>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku3.dts b/arc= h/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku3.dts new file mode 100644 index 000000000000..524f7f0064c1 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku3.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2024 Google LLC + */ +/dts-v1/; +#include "mt8188-geralt-ciri.dtsi" + +/ { + model =3D "Google Ciri sku3 board"; + compatible =3D "google,ciri-sku3", "google,ciri", "mediatek,mt8188"; +}; + +&dsi_panel { + compatible =3D "ivo,t109nw41", "himax,hx83102"; +}; + +&sound { + compatible =3D "mediatek,mt8188-rt5682s"; + model =3D "mt8188_m98390_5682"; + + audio-routing =3D + "ETDM1_OUT", "ETDM_SPK_PIN", + "ETDM2_OUT", "ETDM_HP_PIN", + "ETDM1_IN", "ETDM_SPK_PIN", + "ETDM2_IN", "ETDM_HP_PIN", + "ADDA Capture", "MTKAIF_PIN", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "IN1P", "Headset Mic", + "Left Spk", "Front Left BE_OUT", + "Right Spk", "Front Right BE_OUT"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku4.dts b/arc= h/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku4.dts new file mode 100644 index 000000000000..ea953d7e1543 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku4.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2024 Google LLC + */ +/dts-v1/; +#include "mt8188-geralt-ciri.dtsi" + +/ { + model =3D "Google Ciri sku4 board (rev4)"; + compatible =3D "google,ciri-sku4", "google,ciri", "mediatek,mt8188"; +}; + +&dsi_panel { + compatible =3D "boe,nv110wum-l60", "himax,hx83102"; +}; + +&i2c0 { + /delete-node/ amplifier@38; + /delete-node/ amplifier@39; + + tas2563: amplifier@4f { + compatible =3D "ti,tas2563", "ti,tas2781"; + reg =3D <0x4f>, <0x4c>; /* left / right channel */ + reset-gpios =3D <&pio 118 GPIO_ACTIVE_HIGH>; + #sound-dai-cells =3D <0>; + }; +}; + +&sound { + compatible =3D "mediatek,mt8188-rt5682s"; + model =3D "mt8188_tas2563_5682"; + + audio-routing =3D + "ETDM1_OUT", "ETDM_SPK_PIN", + "ETDM2_OUT", "ETDM_HP_PIN", + "ETDM1_IN", "ETDM_SPK_PIN", + "ETDM2_IN", "ETDM_HP_PIN", + "ADDA Capture", "MTKAIF_PIN", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "IN1P", "Headset Mic"; + + dai-link-1 { + codec { + sound-dai =3D <&tas2563>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku5.dts b/arc= h/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku5.dts new file mode 100644 index 000000000000..bf87201ccf27 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku5.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2024 Google LLC + */ +/dts-v1/; +#include "mt8188-geralt-ciri.dtsi" + +/ { + model =3D "Google Ciri sku5 board (rev4)"; + compatible =3D "google,ciri-sku5", "google,ciri", "mediatek,mt8188"; +}; + +&dsi_panel { + compatible =3D "ivo,t109nw41", "himax,hx83102"; +}; + +&i2c0 { + /delete-node/ audio-codec@1a; + /delete-node/ amplifier@38; + /delete-node/ amplifier@39; + + es8326: audio-codec@19 { + compatible =3D "everest,es8326"; + reg =3D <0x19>; + interrupts-extended =3D <&pio 108 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&audio_codec_pins>; + #sound-dai-cells =3D <0>; + everest,jack-pol =3D [0e]; + everest,interrupt-clk =3D [00]; + }; + + tas2563: amplifier@4f { + compatible =3D "ti,tas2563", "ti,tas2781"; + reg =3D <0x4f>, <0x4c>; /* left / right channel */ + reset-gpios =3D <&pio 118 GPIO_ACTIVE_HIGH>; + #sound-dai-cells =3D <0>; + }; +}; + +&sound { + compatible =3D "mediatek,mt8188-es8326"; + model =3D "mt8188_tas2563_8326"; + + audio-routing =3D + "ETDM1_OUT", "ETDM_SPK_PIN", + "ETDM2_OUT", "ETDM_HP_PIN", + "ETDM1_IN", "ETDM_SPK_PIN", + "ETDM2_IN", "ETDM_HP_PIN", + "ADDA Capture", "MTKAIF_PIN", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "MIC1", "Headset Mic"; + + dai-link-1 { + codec { + sound-dai =3D <&tas2563>; + }; + }; + + dai-link-2 { + codec { + sound-dai =3D <&es8326>; + }; + }; + + dai-link-3 { + codec { + sound-dai =3D <&es8326>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku6.dts b/arc= h/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku6.dts new file mode 100644 index 000000000000..17d7359dfb6a --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku6.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2024 Google LLC + */ +/dts-v1/; +#include "mt8188-geralt-ciri.dtsi" + +/ { + model =3D "Google Ciri sku6 board (rev4)"; + compatible =3D "google,ciri-sku6", "google,ciri", "mediatek,mt8188"; +}; + +&dsi_panel { + compatible =3D "boe,nv110wum-l60", "himax,hx83102"; +}; + +&i2c0 { + /delete-node/ audio-codec@1a; + /delete-node/ amplifier@38; + /delete-node/ amplifier@39; + + es8326: audio-codec@19 { + compatible =3D "everest,es8326"; + reg =3D <0x19>; + interrupts-extended =3D <&pio 108 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&audio_codec_pins>; + #sound-dai-cells =3D <0>; + everest,jack-pol =3D [0e]; + everest,interrupt-clk =3D [00]; + }; + + tas2563: amplifier@4f { + compatible =3D "ti,tas2563", "ti,tas2781"; + reg =3D <0x4f>, <0x4c>; /* left / right channel */ + reset-gpios =3D <&pio 118 GPIO_ACTIVE_HIGH>; + #sound-dai-cells =3D <0>; + }; +}; + +&sound { + compatible =3D "mediatek,mt8188-es8326"; + model =3D "mt8188_tas2563_8326"; + + audio-routing =3D + "ETDM1_OUT", "ETDM_SPK_PIN", + "ETDM2_OUT", "ETDM_HP_PIN", + "ETDM1_IN", "ETDM_SPK_PIN", + "ETDM2_IN", "ETDM_HP_PIN", + "ADDA Capture", "MTKAIF_PIN", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "MIC1", "Headset Mic"; + + dai-link-1 { + codec { + sound-dai =3D <&tas2563>; + }; + }; + + dai-link-2 { + codec { + sound-dai =3D <&es8326>; + }; + }; + + dai-link-3 { + codec { + sound-dai =3D <&es8326>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku7.dts b/arc= h/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku7.dts new file mode 100644 index 000000000000..825015b452d5 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku7.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2024 Google LLC + */ +/dts-v1/; +#include "mt8188-geralt-ciri.dtsi" + +/ { + model =3D "Google Ciri sku7 board (rev4)"; + compatible =3D "google,ciri-sku7", "google,ciri", "mediatek,mt8188"; +}; + +&dsi_panel { + compatible =3D "ivo,t109nw41", "himax,hx83102"; +}; + +&i2c0 { + /delete-node/ amplifier@38; + /delete-node/ amplifier@39; + + tas2563: amplifier@4f { + compatible =3D "ti,tas2563", "ti,tas2781"; + reg =3D <0x4f>, <0x4c>; /* left / right channel */ + reset-gpios =3D <&pio 118 GPIO_ACTIVE_HIGH>; + #sound-dai-cells =3D <0>; + }; +}; + +&sound { + compatible =3D "mediatek,mt8188-rt5682s"; + model =3D "mt8188_tas2563_5682"; + + audio-routing =3D + "ETDM1_OUT", "ETDM_SPK_PIN", + "ETDM2_OUT", "ETDM_HP_PIN", + "ETDM1_IN", "ETDM_SPK_PIN", + "ETDM2_IN", "ETDM_HP_PIN", + "ADDA Capture", "MTKAIF_PIN", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "IN1P", "Headset Mic"; + + dai-link-1 { + codec { + sound-dai =3D <&tas2563>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri.dtsi b/arch/ar= m64/boot/dts/mediatek/mt8188-geralt-ciri.dtsi new file mode 100644 index 000000000000..6815c435a57e --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri.dtsi @@ -0,0 +1,316 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2023 Google LLC + */ +/dts-v1/; +#include "mt8188-geralt.dtsi" + +&aud_etdm_hp_on { + pins-mclk { + pinmux =3D ; + }; +}; + +&aud_etdm_hp_off { + pins-mclk { + pinmux =3D ; + bias-pull-down; + input-enable; + }; +}; + +&i2c0 { + rt5682s: audio-codec@1a { + compatible =3D "realtek,rt5682s"; + reg =3D <0x1a>; + interrupts-extended =3D <&pio 108 IRQ_TYPE_EDGE_BOTH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&audio_codec_pins>; + #sound-dai-cells =3D <1>; + + AVDD-supply =3D <&mt6359_vio18_ldo_reg>; + DBVDD-supply =3D <&mt6359_vio18_ldo_reg>; + LDO1-IN-supply =3D <&mt6359_vio18_ldo_reg>; + MICVDD-supply =3D <&pp3300_s3>; + realtek,jd-src =3D <1>; + }; + + max98390_38: amplifier@38 { + compatible =3D "maxim,max98390"; + reg =3D <0x38>; + sound-name-prefix =3D "Front Right"; + reset-gpios =3D <&pio 118 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&speaker_en>; + #sound-dai-cells =3D <0>; + }; + + max98390_39: amplifier@39 { + compatible =3D "maxim,max98390"; + reg =3D <0x39>; + sound-name-prefix =3D "Front Left"; + #sound-dai-cells =3D <0>; + }; +}; + +&i2c_tunnel { + /* + * The virtual battery I2C addr is 0xf on Ciri, so we describe it + * manually instead of including 'arm/cros-ec-sbs.dtsi'. + **/ + battery: sbs-battery@f { + compatible =3D "sbs,sbs-battery"; + reg =3D <0xf>; + sbs,i2c-retry-count =3D <2>; + sbs,poll-retry-count =3D <1>; + }; +}; + +&mipi_tx_config0 { + drive-strength-microamp =3D <5200>; +}; + +&mt6359_vm18_ldo_reg { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1900000>; + regulator-microvolt-offset =3D <100000>; +}; + +&sound { + dai-link-0 { + link-name =3D "ETDM1_IN_BE"; + dai-format =3D "i2s"; + mediatek,clk-provider =3D "cpu"; + }; + + dai-link-1 { + link-name =3D "ETDM1_OUT_BE"; + dai-format =3D "i2s"; + mediatek,clk-provider =3D "cpu"; + + codec { + sound-dai =3D <&max98390_38>, + <&max98390_39>; + }; + }; + + dai-link-2 { + link-name =3D "ETDM2_IN_BE"; + mediatek,clk-provider =3D "cpu"; + + codec { + sound-dai =3D <&rt5682s 0>; + }; + }; + + dai-link-3 { + link-name =3D "ETDM2_OUT_BE"; + mediatek,clk-provider =3D "cpu"; + + codec { + sound-dai =3D <&rt5682s 0>; + }; + }; + + dai-link-4 { + link-name =3D "DPTX_BE"; + + codec { + sound-dai =3D <&dp_tx>; + }; + }; +}; + +&pio { + gpio-line-names =3D + "GSC_AP_INT_ODL", + "AP_DISP_BKLTEN", + "", + "EN_PPVAR_MIPI_DISP", + "EN_PPVAR_MIPI_DISP_150MA", + "TCHSCR_RST_1V8_L", + "", + "", + "", + "", + "", + "I2S_SPKR_DATAOUT", + "EN_PP3300_WLAN_X", + "WIFI_KILL_1V8_L", + "BT_KILL_1V8_L", + "AP_FLASH_WP_L", /* ... is crossystem ABI. Rev1 schematics call it AP_WP= _ODL. */ + "", + "", + "WCAM_PWDN_L", + "WCAM_RST_L", + "UCAM_PWDM_L", + "UCAM_RST_L", + "WCAM_24M_CLK", + "UCAM_24M_CLK", + "MT6319_INT", + "DISP_RST_1V8_L", + "DSIO_DSI_TE", + "", + "TP", + "MIPI_BL_PWM_1V8", + "", + "UART_AP_TX_GSC_RX", + "UART_GSC_TX_AP_RX", + "UART_SSPM_TX_DBGCON_RX", + "UART_DBGCON_TX_SSPM_RX", + "UART_ADSP_TX_DBGCON_RX", + "UART_DBGCON_TX_ADSP_RX", + "JTAG_AP_TMS", + "JTAG_AP_TCK", + "JTAG_AP_TDI", + "JTAG_AP_TDO", + "JTAG_AP_TRST", + "AP_KPCOL0", + "TP", + "", + "TP", + "EC_AP_HPD_OD", + "PCIE_WAKE_1V8_ODL", + "PCIE_RST_1V8_L", + "PCIE_CLKREQ_1V8_ODL", + "", + "", + "", + "", + "", + "AP_I2C_AUD_SCL_1V8", + "AP_I2C_AUD_SDA_1V8", + "AP_I2C_TPM_SCL_1V8", + "AP_I2C_TPM_SDA_1V8", + "AP_I2C_TCHSCR_SCL_1V8", + "AP_I2C_TCHSCR_SDA_1V8", + "AP_I2C_PMIC_SAR_SCL_1V8", + "AP_I2C_PMIC_SAR_SDA_1V8", + "AP_I2C_EC_HID_KB_SCL_1V8", + "AP_I2C_EC_HID_KB_SDA_1V8", + "AP_I2C_UCAM_SCL_1V8", + "AP_I2C_UCAM_SDA_1V8", + "AP_I2C_WCAM_SCL_1V8", + "AP_I2C_WCAM_SDA_1V8", + "SPI_AP_CS_EC_L", + "SPI_AP_CLK_EC", + "SPI_AP_DO_EC_DI", + "SPI_AP_DI_EC_DO", + "TP", + "TP", + "SPI_AP_CS_TCHSCR_L", + "SPI_AP_CLK_TCHSCR", + "SPI_AP_DO_TCHSCR_DI", + "SPI_AP_DI_TCHSCR_DO", + "TP", + "TP", + "TP", + "TP", + "", + "", + "", + "TP", + "", + "", + "", + "", + "", + "PWRAP_SPI_CS_L", + "PWRAP_SPI_CK", + "PWRAP_SPI_MOSI", + "PWRAP_SPI_MISO", + "SRCLKENA0", + "SRCLKENA1", + "SCP_VREQ_VAO", + "AP_RTC_CLK32K", + "AP_PMIC_WDTRST_L", + "AUD_CLK_MOSI", + "AUD_SYNC_MOSI", + "AUD_DAT_MOSI0", + "AUD_DAT_MOSI1", + "AUD_DAT_MISO0", + "AUD_DAT_MISO1", + "", + "HP_INT_ODL", + "SPKR_INT_ODL", + "I2S_HP_DATAIN", + "EN_SPKR", + "I2S_SPKR_MCLK", + "I2S_SPKR_BCLK", + "I2S_HP_MCLK", + "I2S_HP_BCLK", + "I2S_HP_LRCK", + "I2S_HP_DATAOUT", + "RST_SPKR_L", + "I2S_SPKR_LRCK", + "I2S_SPKR_DATAIN", + "", + "", + "", + "", + "SPI_AP_CLK_ROM", + "SPI_AP_CS_ROM_L", + "SPI_AP_DO_ROM_DI", + "SPI_AP_DI_ROM_DO", + "TP", + "TP", + "", + "", + "", + "", + "", + "", + "", + "", + "EN_PP2800A_UCAM_X", + "EN_PP1200_UCAM_X", + "EN_PP2800A_WCAM_X", + "EN_PP1100_WCAM_X", + "TCHSCR_INT_1V8_L", + "", + "MT7921_PMU_EN_1V8", + "", + "AP_EC_WARM_RST_REQ", + "EC_AP_HID_INT_ODL", + "EC_AP_INT_ODL", + "AP_XHCI_INIT_DONE", + "EMMC_DAT7", + "EMMC_DAT6", + "EMMC_DAT5", + "EMMC_DAT4", + "EMMC_RST_L", + "EMMC_CMD", + "EMMC_CLK", + "EMMC_DAT3", + "EMMC_DAT2", + "EMMC_DAT1", + "EMMC_DAT0", + "EMMC_DSL", + "", + "", + "", + "", + "", + "", + "", + "", + "USB3_HUB_RST_L", + "EC_AP_RSVD0_ODL", + "", + "", + "SPMI_SCL", + "SPMI_SDA"; + + audio_codec_pins: audio-codec-pins { + pins-hp-int-odl { + pinmux =3D ; + input-enable; + }; + }; + + speaker_en: speaker-en-pins { + pins-en-spkr { + pinmux =3D ; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi b/arch/arm64/b= oot/dts/mediatek/mt8188-geralt.dtsi new file mode 100644 index 000000000000..b6abecbcfa81 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi @@ -0,0 +1,1156 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + */ +/dts-v1/; +#include +#include "mt8188.dtsi" +#include "mt6359.dtsi" + +/ { + aliases { + i2c0 =3D &i2c0; + i2c1 =3D &i2c1; + i2c2 =3D &i2c2; + i2c3 =3D &i2c3; + i2c4 =3D &i2c4; + i2c5 =3D &i2c5; + i2c6 =3D &i2c6; + mmc0 =3D &mmc0; + serial0 =3D &uart0; + }; + + backlight_lcd0: backlight-lcd0 { + compatible =3D "pwm-backlight"; + brightness-levels =3D <0 1023>; + default-brightness-level =3D <576>; + enable-gpios =3D <&pio 1 GPIO_ACTIVE_HIGH>; + num-interpolated-steps =3D <1023>; + power-supply =3D <&ppvar_sys>; + pwms =3D <&disp_pwm0 0 500000>; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + dmic-codec { + compatible =3D "dmic-codec"; + num-channels =3D <2>; + wakeup-delay-ms =3D <100>; + }; + + memory@40000000 { + device_type =3D "memory"; + /* The size will be filled in by the bootloader */ + reg =3D <0 0x40000000 0 0>; + }; + + /* system wide LDO 1.8V power rail */ + pp1800_ldo_z1: regulator-pp1800-ldo-z1 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp1800_ldo_z1"; + /* controlled by PP3300_Z1 */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&pp3300_z1>; + }; + + /* separately switched 3.3V power rail */ + pp3300_s3: regulator-pp3300-s3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp3300_s3"; + /* controlled by PMIC */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&pp3300_z1>; + }; + + /* system wide 3.3V power rail */ + pp3300_z1: regulator-pp3300-z1 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp3300_z1"; + /* controlled by PP3300_LDO_Z5 & EN_PWR_Z1 */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&ppvar_sys>; + }; + + pp3300_wlan: regulator-pp3300-wlan { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp3300_wlan"; + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + enable-active-high; + gpio =3D <&pio 12 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&wlan_en>; + pinctrl-names =3D "default"; + vin-supply =3D <&pp3300_z1>; + }; + + /* system wide 4.2V power rail */ + pp4200_s5: regulator-pp4200-s5 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp4200_s5"; + /* controlled by EC */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <4200000>; + regulator-max-microvolt =3D <4200000>; + vin-supply =3D <&ppvar_sys>; + }; + + /* system wide 5.0V power rail */ + pp5000_z1: regulator-pp5000-z1 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp5000_z1"; + /* controlled by EC */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&ppvar_sys>; + }; + + pp5000_usb_vbus: regulator-pp5000-usb-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp5000_usb_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&pio 150 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&pp5000_z1>; + }; + + /* system wide semi-regulated power rail from battery or USB */ + ppvar_sys: regulator-ppvar-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "ppvar_sys"; + regulator-always-on; + regulator-boot-on; + }; + + ppvar_mipi_disp_avdd: regulator-ppvar-mipi-disp-avdd { + compatible =3D "regulator-fixed"; + regulator-name =3D "ppvar_mipi_disp_avdd"; + enable-active-high; + gpio =3D <&pio 3 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mipi_disp_avdd_en>; + vin-supply =3D <&pp5000_z1>; + }; + + ppvar_mipi_disp_avee: regulator-ppvar-mipi-disp-avee { + compatible =3D "regulator-fixed"; + regulator-name =3D "ppvar_mipi_disp_avee"; + regulator-enable-ramp-delay =3D <10000>; + enable-active-high; + gpio =3D <&pio 4 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mipi_disp_avee_en>; + vin-supply =3D <&pp5000_z1>; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + apu_mem: memory@55000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x55000000 0 0x1400000>; + }; + + adsp_mem: memory@60000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x60000000 0 0xf00000>; + no-map; + }; + + afe_dma_mem: memory@60f00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x60f00000 0 0x100000>; + no-map; + }; + + adsp_dma_mem: memory@61000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x61000000 0 0x100000>; + no-map; + }; + }; +}; + +&adsp { + memory-region =3D <&adsp_dma_mem>, <&adsp_mem>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&adsp_uart_pins>; + status =3D "okay"; +}; + +&afe { + memory-region =3D <&afe_dma_mem>; + mediatek,etdm-out1-cowork-source =3D <0>; /* in1 */ + mediatek,etdm-in2-cowork-source =3D <3>; /* out2 */ + status =3D "okay"; +}; + +&auxadc { + status =3D "okay"; +}; + +&cam_vcore { + domain-supply =3D <&mt6359_vproc1_buck_reg>; +}; + +/* + * Geralt is the reference design and doesn't have target TDP. + * Ciri is (currently) the only device following Geralt, and its + * TDP target is 90 degrees. + **/ +&cpu_little0_alert0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; +}; + +&cpu_little1_alert0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; +}; + +&cpu_little2_alert0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; +}; + +&cpu_little3_alert0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; +}; + +&cpu_big0_alert0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; +}; + +&cpu_big1_alert0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; +}; + +&disp_dsi0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + dsi_panel: panel@0 { + /* Compatible string for different panels can be found in each device dt= s */ + reg =3D <0>; + enable-gpios =3D <&pio 25 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mipi_dsi_pins>; + + backlight =3D <&backlight_lcd0>; + avdd-supply =3D <&ppvar_mipi_disp_avdd>; + avee-supply =3D <&ppvar_mipi_disp_avee>; + pp1800-supply =3D <&mt6359_vm18_ldo_reg>; + rotation =3D <270>; + + status =3D "okay"; + + port { + dsi_panel_in: endpoint { + remote-endpoint =3D <&dsi_out>; + }; + }; + }; + + port { + dsi_out: endpoint { + remote-endpoint =3D <&dsi_panel_in>; + }; + }; +}; + +&disp_pwm0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&disp_pwm0_pins>; + status =3D "okay"; +}; + +&disp_pwm1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&disp_pwm1_pins>; +}; + +&dp_intf1 { + status =3D "okay"; + + port { + dp_intf1_out: endpoint { + remote-endpoint =3D <&dptx_in>; + }; + }; +}; + +&dp_tx { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&dp_tx_hpd>; + #sound-dai-cells =3D <0>; + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dptx_in: endpoint { + remote-endpoint =3D <&dp_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + dptx_out: endpoint { + data-lanes =3D <0 1 2 3>; + }; + }; + }; +}; + +&gpu { + mali-supply =3D <&mt6359_vproc2_buck_reg>; + status =3D "okay"; +}; + +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; + + tpm@50 { + compatible =3D "google,cr50"; + reg =3D <0x50>; + interrupts-extended =3D <&pio 0 IRQ_TYPE_EDGE_RISING>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gsc_int>; + }; +}; + +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&i2c3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&i2c4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c4_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&i2c5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c5_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&i2c6 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c6_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&mfg0 { + domain-supply =3D <&mt6359_vproc2_buck_reg>; +}; + +&mfg1 { + domain-supply =3D <&mt6359_vsram_others_ldo_reg>; +}; + +&mipi_tx_config0 { + status =3D "okay"; +}; + +&mmc0 { + bus-width =3D <8>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + hs400-ds-delay =3D <0x1481b>; + max-frequency =3D <200000000>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sd; + no-sdio; + non-removable; + pinctrl-names =3D "default", "state_uhs"; + pinctrl-0 =3D <&mmc0_pins_default>; + pinctrl-1 =3D <&mmc0_pins_uhs>; + supports-cqe; + vmmc-supply =3D <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply =3D <&mt6359_vufs_ldo_reg>; + status =3D "okay"; +}; + +&mt6359codec { + mediatek,dmic-mode =3D <1>; /* one-wire */ + mediatek,mic-type-0 =3D <2>; /* DMIC */ + mediatek,mic-type-2 =3D <2>; /* DMIC */ +}; + +&mt6359_vcore_buck_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_sshub_buck_reg { + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <550000>; + regulator-always-on; +}; + +&mt6359_vio28_ldo_reg { + /delete-property/ regulator-always-on; +}; + +&mt6359_vm18_ldo_reg { + /delete-property/ regulator-always-on; +}; + +&mt6359_vmodem_buck_reg { + regulator-min-microvolt =3D <775000>; + regulator-max-microvolt =3D <775000>; +}; + +&mt6359_vpa_buck_reg { + regulator-max-microvolt =3D <3100000>; +}; + +&mt6359_vproc2_buck_reg { + /* + * Called "ppvar_dvdd_gpu" in the schematic. Renamed to + * "ppvar_dvdd_vgpu" here to match mtk-regulator-coupler requirements. + */ + regulator-name =3D "ppvar_dvdd_vgpu"; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <800000>; + regulator-coupled-with =3D <&mt6359_vsram_others_ldo_reg>; + regulator-coupled-max-spread =3D <6250>; +}; + +&mt6359_vpu_buck_reg { + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-always-on; +}; + +&mt6359_vsram_md_ldo_reg { + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <800000>; +}; + +&mt6359_vsram_others_ldo_reg { + regulator-name =3D "pp0850_dvdd_sram_gpu"; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <800000>; + regulator-coupled-with =3D <&mt6359_vproc2_buck_reg>; + regulator-coupled-max-spread =3D <6250>; +}; + +&mt6359_vufs_ldo_reg { + regulator-always-on; +}; + +&nor_flash { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&nor_pins>; + status =3D "okay"; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <52000000>; + }; +}; + +&pcie { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie_pins>; + status =3D "okay"; +}; + +&pciephy { + status =3D "okay"; +}; + +&pio { + gpio-line-names =3D + "gsc_int", + "AP_DISP_BKLTEN", + "", + "EN_PPVAR_MIPI_DISP", + "EN_PPVAR_MIPI_DISP_150MA", + "TCHSCR_RST_1V8_L", + "TCHSRC_REPORT_DISABLE", + "", + "", + "", + "", + "I2S_SPKR_DATAOUT", + "EN_PP3300_WLAN_X", + "WIFI_KILL_1V8_L", + "BT_KILL_1V8_L", + "AP_FLASH_WP_L", /* ... is crossystem ABI. Rev1 schematics call it AP_WP= _ODL. */ + "", + "EDP_HPD_1V8", + "WCAM_PWDN_L", + "WCAM_RST_L", + "UCAM_PWDM_L", + "UCAM_RST_L", + "WCAM_24M_CLK", + "UCAM_24M_CLK", + "MT6319_INT", + "DISP_RST_1V8_L", + "DSIO_DSI_TE", + "EN_PP3300_EDP_DISP_X", + "TP", + "MIPI_BL_PWM_1V8", + "EDP_BL_PWM_1V8", + "UART_AP_TX_GSC_RX", + "UART_GSC_TX_AP_RX", + "UART_SSPM_TX_DBGCON_RX", + "UART_DBGCON_TX_SSPM_RX", + "UART_ADSP_TX_DBGCON_RX", + "UART_DBGCON_TX_ADSP_RX", + "JTAG_AP_TMS", + "JTAG_AP_TCK", + "JTAG_AP_TDI", + "JTAG_AP_TDO", + "JTAG_AP_TRST", + "AP_KPCOL0", + "TP", + "BEEP_ON_OD", + "TP", + "EC_AP_HPD_OD", + "PCIE_WAKE_1V8_ODL", + "PCIE_RST_1V8_L", + "PCIE_CLKREQ_1V8_ODL", + "", + "", + "", + "", + "", + "AP_I2C_AUD_SCL_1V8", + "AP_I2C_AUD_SDA_1V8", + "AP_I2C_TPM_SCL_1V8", + "AP_I2C_TPM_SDA_1V8", + "AP_I2C_TCHSCR_SCL_1V8", + "AP_I2C_TCHSCR_SDA_1V8", + "AP_I2C_PMIC_SAR_SCL_1V8", + "AP_I2C_PMIC_SAR_SDA_1V8", + "AP_I2C_EC_HID_KB_SCL_1V8", + "AP_I2C_EC_HID_KB_SDA_1V8", + "AP_I2C_UCAM_SCL_1V8", + "AP_I2C_UCAM_SDA_1V8", + "AP_I2C_WCAM_SCL_1V8", + "AP_I2C_WCAM_SDA_1V8", + "SPI_AP_CS_EC_L", + "SPI_AP_CLK_EC", + "SPI_AP_DO_EC_DI", + "SPI_AP_DI_EC_DO", + "TP", + "TP", + "SPI_AP_CS_TCHSCR_L", + "SPI_AP_CLK_TCHSCR", + "SPI_AP_DO_TCHSCR_DI", + "SPI_AP_DI_TCHSCR_DO", + "TP", + "TP", + "TP", + "TP", + "", + "", + "", + "TP", + "", + "SAR_INT_ODL", + "", + "", + "", + "PWRAP_SPI_CS_L", + "PWRAP_SPI_CK", + "PWRAP_SPI_MOSI", + "PWRAP_SPI_MISO", + "SRCLKENA0", + "SRCLKENA1", + "SCP_VREQ_VAO", + "AP_RTC_CLK32K", + "AP_PMIC_WDTRST_L", + "AUD_CLK_MOSI", + "AUD_SYNC_MOSI", + "AUD_DAT_MOSI0", + "AUD_DAT_MOSI1", + "AUD_DAT_MISO0", + "AUD_DAT_MISO1", + "SD_CD_ODL", + "HP_INT_ODL", + "SPKR_INT_ODL", + "I2S_HP_DATAIN", + "EN_SPKR", + "I2S_SPKR_MCLK", + "I2S_SPKR_BCLK", + "I2S_HP_MCLK", + "I2S_HP_BCLK", + "I2S_HP_LRCK", + "I2S_HP_DATAOUT", + "RST_SPKR_L", + "I2S_SPKR_LRCK", + "I2S_SPKR_DATAIN", + "", + "", + "", + "", + "SPI_AP_CLK_ROM", + "SPI_AP_CS_ROM_L", + "SPI_AP_DO_ROM_DI", + "SPI_AP_DI_ROM_DO", + "TP", + "TP", + "", + "", + "", + "", + "", + "", + "", + "", + "EN_PP2800A_UCAM_X", + "EN_PP1200_UCAM_X", + "EN_PP2800A_WCAM_X", + "EN_PP1100_WCAM_X", + "TCHSCR_INT_1V8_L", + "EN_PP3300_MIPI_TCHSCR_X", + "MT7921_PMU_EN_1V8", + "EN_PP3300_EDP_TCHSCR_X", + "AP_EC_WARM_RST_REQ", + "EC_AP_HID_INT_ODL", + "EC_AP_INT_ODL", + "AP_XHCI_INIT_DONE", + "EMMC_DAT7", + "EMMC_DAT6", + "EMMC_DAT5", + "EMMC_DAT4", + "EMMC_RST_L", + "EMMC_CMD", + "EMMC_CLK", + "EMMC_DAT3", + "EMMC_DAT2", + "EMMC_DAT1", + "EMMC_DAT0", + "EMMC_DSL", + "SD_CMD", + "SD_CLK", + "SD_DAT0", + "SD_DAT1", + "SD_DAT2", + "SD_DAT3", + "", + "", + "USB3_HUB_RST_L", + "EC_AP_RSVD0_ODL", + "", + "", + "SPMI_SCL", + "SPMI_SDA"; + + adsp_uart_pins: adsp-uart-pins { + pins-bus { + pinmux =3D , + ; + }; + }; + + aud_etdm_hp_on: aud-etdm-hp-on-pins { + pins-bus { + pinmux =3D , + , + , + ; + }; + }; + + aud_etdm_hp_off: aud-etdm-hp-off-pins { + pins-bus { + pinmux =3D , + , + , + ; + bias-pull-down; + input-enable; + }; + }; + + aud_etdm_spk_on: aud-etdm-spk-on-pins { + pins-bus { + pinmux =3D , + , + , + ; + drive-strength =3D <8>; + }; + }; + + aud_etdm_spk_off: aud-etdm-spk-off-pins { + pins-bus { + pinmux =3D , + , + , + ; + bias-pull-down; + input-enable; + }; + }; + + aud_mtkaif_on: aud-mtkaif-on-pins { + pins-bus { + pinmux =3D , + , + , + , + , + ; + }; + }; + + aud_mtkaif_off: aud-mtkaif-off-pins { + pins-bus { + pinmux =3D , + , + , + , + , + ; + bias-pull-down; + input-enable; + }; + }; + + cros_ec_int: cros-ec-int-pins { + pins-ec-ap-int-odl { + pinmux =3D ; + input-enable; + }; + }; + + disp_pwm0_pins: disp-pwm0-pins { + pins-disp-pwm0 { + pinmux =3D ; + output-high; + }; + }; + + disp_pwm1_pins: disp-pwm1-pins { + pins-disp-pwm1 { + pinmux =3D ; + output-high; + }; + }; + + dp_tx_hpd: dp-tx-hpd-pins { + pins-dp-tx-hpd { + pinmux =3D ; + }; + }; + + gsc_int: gsc-int-pins { + pins-gsc-ap-int-odl { + pinmux =3D ; + input-enable; + }; + }; + + i2c0_pins: i2c0-pins { + pins-bus { + pinmux =3D , + ; + }; + }; + + i2c1_pins: i2c1-pins { + pins-bus { + pinmux =3D , + ; + }; + }; + + i2c2_pins: i2c2-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + drive-strength =3D <12>; + }; + }; + + i2c3_pins: i2c3-pins { + pins-bus { + pinmux =3D , + ; + }; + }; + + i2c4_pins: i2c4-pins { + pins-bus { + pinmux =3D , + ; + }; + }; + + i2c5_pins: i2c5-pins { + pins-bus { + pinmux =3D , + ; + }; + }; + + i2c6_pins: i2c6-pins { + pins-bus { + pinmux =3D , + ; + }; + }; + + mipi_disp_avdd_en: mipi-disp-avdd-en-pins { + pins-en-ppvar-mipi-disp { + pinmux =3D ; + output-low; + }; + }; + + mipi_disp_avee_en: mipi-disp-avee-en-pins { + pins-en-ppvar-mipi-disp-150ma { + pinmux =3D ; + output-low; + }; + }; + + mipi_dsi_pins: mipi-dsi-pins { + pins-bus { + pinmux =3D , + ; + output-low; + }; + }; + + mmc0_pins_default: mmc0-default-pins { + pins-bus { + pinmux =3D , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength =3D <6>; + bias-pull-up =3D ; + }; + + pins-clk { + pinmux =3D ; + drive-strength =3D <6>; + bias-pull-down =3D ; + }; + + pins-rst { + pinmux =3D ; + drive-strength =3D <6>; + bias-pull-up =3D ; + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + pins-bus { + pinmux =3D , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength =3D <8>; + bias-pull-up =3D ; + }; + + pins-clk { + pinmux =3D ; + drive-strength =3D <8>; + bias-pull-down =3D ; + }; + + pins-ds { + pinmux =3D ; + drive-strength =3D <8>; + bias-pull-down =3D ; + }; + + pins-rst { + pinmux =3D ; + drive-strength =3D <8>; + bias-pull-up =3D ; + }; + }; + + nor_pins: nor-default-pins { + pins-clk { + pinmux =3D , + , + ; + bias-pull-down; + }; + + pins-cs { + pinmux =3D ; + bias-pull-up; + }; + }; + + pcie_pins: pcie-default-pins { + pins-bus { + pinmux =3D , + , + ; + }; + }; + + spi0_pins: spi0-pins { + pins-bus { + pinmux =3D , + , + , + ; + bias-disable; + }; + }; + + spi1_pins_default: spi1-default-pins { + pins-bus { + pinmux =3D , + , + , + ; + bias-disable; + }; + }; + + spi1_pins_sleep: spi1-sleep-pins { + pins-bus { + pinmux =3D , + , + , + ; + bias-pull-down; + input-enable; + }; + }; + + spi2_pins: spi2-pins { + pins-bus { + pinmux =3D , + , + , + ; + bias-disable; + }; + }; + + uart0_pins: uart0-pins { + pins-bus { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + wlan_en: wlan-en-pins { + pins-en-pp3300-wlan { + pinmux =3D ; + output-low; + }; + }; +}; + +&pmic { + interrupts-extended =3D <&pio 222 IRQ_TYPE_LEVEL_HIGH>; +}; + +&sound { + pinctrl-names =3D "aud_etdm_hp_on", "aud_etdm_hp_off", + "aud_etdm_spk_on", "aud_etdm_spk_off", + "aud_mtkaif_on", "aud_mtkaif_off"; + pinctrl-0 =3D <&aud_etdm_hp_on>; + pinctrl-1 =3D <&aud_etdm_hp_off>; + pinctrl-2 =3D <&aud_etdm_spk_on>; + pinctrl-3 =3D <&aud_etdm_spk_off>; + pinctrl-4 =3D <&aud_mtkaif_on>; + pinctrl-5 =3D <&aud_mtkaif_off>; + mediatek,adsp =3D <&adsp>; + /* The audio-routing is defined in each board dts */ + + status =3D "okay"; +}; + +&spi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi0_pins>; + status =3D "okay"; + + cros_ec: ec@0 { + compatible =3D "google,cros-ec-spi"; + reg =3D <0>; + interrupts-extended =3D <&pio 149 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cros_ec_int>; + spi-max-frequency =3D <3000000>; + + i2c_tunnel: i2c-tunnel { + compatible =3D "google,cros-ec-i2c-tunnel"; + google,remote-bus =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cbas { + compatible =3D "google,cros-cbas"; + }; + }; +}; + +&spi1 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&spi1_pins_default>; + pinctrl-1 =3D <&spi1_pins_sleep>; + status =3D "okay"; +}; + +&spi2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi2_pins>; + status =3D "okay"; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pins>; + status =3D "okay"; +}; + +&u3phy0 { + status =3D "okay"; +}; + +&u3phy1 { + status =3D "okay"; +}; + +&u3phy2 { + status =3D "okay"; +}; + +/* USB detachable base */ +&xhci0 { + /* controlled by EC */ + vbus-supply =3D <&pp3300_z1>; + status =3D "okay"; +}; + +/* USB3 hub */ +&xhci1 { + vusb33-supply =3D <&pp3300_s3>; + vbus-supply =3D <&pp5000_usb_vbus>; + status =3D "okay"; +}; + +/* USB BT */ +&xhci2 { + /* no power supply since MT7921's power is controlled by PCIe */ + /* MT7921's USB BT has issues with USB2 LPM */ + usb2-lpm-disable; + status =3D "okay"; +}; + +#include + +&keyboard_controller { + function-row-physmap =3D < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + + linux,keymap =3D < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x01, 0x04, KEY_MICMUTE) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + CROS_STD_MAIN_KEYMAP + >; +}; --=20 2.47.0.371.ga323438b13-goog