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Sat, 23 Nov 2024 14:01:52 -0800 (PST) Received: from newman.cs.purdue.edu ([128.10.127.250]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6d451b4a0a5sm25789426d6.106.2024.11.23.14.01.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Nov 2024 14:01:51 -0800 (PST) From: Jiasheng Jiang To: jic23@kernel.org Cc: dlechner@baylibre.com, lars@metafoo.de, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, u.kleine-koenig@baylibre.com, tgamblin@baylibre.com, fabrice.gasnier@st.com, benjamin.gaignard@linaro.org, lee@kernel.org, linux-iio@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jiasheng Jiang Subject: [PATCH v5] iio: trigger: stm32-timer-trigger: Add check for clk_enable() Date: Sat, 23 Nov 2024 22:01:49 +0000 Message-Id: <20241123220149.30655-1-jiashengjiangcool@gmail.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add check for the return value of clk_enable() in order to catch the potential exception. Reviewed-by: David Lechner Signed-off-by: Jiasheng Jiang --- Changelog: v4 -> v5: 1. Add a default in the switch. v3 -> v4: 1. Place braces around the case body. v2 -> v3: 1. Use guard() to simplify the resulting code. v1 -> v2: 1. Remove unsuitable dev_err_probe(). --- drivers/iio/trigger/stm32-timer-trigger.c | 49 ++++++++++++++--------- 1 file changed, 29 insertions(+), 20 deletions(-) diff --git a/drivers/iio/trigger/stm32-timer-trigger.c b/drivers/iio/trigge= r/stm32-timer-trigger.c index 0684329956d9..67528ec7d0a5 100644 --- a/drivers/iio/trigger/stm32-timer-trigger.c +++ b/drivers/iio/trigger/stm32-timer-trigger.c @@ -119,7 +119,7 @@ static int stm32_timer_start(struct stm32_timer_trigger= *priv, unsigned int frequency) { unsigned long long prd, div; - int prescaler =3D 0; + int prescaler =3D 0, ret; u32 ccer; =20 /* Period and prescaler values depends of clock rate */ @@ -150,10 +150,12 @@ static int stm32_timer_start(struct stm32_timer_trigg= er *priv, if (ccer & TIM_CCER_CCXE) return -EBUSY; =20 - mutex_lock(&priv->lock); + guard(mutex)(&priv->lock); if (!priv->enabled) { priv->enabled =3D true; - clk_enable(priv->clk); + ret =3D clk_enable(priv->clk); + if (ret) + return ret; } =20 regmap_write(priv->regmap, TIM_PSC, prescaler); @@ -173,7 +175,6 @@ static int stm32_timer_start(struct stm32_timer_trigger= *priv, =20 /* Enable controller */ regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); - mutex_unlock(&priv->lock); =20 return 0; } @@ -307,7 +308,7 @@ static ssize_t stm32_tt_store_master_mode(struct device= *dev, struct stm32_timer_trigger *priv =3D dev_get_drvdata(dev); struct iio_trigger *trig =3D to_iio_trigger(dev); u32 mask, shift, master_mode_max; - int i; + int i, ret; =20 if (stm32_timer_is_trgo2_name(trig->name)) { mask =3D TIM_CR2_MMS2; @@ -322,15 +323,16 @@ static ssize_t stm32_tt_store_master_mode(struct devi= ce *dev, for (i =3D 0; i <=3D master_mode_max; i++) { if (!strncmp(master_mode_table[i], buf, strlen(master_mode_table[i]))) { - mutex_lock(&priv->lock); + guard(mutex)(&priv->lock); if (!priv->enabled) { /* Clock should be enabled first */ priv->enabled =3D true; - clk_enable(priv->clk); + ret =3D clk_enable(priv->clk); + if (ret) + return ret; } regmap_update_bits(priv->regmap, TIM_CR2, mask, i << shift); - mutex_unlock(&priv->lock); return len; } } @@ -482,6 +484,7 @@ static int stm32_counter_write_raw(struct iio_dev *indi= o_dev, int val, int val2, long mask) { struct stm32_timer_trigger *priv =3D iio_priv(indio_dev); + int ret; =20 switch (mask) { case IIO_CHAN_INFO_RAW: @@ -491,12 +494,14 @@ static int stm32_counter_write_raw(struct iio_dev *in= dio_dev, /* fixed scale */ return -EINVAL; =20 - case IIO_CHAN_INFO_ENABLE: - mutex_lock(&priv->lock); + case IIO_CHAN_INFO_ENABLE: { + guard(mutex)(&priv->lock); if (val) { if (!priv->enabled) { priv->enabled =3D true; - clk_enable(priv->clk); + ret =3D clk_enable(priv->clk); + if (ret) + return ret; } regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); } else { @@ -506,11 +511,12 @@ static int stm32_counter_write_raw(struct iio_dev *in= dio_dev, clk_disable(priv->clk); } } - mutex_unlock(&priv->lock); + return 0; } - - return -EINVAL; + default: + return -EINVAL; + } } =20 static int stm32_counter_validate_trigger(struct iio_dev *indio_dev, @@ -601,7 +607,7 @@ static int stm32_set_enable_mode(struct iio_dev *indio_= dev, unsigned int mode) { struct stm32_timer_trigger *priv =3D iio_priv(indio_dev); - int sms =3D stm32_enable_mode2sms(mode); + int sms =3D stm32_enable_mode2sms(mode), ret; =20 if (sms < 0) return sms; @@ -609,12 +615,15 @@ static int stm32_set_enable_mode(struct iio_dev *indi= o_dev, * Triggered mode sets CEN bit automatically by hardware. So, first * enable counter clock, so it can use it. Keeps it in sync with CEN. */ - mutex_lock(&priv->lock); - if (sms =3D=3D 6 && !priv->enabled) { - clk_enable(priv->clk); - priv->enabled =3D true; + scoped_guard(mutex, &priv->lock) { + if (sms =3D=3D 6 && !priv->enabled) { + ret =3D clk_enable(priv->clk); + if (ret) + return ret; + + priv->enabled =3D true; + } } - mutex_unlock(&priv->lock); =20 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms); =20 --=20 2.25.1