From nobody Sun Nov 24 06:51:17 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2994337171; Sat, 23 Nov 2024 07:01:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732345292; cv=none; b=Qdio1gqZh4eNCDFdSDrfD2PqEYELxMs3rtWJKcQJoj9QD3lXkJ+cvM9u4Ksgpm/U1JT73WunU/t/ahpH/mqqGfKBj+a4yqnYcw2Kyhs/BmMR5+38QUmuAt5z8xoQAIhfKfyTh8zZbsWZ03g8WSKIU2xps2Hwa37oRi3z9Jyi76Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732345292; c=relaxed/simple; bh=eLUZRvzAb/JMAqXqi3XSFoRGRNFvuqn37EsysAuIq7I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=aFZNrU3NeQD5nDS6UB+qjkBlHHQUq4veIQ8LGow53XKwQckWcljoKmwn7k8ikIZEoYE+M0rrGREYfEUgtVg9QV2sMuTP8HwHM9XRJsElvN0hsjhotsfexIV5j+6osABv2kWZM/EztwuulZ/7pp3aFprnpSe6yhL+CElKDvsUWxg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Tq5juvSF; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Tq5juvSF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1732345291; x=1763881291; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eLUZRvzAb/JMAqXqi3XSFoRGRNFvuqn37EsysAuIq7I=; b=Tq5juvSFJtZoG+LWAuv46El/Hbrq44nUhemPbGmWiEmYy5OTSq5m1Qad IPAMLnR1rFYnS/N0Z7D3Tk0y5OdyokYbTC2qzZxEP93kTrQ+G2Wc51Yt1 Jz+h53e83ACs1SVN9kLeHZaPKZojI83K/9++Cjp5fBk7YMnJ3QHOmI9bX 6gz0Vvn+sFb7vhmDhZuK3KIcMN3mrqy1rD3cdBGsmGWfz2D2YNMbEIg2J l3AejDupT12OvB7tAia97lXRM+pvTnH7RCp0GmhiGRbEM9mYGDEjamknE rRYzrkKgkDClAJTMdQlay7AKZyGZcATg9XFfwit2xI8pj1RV31AhjvG9v Q==; X-CSE-ConnectionGUID: tjQvXiUTS3GOOX1Sz4AhCg== X-CSE-MsgGUID: 1tGfB3c3QRuU+gRht0pspA== X-IronPort-AV: E=McAfee;i="6700,10204,11264"; a="32435459" X-IronPort-AV: E=Sophos;i="6.12,178,1728975600"; d="scan'208";a="32435459" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Nov 2024 23:01:28 -0800 X-CSE-ConnectionGUID: nicOeVJqS2iI9cBEFnDBKg== X-CSE-MsgGUID: +RhtWcv3QkidP9LiFSjxvw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,178,1728975600"; d="scan'208";a="91573547" Received: from unknown (HELO JF5300-B11A338T.jf.intel.com) ([10.242.51.115]) by orviesa008.jf.intel.com with ESMTP; 22 Nov 2024 23:01:28 -0800 From: Kanchana P Sridhar To: linux-kernel@vger.kernel.org, linux-mm@kvack.org, hannes@cmpxchg.org, yosryahmed@google.com, nphamcs@gmail.com, chengming.zhou@linux.dev, usamaarif642@gmail.com, ryan.roberts@arm.com, ying.huang@intel.com, 21cnbao@gmail.com, akpm@linux-foundation.org, linux-crypto@vger.kernel.org, herbert@gondor.apana.org.au, davem@davemloft.net, clabbe@baylibre.com, ardb@kernel.org, ebiggers@google.com, surenb@google.com, kristen.c.accardi@intel.com Cc: wajdi.k.feghali@intel.com, vinodh.gopal@intel.com, kanchana.p.sridhar@intel.com Subject: [PATCH v4 01/10] crypto: acomp - Define two new interfaces for compress/decompress batching. Date: Fri, 22 Nov 2024 23:01:18 -0800 Message-Id: <20241123070127.332773-2-kanchana.p.sridhar@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20241123070127.332773-1-kanchana.p.sridhar@intel.com> References: <20241123070127.332773-1-kanchana.p.sridhar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This commit adds batch_compress() and batch_decompress() interfaces to: struct acomp_alg struct crypto_acomp This allows the iaa_crypto Intel IAA driver to register implementations for the batch_compress() and batch_decompress() API, that can subsequently be invoked from the kernel zswap/zram swap modules to compress/decompress up to CRYPTO_BATCH_SIZE (i.e. 8) pages in parallel in the IAA hardware accelerator to improve swapout/swapin performance. A new helper function acomp_has_async_batching() can be invoked to query if a crypto_acomp has registered these batch_compress and batch_decompress interfaces. Signed-off-by: Kanchana P Sridhar --- crypto/acompress.c | 2 + include/crypto/acompress.h | 91 +++++++++++++++++++++++++++++ include/crypto/internal/acompress.h | 16 +++++ 3 files changed, 109 insertions(+) diff --git a/crypto/acompress.c b/crypto/acompress.c index 6fdf0ff9f3c0..a506db499a37 100644 --- a/crypto/acompress.c +++ b/crypto/acompress.c @@ -71,6 +71,8 @@ static int crypto_acomp_init_tfm(struct crypto_tfm *tfm) =20 acomp->compress =3D alg->compress; acomp->decompress =3D alg->decompress; + acomp->batch_compress =3D alg->batch_compress; + acomp->batch_decompress =3D alg->batch_decompress; acomp->dst_free =3D alg->dst_free; acomp->reqsize =3D alg->reqsize; =20 diff --git a/include/crypto/acompress.h b/include/crypto/acompress.h index 54937b615239..4252bab3d0e1 100644 --- a/include/crypto/acompress.h +++ b/include/crypto/acompress.h @@ -37,12 +37,20 @@ struct acomp_req { void *__ctx[] CRYPTO_MINALIGN_ATTR; }; =20 +/* + * The max compress/decompress batch size, for crypto algorithms + * that support batch_compress and batch_decompress API. + */ +#define CRYPTO_BATCH_SIZE 8UL + /** * struct crypto_acomp - user-instantiated objects which encapsulate * algorithms and core processing logic * * @compress: Function performs a compress operation * @decompress: Function performs a de-compress operation + * @batch_compress: Function performs a batch compress operation + * @batch_decompress: Function performs a batch decompress operation * @dst_free: Frees destination buffer if allocated inside the * algorithm * @reqsize: Context size for (de)compression requests @@ -51,6 +59,20 @@ struct acomp_req { struct crypto_acomp { int (*compress)(struct acomp_req *req); int (*decompress)(struct acomp_req *req); + void (*batch_compress)(struct acomp_req *reqs[], + struct crypto_wait *wait, + struct page *pages[], + u8 *dsts[], + unsigned int dlens[], + int errors[], + int nr_pages); + void (*batch_decompress)(struct acomp_req *reqs[], + struct crypto_wait *wait, + u8 *srcs[], + struct page *pages[], + unsigned int slens[], + int errors[], + int nr_pages); void (*dst_free)(struct scatterlist *dst); unsigned int reqsize; struct crypto_tfm base; @@ -142,6 +164,13 @@ static inline bool acomp_is_async(struct crypto_acomp = *tfm) CRYPTO_ALG_ASYNC; } =20 +static inline bool acomp_has_async_batching(struct crypto_acomp *tfm) +{ + return (acomp_is_async(tfm) && + (crypto_comp_alg_common(tfm)->base.cra_flags & CRYPTO_ALG_TYPE_ACOMPRESS= ) && + tfm->batch_compress && tfm->batch_decompress); +} + static inline struct crypto_acomp *crypto_acomp_reqtfm(struct acomp_req *r= eq) { return __crypto_acomp_tfm(req->base.tfm); @@ -265,4 +294,66 @@ static inline int crypto_acomp_decompress(struct acomp= _req *req) return crypto_acomp_reqtfm(req)->decompress(req); } =20 +/** + * crypto_acomp_batch_compress() -- Invoke asynchronous compress of + * a batch of requests + * + * Function invokes the asynchronous batch compress operation + * + * @reqs: @nr_pages asynchronous compress requests. + * @wait: crypto_wait for synchronous acomp batch compress. If NULL, the + * driver must provide a way to process completions asynchronously. + * @pages: Pages to be compressed. + * @dsts: Pre-allocated destination buffers to store results of compressio= n. + * @dlens: Will contain the compressed lengths. + * @errors: zero on successful compression of the corresponding + * req, or error code in case of error. + * @nr_pages: The number of pages, up to CRYPTO_BATCH_SIZE, + * to be compressed. + */ +static inline void crypto_acomp_batch_compress(struct acomp_req *reqs[], + struct crypto_wait *wait, + struct page *pages[], + u8 *dsts[], + unsigned int dlens[], + int errors[], + int nr_pages) +{ + struct crypto_acomp *tfm =3D crypto_acomp_reqtfm(reqs[0]); + + return tfm->batch_compress(reqs, wait, pages, dsts, + dlens, errors, nr_pages); +} + +/** + * crypto_acomp_batch_decompress() -- Invoke asynchronous decompress of + * a batch of requests + * + * Function invokes the asynchronous batch decompress operation + * + * @reqs: @nr_pages asynchronous decompress requests. + * @wait: crypto_wait for synchronous acomp batch decompress. If NULL, the + * driver must provide a way to process completions asynchronously. + * @srcs: The src buffers to be decompressed. + * @pages: The pages to store the decompressed buffers. + * @slens: Compressed lengths of @srcs. + * @errors: zero on successful compression of the corresponding + * req, or error code in case of error. + * @nr_pages: The number of pages, up to CRYPTO_BATCH_SIZE, + * to be decompressed. + */ +static inline void crypto_acomp_batch_decompress(struct acomp_req *reqs[], + struct crypto_wait *wait, + u8 *srcs[], + struct page *pages[], + unsigned int slens[], + int errors[], + int nr_pages) +{ + struct crypto_acomp *tfm =3D crypto_acomp_reqtfm(reqs[0]); + + return tfm->batch_decompress(reqs, wait, srcs, pages, + slens, errors, nr_pages); +} + #endif diff --git a/include/crypto/internal/acompress.h b/include/crypto/internal/= acompress.h index 8831edaafc05..acfe2d9d5a83 100644 --- a/include/crypto/internal/acompress.h +++ b/include/crypto/internal/acompress.h @@ -17,6 +17,8 @@ * * @compress: Function performs a compress operation * @decompress: Function performs a de-compress operation + * @batch_compress: Function performs a batch compress operation + * @batch_decompress: Function performs a batch decompress operation * @dst_free: Frees destination buffer if allocated inside the algorithm * @init: Initialize the cryptographic transformation object. * This function is used to initialize the cryptographic @@ -37,6 +39,20 @@ struct acomp_alg { int (*compress)(struct acomp_req *req); int (*decompress)(struct acomp_req *req); + void (*batch_compress)(struct acomp_req *reqs[], + struct crypto_wait *wait, + struct page *pages[], + u8 *dsts[], + unsigned int dlens[], + int errors[], + int nr_pages); + void (*batch_decompress)(struct acomp_req *reqs[], + struct crypto_wait *wait, + u8 *srcs[], + struct page *pages[], + unsigned int slens[], + int errors[], + int nr_pages); void (*dst_free)(struct scatterlist *dst); int (*init)(struct crypto_acomp *tfm); void (*exit)(struct crypto_acomp *tfm); --=20 2.27.0 From nobody Sun Nov 24 06:51:17 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B27A157E99; Sat, 23 Nov 2024 07:01:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732345293; 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22 Nov 2024 23:01:29 -0800 X-CSE-ConnectionGUID: zgZFbcPVTsqJbBTEyVkAlQ== X-CSE-MsgGUID: 2fHdvS1NQqiWAwE+SNwUbA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,178,1728975600"; d="scan'208";a="91573550" Received: from unknown (HELO JF5300-B11A338T.jf.intel.com) ([10.242.51.115]) by orviesa008.jf.intel.com with ESMTP; 22 Nov 2024 23:01:28 -0800 From: Kanchana P Sridhar To: linux-kernel@vger.kernel.org, linux-mm@kvack.org, hannes@cmpxchg.org, yosryahmed@google.com, nphamcs@gmail.com, chengming.zhou@linux.dev, usamaarif642@gmail.com, ryan.roberts@arm.com, ying.huang@intel.com, 21cnbao@gmail.com, akpm@linux-foundation.org, linux-crypto@vger.kernel.org, herbert@gondor.apana.org.au, davem@davemloft.net, clabbe@baylibre.com, ardb@kernel.org, ebiggers@google.com, surenb@google.com, kristen.c.accardi@intel.com Cc: wajdi.k.feghali@intel.com, vinodh.gopal@intel.com, kanchana.p.sridhar@intel.com Subject: [PATCH v4 02/10] crypto: iaa - Add an acomp_req flag CRYPTO_ACOMP_REQ_POLL to enable async mode. Date: Fri, 22 Nov 2024 23:01:19 -0800 Message-Id: <20241123070127.332773-3-kanchana.p.sridhar@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20241123070127.332773-1-kanchana.p.sridhar@intel.com> References: <20241123070127.332773-1-kanchana.p.sridhar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If the iaa_crypto driver has async_mode set to true, and use_irq set to false, it can still be forced to use synchronous mode by turning off the CRYPTO_ACOMP_REQ_POLL flag in req->flags. All three of the following need to be true for a request to be processed in fully async poll mode: 1) async_mode should be "true" 2) use_irq should be "false" 3) req->flags & CRYPTO_ACOMP_REQ_POLL should be "true" Suggested-by: Herbert Xu Signed-off-by: Kanchana P Sridhar --- drivers/crypto/intel/iaa/iaa_crypto_main.c | 11 ++++++++++- include/crypto/acompress.h | 5 +++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/intel/iaa/iaa_crypto_main.c b/drivers/crypto/in= tel/iaa/iaa_crypto_main.c index 237f87000070..2edaecd42cc6 100644 --- a/drivers/crypto/intel/iaa/iaa_crypto_main.c +++ b/drivers/crypto/intel/iaa/iaa_crypto_main.c @@ -1510,6 +1510,10 @@ static int iaa_comp_acompress(struct acomp_req *req) return -EINVAL; } =20 + /* If the caller has requested no polling, disable async. */ + if (!(req->flags & CRYPTO_ACOMP_REQ_POLL)) + disable_async =3D true; + cpu =3D get_cpu(); wq =3D wq_table_next_wq(cpu); put_cpu(); @@ -1702,6 +1706,7 @@ static int iaa_comp_adecompress(struct acomp_req *req) { struct crypto_tfm *tfm =3D req->base.tfm; dma_addr_t src_addr, dst_addr; + bool disable_async =3D false; int nr_sgs, cpu, ret =3D 0; struct iaa_wq *iaa_wq; struct device *dev; @@ -1717,6 +1722,10 @@ static int iaa_comp_adecompress(struct acomp_req *re= q) return -EINVAL; } =20 + /* If the caller has requested no polling, disable async. */ + if (!(req->flags & CRYPTO_ACOMP_REQ_POLL)) + disable_async =3D true; + if (!req->dst) return iaa_comp_adecompress_alloc_dest(req); =20 @@ -1765,7 +1774,7 @@ static int iaa_comp_adecompress(struct acomp_req *req) req->dst, req->dlen, sg_dma_len(req->dst)); =20 ret =3D iaa_decompress(tfm, req, wq, src_addr, req->slen, - dst_addr, &req->dlen, false); + dst_addr, &req->dlen, disable_async); if (ret =3D=3D -EINPROGRESS) return ret; =20 diff --git a/include/crypto/acompress.h b/include/crypto/acompress.h index 4252bab3d0e1..c1ed47405557 100644 --- a/include/crypto/acompress.h +++ b/include/crypto/acompress.h @@ -14,6 +14,11 @@ #include =20 #define CRYPTO_ACOMP_ALLOC_OUTPUT 0x00000001 +/* + * If set, the driver must have a way to submit the req, then + * poll its completion status for success/error. + */ +#define CRYPTO_ACOMP_REQ_POLL 0x00000002 #define CRYPTO_ACOMP_DST_MAX 131072 =20 /** --=20 2.27.0 From nobody Sun Nov 24 06:51:17 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5419A1632D9; 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a="32435493" X-IronPort-AV: E=Sophos;i="6.12,178,1728975600"; d="scan'208";a="32435493" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Nov 2024 23:01:29 -0800 X-CSE-ConnectionGUID: +9cFtZNpRvepDy39vtdjBA== X-CSE-MsgGUID: Ykq8GXYtQf6rbBjDUFo5yg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,178,1728975600"; d="scan'208";a="91573553" Received: from unknown (HELO JF5300-B11A338T.jf.intel.com) ([10.242.51.115]) by orviesa008.jf.intel.com with ESMTP; 22 Nov 2024 23:01:28 -0800 From: Kanchana P Sridhar To: linux-kernel@vger.kernel.org, linux-mm@kvack.org, hannes@cmpxchg.org, yosryahmed@google.com, nphamcs@gmail.com, chengming.zhou@linux.dev, usamaarif642@gmail.com, ryan.roberts@arm.com, ying.huang@intel.com, 21cnbao@gmail.com, akpm@linux-foundation.org, linux-crypto@vger.kernel.org, herbert@gondor.apana.org.au, davem@davemloft.net, clabbe@baylibre.com, ardb@kernel.org, ebiggers@google.com, surenb@google.com, kristen.c.accardi@intel.com Cc: wajdi.k.feghali@intel.com, vinodh.gopal@intel.com, kanchana.p.sridhar@intel.com Subject: [PATCH v4 03/10] crypto: iaa - Implement batch_compress(), batch_decompress() API in iaa_crypto. Date: Fri, 22 Nov 2024 23:01:20 -0800 Message-Id: <20241123070127.332773-4-kanchana.p.sridhar@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20241123070127.332773-1-kanchana.p.sridhar@intel.com> References: <20241123070127.332773-1-kanchana.p.sridhar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch provides iaa_crypto driver implementations for the newly added crypto_acomp batch_compress() and batch_decompress() interfaces. This allows swap modules such as zswap/zram to invoke batch parallel compression/decompression of pages on systems with Intel IAA, by invoking these API, respectively: crypto_acomp_batch_compress(...); crypto_acomp_batch_decompress(...); This enables zswap_batch_store() compress batching code to be developed in a manner similar to the current single-page synchronous calls to: crypto_acomp_compress(...); crypto_acomp_decompress(...); thereby, facilitating encapsulated and modular hand-off between the kernel zswap/zram code and the crypto_acomp layer. Suggested-by: Yosry Ahmed Suggested-by: Herbert Xu Signed-off-by: Kanchana P Sridhar --- drivers/crypto/intel/iaa/iaa_crypto_main.c | 337 +++++++++++++++++++++ 1 file changed, 337 insertions(+) diff --git a/drivers/crypto/intel/iaa/iaa_crypto_main.c b/drivers/crypto/in= tel/iaa/iaa_crypto_main.c index 2edaecd42cc6..cbf147a3c3cb 100644 --- a/drivers/crypto/intel/iaa/iaa_crypto_main.c +++ b/drivers/crypto/intel/iaa/iaa_crypto_main.c @@ -1797,6 +1797,341 @@ static void compression_ctx_init(struct iaa_compres= sion_ctx *ctx) ctx->use_irq =3D use_irq; } =20 +static int iaa_comp_poll(struct acomp_req *req) +{ + struct idxd_desc *idxd_desc; + struct idxd_device *idxd; + struct iaa_wq *iaa_wq; + struct pci_dev *pdev; + struct device *dev; + struct idxd_wq *wq; + bool compress_op; + int ret; + + idxd_desc =3D req->base.data; + if (!idxd_desc) + return -EAGAIN; + + compress_op =3D (idxd_desc->iax_hw->opcode =3D=3D IAX_OPCODE_COMPRESS); + wq =3D idxd_desc->wq; + iaa_wq =3D idxd_wq_get_private(wq); + idxd =3D iaa_wq->iaa_device->idxd; + pdev =3D idxd->pdev; + dev =3D &pdev->dev; + + ret =3D check_completion(dev, idxd_desc->iax_completion, true, true); + if (ret =3D=3D -EAGAIN) + return ret; + if (ret) + goto out; + + req->dlen =3D idxd_desc->iax_completion->output_size; + + /* Update stats */ + if (compress_op) { + update_total_comp_bytes_out(req->dlen); + update_wq_comp_bytes(wq, req->dlen); + } else { + update_total_decomp_bytes_in(req->slen); + update_wq_decomp_bytes(wq, req->slen); + } + + if (iaa_verify_compress && (idxd_desc->iax_hw->opcode =3D=3D IAX_OPCODE_C= OMPRESS)) { + struct crypto_tfm *tfm =3D req->base.tfm; + dma_addr_t src_addr, dst_addr; + u32 compression_crc; + + compression_crc =3D idxd_desc->iax_completion->crc; + + dma_sync_sg_for_device(dev, req->dst, 1, DMA_FROM_DEVICE); + dma_sync_sg_for_device(dev, req->src, 1, DMA_TO_DEVICE); + + src_addr =3D sg_dma_address(req->src); + dst_addr =3D sg_dma_address(req->dst); + + ret =3D iaa_compress_verify(tfm, req, wq, src_addr, req->slen, + dst_addr, &req->dlen, compression_crc); + } +out: + /* caller doesn't call crypto_wait_req, so no acomp_request_complete() */ + + dma_unmap_sg(dev, req->dst, sg_nents(req->dst), DMA_FROM_DEVICE); + dma_unmap_sg(dev, req->src, sg_nents(req->src), DMA_TO_DEVICE); + + idxd_free_desc(idxd_desc->wq, idxd_desc); + + dev_dbg(dev, "%s: returning ret=3D%d\n", __func__, ret); + + return ret; +} + +static void iaa_set_req_poll( + struct acomp_req *reqs[], + int nr_reqs, + bool set_flag) +{ + int i; + + for (i =3D 0; i < nr_reqs; ++i) { + set_flag ? (reqs[i]->flags |=3D CRYPTO_ACOMP_REQ_POLL) : + (reqs[i]->flags &=3D ~CRYPTO_ACOMP_REQ_POLL); + } +} + +/** + * This API provides IAA compress batching functionality for use by swap + * modules. + * + * @reqs: @nr_pages asynchronous compress requests. + * @wait: crypto_wait for synchronous acomp batch compress. If NULL, the + * completions will be processed asynchronously. + * @pages: Pages to be compressed by IAA in parallel. + * @dsts: Pre-allocated destination buffers to store results of IAA + * compression. Each element of @dsts must be of size "PAGE_SIZE * = 2". + * @dlens: Will contain the compressed lengths. + * @errors: zero on successful compression of the corresponding + * req, or error code in case of error. + * @nr_pages: The number of pages, up to CRYPTO_BATCH_SIZE, + * to be compressed. + */ +static void iaa_comp_acompress_batch( + struct acomp_req *reqs[], + struct crypto_wait *wait, + struct page *pages[], + u8 *dsts[], + unsigned int dlens[], + int errors[], + int nr_pages) +{ + struct scatterlist inputs[CRYPTO_BATCH_SIZE]; + struct scatterlist outputs[CRYPTO_BATCH_SIZE]; + bool compressions_done =3D false; + bool poll =3D (async_mode && !use_irq); + int i; + + BUG_ON(nr_pages > CRYPTO_BATCH_SIZE); + BUG_ON(!poll && !wait); + + if (poll) + iaa_set_req_poll(reqs, nr_pages, true); + else + iaa_set_req_poll(reqs, nr_pages, false); + + /* + * Prepare and submit acomp_reqs to IAA. IAA will process these + * compress jobs in parallel if async-poll mode is enabled. + * If IAA is used in sync mode, the jobs will be processed sequentially + * using "wait". + */ + for (i =3D 0; i < nr_pages; ++i) { + sg_init_table(&inputs[i], 1); + sg_set_page(&inputs[i], pages[i], PAGE_SIZE, 0); + + /* + * Each dst buffer should be of size (PAGE_SIZE * 2). + * Reflect same in sg_list. + */ + sg_init_one(&outputs[i], dsts[i], PAGE_SIZE * 2); + acomp_request_set_params(reqs[i], &inputs[i], + &outputs[i], PAGE_SIZE, dlens[i]); + + /* + * If poll is in effect, submit the request now, and poll for + * a completion status later, after all descriptors have been + * submitted. If polling is not enabled, submit the request + * and wait for it to complete, i.e., synchronously, before + * moving on to the next request. + */ + if (poll) { + errors[i] =3D iaa_comp_acompress(reqs[i]); + + if (errors[i] !=3D -EINPROGRESS) + errors[i] =3D -EINVAL; + else + errors[i] =3D -EAGAIN; + } else { + acomp_request_set_callback(reqs[i], + CRYPTO_TFM_REQ_MAY_BACKLOG, + crypto_req_done, wait); + errors[i] =3D crypto_wait_req(iaa_comp_acompress(reqs[i]), + wait); + if (!errors[i]) + dlens[i] =3D reqs[i]->dlen; + } + } + + /* + * If not doing async compressions, the batch has been processed at + * this point and we can return. + */ + if (!poll) + goto reset_reqs_wait; + + /* + * Poll for and process IAA compress job completions + * in out-of-order manner. + */ + while (!compressions_done) { + compressions_done =3D true; + + for (i =3D 0; i < nr_pages; ++i) { + /* + * Skip, if the compression has already completed + * successfully or with an error. + */ + if (errors[i] !=3D -EAGAIN) + continue; + + errors[i] =3D iaa_comp_poll(reqs[i]); + + if (errors[i]) { + if (errors[i] =3D=3D -EAGAIN) + compressions_done =3D false; + } else { + dlens[i] =3D reqs[i]->dlen; + } + } + } + +reset_reqs_wait: + /* + * For the same 'reqs[]' and 'wait' to be usable by + * iaa_comp_acompress()/iaa_comp_deacompress(): + * Clear the CRYPTO_ACOMP_REQ_POLL bit on the acomp_reqs. + * Reset the crypto_wait "wait" callback to reqs[0]. + */ + iaa_set_req_poll(reqs, nr_pages, false); + acomp_request_set_callback(reqs[0], + CRYPTO_TFM_REQ_MAY_BACKLOG, + crypto_req_done, wait); +} + +/** + * This API provides IAA decompress batching functionality for use by swap + * modules. + * + * @reqs: @nr_pages asynchronous decompress requests. + * @wait: crypto_wait for synchronous acomp batch decompress. If NULL, the + * driver must provide a way to process completions asynchronously. + * @srcs: The src buffers to be decompressed by IAA in parallel. + * @pages: The pages to store the decompressed buffers. + * @slens: Compressed lengths of @srcs. + * @errors: zero on successful compression of the corresponding + * req, or error code in case of error. + * @nr_pages: The number of pages, up to CRYPTO_BATCH_SIZE, + * to be decompressed. + */ +static void iaa_comp_adecompress_batch( + struct acomp_req *reqs[], + struct crypto_wait *wait, + u8 *srcs[], + struct page *pages[], + unsigned int slens[], + int errors[], + int nr_pages) +{ + struct scatterlist inputs[CRYPTO_BATCH_SIZE]; + struct scatterlist outputs[CRYPTO_BATCH_SIZE]; + unsigned int dlens[CRYPTO_BATCH_SIZE]; + bool decompressions_done =3D false; + bool poll =3D (async_mode && !use_irq); + int i; + + BUG_ON(nr_pages > CRYPTO_BATCH_SIZE); + BUG_ON(!poll && !wait); + + if (poll) + iaa_set_req_poll(reqs, nr_pages, true); + else + iaa_set_req_poll(reqs, nr_pages, false); + + /* + * Prepare and submit acomp_reqs to IAA. IAA will process these + * decompress jobs in parallel if async-poll mode is enabled. + * If IAA is used in sync mode, the jobs will be processed sequentially + * using "wait". + */ + for (i =3D 0; i < nr_pages; ++i) { + dlens[i] =3D PAGE_SIZE; + sg_init_one(&inputs[i], srcs[i], slens[i]); + sg_init_table(&outputs[i], 1); + sg_set_page(&outputs[i], pages[i], PAGE_SIZE, 0); + acomp_request_set_params(reqs[i], &inputs[i], + &outputs[i], slens[i], dlens[i]); + /* + * If poll is in effect, submit the request now, and poll for + * a completion status later, after all descriptors have been + * submitted. If polling is not enabled, submit the request + * and wait for it to complete, i.e., synchronously, before + * moving on to the next request. + */ + if (poll) { + errors[i] =3D iaa_comp_adecompress(reqs[i]); + + if (errors[i] !=3D -EINPROGRESS) + errors[i] =3D -EINVAL; + else + errors[i] =3D -EAGAIN; + } else { + acomp_request_set_callback(reqs[i], + CRYPTO_TFM_REQ_MAY_BACKLOG, + crypto_req_done, wait); + errors[i] =3D crypto_wait_req(iaa_comp_adecompress(reqs[i]), + wait); + if (!errors[i]) { + dlens[i] =3D reqs[i]->dlen; + BUG_ON(dlens[i] !=3D PAGE_SIZE); + } + } + } + + /* + * If not doing async decompressions, the batch has been processed at + * this point and we can return. + */ + if (!poll) + goto reset_reqs_wait; + + /* + * Poll for and process IAA decompress job completions + * in out-of-order manner. + */ + while (!decompressions_done) { + decompressions_done =3D true; + + for (i =3D 0; i < nr_pages; ++i) { + /* + * Skip, if the decompression has already completed + * successfully or with an error. + */ + if (errors[i] !=3D -EAGAIN) + continue; + + errors[i] =3D iaa_comp_poll(reqs[i]); + + if (errors[i]) { + if (errors[i] =3D=3D -EAGAIN) + decompressions_done =3D false; + } else { + dlens[i] =3D reqs[i]->dlen; + BUG_ON(dlens[i] !=3D PAGE_SIZE); + } + } + } + +reset_reqs_wait: + /* + * For the same 'reqs[]' and 'wait' to be usable by + * iaa_comp_acompress()/iaa_comp_deacompress(): + * Clear the CRYPTO_ACOMP_REQ_POLL bit on the acomp_reqs. + * Reset the crypto_wait "wait" callback to reqs[0]. + */ + iaa_set_req_poll(reqs, nr_pages, false); + acomp_request_set_callback(reqs[0], + CRYPTO_TFM_REQ_MAY_BACKLOG, + crypto_req_done, wait); +} + static int iaa_comp_init_fixed(struct crypto_acomp *acomp_tfm) { struct crypto_tfm *tfm =3D crypto_acomp_tfm(acomp_tfm); @@ -1822,6 +2157,8 @@ static struct acomp_alg iaa_acomp_fixed_deflate =3D { .compress =3D iaa_comp_acompress, .decompress =3D iaa_comp_adecompress, .dst_free =3D dst_free, + .batch_compress =3D iaa_comp_acompress_batch, + .batch_decompress =3D iaa_comp_adecompress_batch, .base =3D { .cra_name =3D "deflate", .cra_driver_name =3D "deflate-iaa", --=20 2.27.0 From nobody Sun Nov 24 06:51:17 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2DC7316FF4E; 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a="32435496" X-IronPort-AV: E=Sophos;i="6.12,178,1728975600"; d="scan'208";a="32435496" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Nov 2024 23:01:29 -0800 X-CSE-ConnectionGUID: ObQFb837QdKzc06jS1W0Yw== X-CSE-MsgGUID: +0JuenxqTvCxqHgsFnoJTQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,178,1728975600"; d="scan'208";a="91573556" Received: from unknown (HELO JF5300-B11A338T.jf.intel.com) ([10.242.51.115]) by orviesa008.jf.intel.com with ESMTP; 22 Nov 2024 23:01:28 -0800 From: Kanchana P Sridhar To: linux-kernel@vger.kernel.org, linux-mm@kvack.org, hannes@cmpxchg.org, yosryahmed@google.com, nphamcs@gmail.com, chengming.zhou@linux.dev, usamaarif642@gmail.com, ryan.roberts@arm.com, ying.huang@intel.com, 21cnbao@gmail.com, akpm@linux-foundation.org, linux-crypto@vger.kernel.org, herbert@gondor.apana.org.au, davem@davemloft.net, clabbe@baylibre.com, ardb@kernel.org, ebiggers@google.com, surenb@google.com, kristen.c.accardi@intel.com Cc: wajdi.k.feghali@intel.com, vinodh.gopal@intel.com, kanchana.p.sridhar@intel.com Subject: [PATCH v4 04/10] crypto: iaa - Make async mode the default. Date: Fri, 22 Nov 2024 23:01:21 -0800 Message-Id: <20241123070127.332773-5-kanchana.p.sridhar@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20241123070127.332773-1-kanchana.p.sridhar@intel.com> References: <20241123070127.332773-1-kanchana.p.sridhar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch makes it easier for IAA hardware acceleration in the iaa_crypto driver to be loaded by default in the most efficient/recommended "async" mode for parallel compressions/decompressions, namely, asynchronous submission of descriptors, followed by polling for job completions. Earlier, the "sync" mode used to be the default. This way, anyone that wants to use IAA can do so after building the kernel, and without having to go through these steps to use async poll: 1) disable all the IAA device/wq bindings that happen at boot time 2) rmmod iaa_crypto 3) modprobe iaa_crypto 4) echo async > /sys/bus/dsa/drivers/crypto/sync_mode 5) re-run initialization of the IAA devices and wqs Signed-off-by: Kanchana P Sridhar --- drivers/crypto/intel/iaa/iaa_crypto_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/crypto/intel/iaa/iaa_crypto_main.c b/drivers/crypto/in= tel/iaa/iaa_crypto_main.c index cbf147a3c3cb..bd2db0b6f145 100644 --- a/drivers/crypto/intel/iaa/iaa_crypto_main.c +++ b/drivers/crypto/intel/iaa/iaa_crypto_main.c @@ -153,7 +153,7 @@ static DRIVER_ATTR_RW(verify_compress); */ =20 /* Use async mode */ -static bool async_mode; +static bool async_mode =3D true; /* Use interrupts */ static bool use_irq; =20 --=20 2.27.0 From nobody Sun Nov 24 06:51:17 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21CD517D346; Sat, 23 Nov 2024 07:01:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732345294; cv=none; b=AKJZ5YJEYlSjmY4pHqpb8LPiGRPdhS+sbfxys3tgc6RXIOJycVptjnM1/YRcznuhYtaFsxq6IJwTNuQsHEQs7fb7qtC7/A0Qmdf/bwH5u7zAgENfIL21MxTGtJd0Pu0dU58UIZ3bK415qk6pfB5bgOumt4fU2CgzlNQVQUTFemM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732345294; c=relaxed/simple; bh=sUaKs4IKHRtAS2VJ+T+gUebh7+S3mchKFlm9dP1TtUQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fn+3r9TCzm7ksM3MMYhcnHxU9GpRBHg2fHOvzdTxqBJXbFT8FrwW8CHtj3SQwQ3pOwOZfzN+yMJjFf061DpJ1qceJkRNrolm405oK4Eb5kuoJy0b7olWI/OiS8PfsS4LoRkjItsm4kinqBTNTkVP2VixdWPGFPEWDdGY2YLsjrw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=NfTUBiT/; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="NfTUBiT/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1732345294; x=1763881294; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sUaKs4IKHRtAS2VJ+T+gUebh7+S3mchKFlm9dP1TtUQ=; b=NfTUBiT/Raa4VwYnW4PaeZlBjO6ZbQig6kKLtlg+DIey+0OQpmtHcqe8 hw9PHQTY2L91h7pLCRk0/q2H+tbrwdNq0dHaUAqnOJRj4vVs7d8McNfKw QW7w5FPoBho6CfX/VHKKO/JpSlSRETJj7RiHiwZx7s2kLuxqXYR5+qCI2 p+AUEuNgv5X4lDcwrCJn1P6HyG92Kx1T3nGQNYN/kMkzOAtBg8VRkWPfm o+N7t57Vw1Wo0XQuBWFLEk8Jbg4EIAw0zkCYwkhXcsv2Rjqe851God76r 9/sGiso+C9CivZkX7Grx5EsALDsxKr+OUkWrJUxBos4/8eTIUd43W47fl g==; X-CSE-ConnectionGUID: /KJu0QlcTy+m/zm/0XfbRw== X-CSE-MsgGUID: osC9gKo7TIa8WDui7bZebQ== X-IronPort-AV: E=McAfee;i="6700,10204,11264"; a="32435508" X-IronPort-AV: E=Sophos;i="6.12,178,1728975600"; d="scan'208";a="32435508" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Nov 2024 23:01:29 -0800 X-CSE-ConnectionGUID: X3bP/RyIT4erTLLHM7SmIw== X-CSE-MsgGUID: JCLeK2TqTU2sZVaYYC8rcQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,178,1728975600"; d="scan'208";a="91573559" Received: from unknown (HELO JF5300-B11A338T.jf.intel.com) ([10.242.51.115]) by orviesa008.jf.intel.com with ESMTP; 22 Nov 2024 23:01:28 -0800 From: Kanchana P Sridhar To: linux-kernel@vger.kernel.org, linux-mm@kvack.org, hannes@cmpxchg.org, yosryahmed@google.com, nphamcs@gmail.com, chengming.zhou@linux.dev, usamaarif642@gmail.com, ryan.roberts@arm.com, ying.huang@intel.com, 21cnbao@gmail.com, akpm@linux-foundation.org, linux-crypto@vger.kernel.org, herbert@gondor.apana.org.au, davem@davemloft.net, clabbe@baylibre.com, ardb@kernel.org, ebiggers@google.com, surenb@google.com, kristen.c.accardi@intel.com Cc: wajdi.k.feghali@intel.com, vinodh.gopal@intel.com, kanchana.p.sridhar@intel.com Subject: [PATCH v4 05/10] crypto: iaa - Disable iaa_verify_compress by default. Date: Fri, 22 Nov 2024 23:01:22 -0800 Message-Id: <20241123070127.332773-6-kanchana.p.sridhar@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20241123070127.332773-1-kanchana.p.sridhar@intel.com> References: <20241123070127.332773-1-kanchana.p.sridhar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch makes it easier for IAA hardware acceleration in the iaa_crypto driver to be loaded by default with "iaa_verify_compress" disabled, to facilitate performance comparisons with software compressors (which also do not run compress verification by default). Earlier, iaa_crypto compress verification used to be enabled by default. With this patch, if users want to enable compress verification, they can do so with these steps: 1) disable all the IAA device/wq bindings that happen at boot time 2) rmmod iaa_crypto 3) modprobe iaa_crypto 4) echo 1 > /sys/bus/dsa/drivers/crypto/verify_compress 5) re-run initialization of the IAA devices and wqs Signed-off-by: Kanchana P Sridhar --- drivers/crypto/intel/iaa/iaa_crypto_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/crypto/intel/iaa/iaa_crypto_main.c b/drivers/crypto/in= tel/iaa/iaa_crypto_main.c index bd2db0b6f145..a572803a53d0 100644 --- a/drivers/crypto/intel/iaa/iaa_crypto_main.c +++ b/drivers/crypto/intel/iaa/iaa_crypto_main.c @@ -94,7 +94,7 @@ static bool iaa_crypto_enabled; static bool iaa_crypto_registered; =20 /* Verify results of IAA compress or not */ -static bool iaa_verify_compress =3D true; +static bool iaa_verify_compress =3D false; =20 static ssize_t verify_compress_show(struct device_driver *driver, char *bu= f) { --=20 2.27.0 From nobody Sun Nov 24 06:51:17 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4888217E8E2; Sat, 23 Nov 2024 07:01:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732345295; cv=none; b=pw2IunCYkpzUpJa6pxO8r5yOEWLWOIrTkKWZtOHGWz2IpbLoCQP8gue7EbxCKzw20G9qaTIZ6H3r63OGXXAdexPddaqUPZ77g4djONAMgkPAovRNffN1U7r5aJzM8jPsrvn4aoz0svNvbfSNYoD2AfDJsIDB6b4Tx2BvKII4JDc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732345295; c=relaxed/simple; bh=phDCVCTbOTOUTs6hnR3/+bpctRtdx7MRywI2ALUlrtw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Ik77mPgZrFDekccT51VbiCjuy9/6W82X6mF3RRmvvoutA+FjVhq/7FPmo8DDogtIpk5eNY2ec+kIod7GmWPYnmU++nScfSsnqisoww/sTp8KuCEf7PXZO33tZBytO51B5Acz9+e87eMYjf065iBF09Y/GjBeLmGosCJmW2nEzog= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=M2E5FoG0; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="M2E5FoG0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1732345294; x=1763881294; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=phDCVCTbOTOUTs6hnR3/+bpctRtdx7MRywI2ALUlrtw=; b=M2E5FoG0gNFdvl8l8jqyxy5l8E3qqKHQrMjL3joHY7FmvuiB+iA3L6Q3 pwWkbAhxjo2eOb31LmTDtk+IiJrhCTav743xVCL+wWRj2P8ZSDPBhTxnB JyeXfzM96YNb1VAGJV4VegXP/mWSppbupGQwRn6hx1J7iKkI/ajQbtMrd cPmxAcc5WhFT4U/quUDvkN+xh2IUrddrNa8c9FSfa4Bzwb7WtXDporeer zqh+Ja7d4Duhd0X0dnNTHhf2JoHSXjCdxdBJN1t8aKYj982aIRu22ZZ2m i3pBTM9cp36+gmC5yY2RpvsGA/z5rts4DohwIE4rWKiiMW9hrPSeezYPh A==; X-CSE-ConnectionGUID: PWVk1cCKS+a4qMy5Yg/eMA== X-CSE-MsgGUID: AwM6Y/HFTKyaoFytdGmSXQ== X-IronPort-AV: E=McAfee;i="6700,10204,11264"; a="32435520" X-IronPort-AV: E=Sophos;i="6.12,178,1728975600"; d="scan'208";a="32435520" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Nov 2024 23:01:29 -0800 X-CSE-ConnectionGUID: cj8DpYg8QrSAj4SMeEsQKw== X-CSE-MsgGUID: KPSj7zQzSEyM3bKi0wVjiw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,178,1728975600"; d="scan'208";a="91573562" Received: from unknown (HELO JF5300-B11A338T.jf.intel.com) ([10.242.51.115]) by orviesa008.jf.intel.com with ESMTP; 22 Nov 2024 23:01:28 -0800 From: Kanchana P Sridhar To: linux-kernel@vger.kernel.org, linux-mm@kvack.org, hannes@cmpxchg.org, yosryahmed@google.com, nphamcs@gmail.com, chengming.zhou@linux.dev, usamaarif642@gmail.com, ryan.roberts@arm.com, ying.huang@intel.com, 21cnbao@gmail.com, akpm@linux-foundation.org, linux-crypto@vger.kernel.org, herbert@gondor.apana.org.au, davem@davemloft.net, clabbe@baylibre.com, ardb@kernel.org, ebiggers@google.com, surenb@google.com, kristen.c.accardi@intel.com Cc: wajdi.k.feghali@intel.com, vinodh.gopal@intel.com, kanchana.p.sridhar@intel.com Subject: [PATCH v4 06/10] crypto: iaa - Re-organize the iaa_crypto driver code. Date: Fri, 22 Nov 2024 23:01:23 -0800 Message-Id: <20241123070127.332773-7-kanchana.p.sridhar@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20241123070127.332773-1-kanchana.p.sridhar@intel.com> References: <20241123070127.332773-1-kanchana.p.sridhar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch merely reorganizes the code in iaa_crypto_main.c, so that the functions are consolidated into logically related sub-sections of code. This is expected to make the code more maintainable and for it to be easier to replace functional layers and/or add new features. Signed-off-by: Kanchana P Sridhar --- drivers/crypto/intel/iaa/iaa_crypto_main.c | 540 +++++++++++---------- 1 file changed, 275 insertions(+), 265 deletions(-) diff --git a/drivers/crypto/intel/iaa/iaa_crypto_main.c b/drivers/crypto/in= tel/iaa/iaa_crypto_main.c index a572803a53d0..c2362e4525bd 100644 --- a/drivers/crypto/intel/iaa/iaa_crypto_main.c +++ b/drivers/crypto/intel/iaa/iaa_crypto_main.c @@ -24,6 +24,9 @@ =20 #define IAA_ALG_PRIORITY 300 =20 +/************************************** + * Driver internal global variables. + **************************************/ /* number of iaa instances probed */ static unsigned int nr_iaa; static unsigned int nr_cpus; @@ -36,55 +39,46 @@ static unsigned int cpus_per_iaa; static struct crypto_comp *deflate_generic_tfm; =20 /* Per-cpu lookup table for balanced wqs */ -static struct wq_table_entry __percpu *wq_table; +static struct wq_table_entry __percpu *wq_table =3D NULL; =20 -static struct idxd_wq *wq_table_next_wq(int cpu) -{ - struct wq_table_entry *entry =3D per_cpu_ptr(wq_table, cpu); - - if (++entry->cur_wq >=3D entry->n_wqs) - entry->cur_wq =3D 0; - - if (!entry->wqs[entry->cur_wq]) - return NULL; - - pr_debug("%s: returning wq at idx %d (iaa wq %d.%d) from cpu %d\n", __fun= c__, - entry->cur_wq, entry->wqs[entry->cur_wq]->idxd->id, - entry->wqs[entry->cur_wq]->id, cpu); - - return entry->wqs[entry->cur_wq]; -} - -static void wq_table_add(int cpu, struct idxd_wq *wq) -{ - struct wq_table_entry *entry =3D per_cpu_ptr(wq_table, cpu); - - if (WARN_ON(entry->n_wqs =3D=3D entry->max_wqs)) - return; - - entry->wqs[entry->n_wqs++] =3D wq; - - pr_debug("%s: added iaa wq %d.%d to idx %d of cpu %d\n", __func__, - entry->wqs[entry->n_wqs - 1]->idxd->id, - entry->wqs[entry->n_wqs - 1]->id, entry->n_wqs - 1, cpu); -} - -static void wq_table_free_entry(int cpu) -{ - struct wq_table_entry *entry =3D per_cpu_ptr(wq_table, cpu); +/* Verify results of IAA compress or not */ +static bool iaa_verify_compress =3D false; =20 - kfree(entry->wqs); - memset(entry, 0, sizeof(*entry)); -} +/* + * The iaa crypto driver supports three 'sync' methods determining how + * compressions and decompressions are performed: + * + * - sync: the compression or decompression completes before + * returning. This is the mode used by the async crypto + * interface when the sync mode is set to 'sync' and by + * the sync crypto interface regardless of setting. + * + * - async: the compression or decompression is submitted and returns + * immediately. Completion interrupts are not used so + * the caller is responsible for polling the descriptor + * for completion. This mode is applicable to only the + * async crypto interface and is ignored for anything + * else. + * + * - async_irq: the compression or decompression is submitted and + * returns immediately. Completion interrupts are + * enabled so the caller can wait for the completion and + * yield to other threads. When the compression or + * decompression completes, the completion is signaled + * and the caller awakened. This mode is applicable to + * only the async crypto interface and is ignored for + * anything else. + * + * These modes can be set using the iaa_crypto sync_mode driver + * attribute. + */ =20 -static void wq_table_clear_entry(int cpu) -{ - struct wq_table_entry *entry =3D per_cpu_ptr(wq_table, cpu); +/* Use async mode */ +static bool async_mode =3D true; +/* Use interrupts */ +static bool use_irq; =20 - entry->n_wqs =3D 0; - entry->cur_wq =3D 0; - memset(entry->wqs, 0, entry->max_wqs * sizeof(struct idxd_wq *)); -} +static struct iaa_compression_mode *iaa_compression_modes[IAA_COMP_MODES_M= AX]; =20 LIST_HEAD(iaa_devices); DEFINE_MUTEX(iaa_devices_lock); @@ -93,9 +87,9 @@ DEFINE_MUTEX(iaa_devices_lock); static bool iaa_crypto_enabled; static bool iaa_crypto_registered; =20 -/* Verify results of IAA compress or not */ -static bool iaa_verify_compress =3D false; - +/************************************************** + * Driver attributes along with get/set functions. + **************************************************/ static ssize_t verify_compress_show(struct device_driver *driver, char *bu= f) { return sprintf(buf, "%d\n", iaa_verify_compress); @@ -123,40 +117,6 @@ static ssize_t verify_compress_store(struct device_dri= ver *driver, } static DRIVER_ATTR_RW(verify_compress); =20 -/* - * The iaa crypto driver supports three 'sync' methods determining how - * compressions and decompressions are performed: - * - * - sync: the compression or decompression completes before - * returning. This is the mode used by the async crypto - * interface when the sync mode is set to 'sync' and by - * the sync crypto interface regardless of setting. - * - * - async: the compression or decompression is submitted and returns - * immediately. Completion interrupts are not used so - * the caller is responsible for polling the descriptor - * for completion. This mode is applicable to only the - * async crypto interface and is ignored for anything - * else. - * - * - async_irq: the compression or decompression is submitted and - * returns immediately. Completion interrupts are - * enabled so the caller can wait for the completion and - * yield to other threads. When the compression or - * decompression completes, the completion is signaled - * and the caller awakened. This mode is applicable to - * only the async crypto interface and is ignored for - * anything else. - * - * These modes can be set using the iaa_crypto sync_mode driver - * attribute. - */ - -/* Use async mode */ -static bool async_mode =3D true; -/* Use interrupts */ -static bool use_irq; - /** * set_iaa_sync_mode - Set IAA sync mode * @name: The name of the sync mode @@ -219,8 +179,9 @@ static ssize_t sync_mode_store(struct device_driver *dr= iver, } static DRIVER_ATTR_RW(sync_mode); =20 -static struct iaa_compression_mode *iaa_compression_modes[IAA_COMP_MODES_M= AX]; - +/**************************** + * Driver compression modes. + ****************************/ static int find_empty_iaa_compression_mode(void) { int i =3D -EINVAL; @@ -411,11 +372,6 @@ static void free_device_compression_mode(struct iaa_de= vice *iaa_device, IDXD_OP_FLAG_WR_SRC2_AECS_COMP | \ IDXD_OP_FLAG_AECS_RW_TGLS) =20 -static int check_completion(struct device *dev, - struct iax_completion_record *comp, - bool compress, - bool only_once); - static int init_device_compression_mode(struct iaa_device *iaa_device, struct iaa_compression_mode *mode, int idx, struct idxd_wq *wq) @@ -502,6 +458,10 @@ static void remove_device_compression_modes(struct iaa= _device *iaa_device) } } =20 +/*********************************************************** + * Functions for use in crypto probe and remove interfaces: + * allocate/init/query/deallocate devices/wqs. + ***********************************************************/ static struct iaa_device *iaa_device_alloc(void) { struct iaa_device *iaa_device; @@ -614,16 +574,6 @@ static void del_iaa_wq(struct iaa_device *iaa_device, = struct idxd_wq *wq) } } =20 -static void clear_wq_table(void) -{ - int cpu; - - for (cpu =3D 0; cpu < nr_cpus; cpu++) - wq_table_clear_entry(cpu); - - pr_debug("cleared wq table\n"); -} - static void free_iaa_device(struct iaa_device *iaa_device) { if (!iaa_device) @@ -704,43 +654,6 @@ static int iaa_wq_put(struct idxd_wq *wq) return ret; } =20 -static void free_wq_table(void) -{ - int cpu; - - for (cpu =3D 0; cpu < nr_cpus; cpu++) - wq_table_free_entry(cpu); - - free_percpu(wq_table); - - pr_debug("freed wq table\n"); -} - -static int alloc_wq_table(int max_wqs) -{ - struct wq_table_entry *entry; - int cpu; - - wq_table =3D alloc_percpu(struct wq_table_entry); - if (!wq_table) - return -ENOMEM; - - for (cpu =3D 0; cpu < nr_cpus; cpu++) { - entry =3D per_cpu_ptr(wq_table, cpu); - entry->wqs =3D kcalloc(max_wqs, sizeof(struct wq *), GFP_KERNEL); - if (!entry->wqs) { - free_wq_table(); - return -ENOMEM; - } - - entry->max_wqs =3D max_wqs; - } - - pr_debug("initialized wq table\n"); - - return 0; -} - static int save_iaa_wq(struct idxd_wq *wq) { struct iaa_device *iaa_device, *found =3D NULL; @@ -829,6 +742,87 @@ static void remove_iaa_wq(struct idxd_wq *wq) cpus_per_iaa =3D 1; } =20 +/*************************************************************** + * Mapping IAA devices and wqs to cores with per-cpu wq_tables. + ***************************************************************/ +static void wq_table_free_entry(int cpu) +{ + struct wq_table_entry *entry =3D per_cpu_ptr(wq_table, cpu); + + kfree(entry->wqs); + memset(entry, 0, sizeof(*entry)); +} + +static void wq_table_clear_entry(int cpu) +{ + struct wq_table_entry *entry =3D per_cpu_ptr(wq_table, cpu); + + entry->n_wqs =3D 0; + entry->cur_wq =3D 0; + memset(entry->wqs, 0, entry->max_wqs * sizeof(struct idxd_wq *)); +} + +static void clear_wq_table(void) +{ + int cpu; + + for (cpu =3D 0; cpu < nr_cpus; cpu++) + wq_table_clear_entry(cpu); + + pr_debug("cleared wq table\n"); +} + +static void free_wq_table(void) +{ + int cpu; + + for (cpu =3D 0; cpu < nr_cpus; cpu++) + wq_table_free_entry(cpu); + + free_percpu(wq_table); + + pr_debug("freed wq table\n"); +} + +static int alloc_wq_table(int max_wqs) +{ + struct wq_table_entry *entry; + int cpu; + + wq_table =3D alloc_percpu(struct wq_table_entry); + if (!wq_table) + return -ENOMEM; + + for (cpu =3D 0; cpu < nr_cpus; cpu++) { + entry =3D per_cpu_ptr(wq_table, cpu); + entry->wqs =3D kcalloc(max_wqs, sizeof(struct wq *), GFP_KERNEL); + if (!entry->wqs) { + free_wq_table(); + return -ENOMEM; + } + + entry->max_wqs =3D max_wqs; + } + + pr_debug("initialized wq table\n"); + + return 0; +} + +static void wq_table_add(int cpu, struct idxd_wq *wq) +{ + struct wq_table_entry *entry =3D per_cpu_ptr(wq_table, cpu); + + if (WARN_ON(entry->n_wqs =3D=3D entry->max_wqs)) + return; + + entry->wqs[entry->n_wqs++] =3D wq; + + pr_debug("%s: added iaa wq %d.%d to idx %d of cpu %d\n", __func__, + entry->wqs[entry->n_wqs - 1]->idxd->id, + entry->wqs[entry->n_wqs - 1]->id, entry->n_wqs - 1, cpu); +} + static int wq_table_add_wqs(int iaa, int cpu) { struct iaa_device *iaa_device, *found_device =3D NULL; @@ -939,6 +933,29 @@ static void rebalance_wq_table(void) } } =20 +/*************************************************************** + * Assign work-queues for driver ops using per-cpu wq_tables. + ***************************************************************/ +static struct idxd_wq *wq_table_next_wq(int cpu) +{ + struct wq_table_entry *entry =3D per_cpu_ptr(wq_table, cpu); + + if (++entry->cur_wq >=3D entry->n_wqs) + entry->cur_wq =3D 0; + + if (!entry->wqs[entry->cur_wq]) + return NULL; + + pr_debug("%s: returning wq at idx %d (iaa wq %d.%d) from cpu %d\n", __fun= c__, + entry->cur_wq, entry->wqs[entry->cur_wq]->idxd->id, + entry->wqs[entry->cur_wq]->id, cpu); + + return entry->wqs[entry->cur_wq]; +} + +/************************************************* + * Core iaa_crypto compress/decompress functions. + *************************************************/ static inline int check_completion(struct device *dev, struct iax_completion_record *comp, bool compress, @@ -1010,13 +1027,130 @@ static int deflate_generic_decompress(struct acomp= _req *req) =20 static int iaa_remap_for_verify(struct device *dev, struct iaa_wq *iaa_wq, struct acomp_req *req, - dma_addr_t *src_addr, dma_addr_t *dst_addr); + dma_addr_t *src_addr, dma_addr_t *dst_addr) +{ + int ret =3D 0; + int nr_sgs; + + dma_unmap_sg(dev, req->dst, sg_nents(req->dst), DMA_FROM_DEVICE); + dma_unmap_sg(dev, req->src, sg_nents(req->src), DMA_TO_DEVICE); + + nr_sgs =3D dma_map_sg(dev, req->src, sg_nents(req->src), DMA_FROM_DEVICE); + if (nr_sgs <=3D 0 || nr_sgs > 1) { + dev_dbg(dev, "verify: couldn't map src sg for iaa device %d," + " wq %d: ret=3D%d\n", iaa_wq->iaa_device->idxd->id, + iaa_wq->wq->id, ret); + ret =3D -EIO; + goto out; + } + *src_addr =3D sg_dma_address(req->src); + dev_dbg(dev, "verify: dma_map_sg, src_addr %llx, nr_sgs %d, req->src %p," + " req->slen %d, sg_dma_len(sg) %d\n", *src_addr, nr_sgs, + req->src, req->slen, sg_dma_len(req->src)); + + nr_sgs =3D dma_map_sg(dev, req->dst, sg_nents(req->dst), DMA_TO_DEVICE); + if (nr_sgs <=3D 0 || nr_sgs > 1) { + dev_dbg(dev, "verify: couldn't map dst sg for iaa device %d," + " wq %d: ret=3D%d\n", iaa_wq->iaa_device->idxd->id, + iaa_wq->wq->id, ret); + ret =3D -EIO; + dma_unmap_sg(dev, req->src, sg_nents(req->src), DMA_FROM_DEVICE); + goto out; + } + *dst_addr =3D sg_dma_address(req->dst); + dev_dbg(dev, "verify: dma_map_sg, dst_addr %llx, nr_sgs %d, req->dst %p," + " req->dlen %d, sg_dma_len(sg) %d\n", *dst_addr, nr_sgs, + req->dst, req->dlen, sg_dma_len(req->dst)); +out: + return ret; +} =20 static int iaa_compress_verify(struct crypto_tfm *tfm, struct acomp_req *r= eq, struct idxd_wq *wq, dma_addr_t src_addr, unsigned int slen, dma_addr_t dst_addr, unsigned int *dlen, - u32 compression_crc); + u32 compression_crc) +{ + struct iaa_device_compression_mode *active_compression_mode; + struct iaa_compression_ctx *ctx =3D crypto_tfm_ctx(tfm); + struct iaa_device *iaa_device; + struct idxd_desc *idxd_desc; + struct iax_hw_desc *desc; + struct idxd_device *idxd; + struct iaa_wq *iaa_wq; + struct pci_dev *pdev; + struct device *dev; + int ret =3D 0; + + iaa_wq =3D idxd_wq_get_private(wq); + iaa_device =3D iaa_wq->iaa_device; + idxd =3D iaa_device->idxd; + pdev =3D idxd->pdev; + dev =3D &pdev->dev; + + active_compression_mode =3D get_iaa_device_compression_mode(iaa_device, c= tx->mode); + + idxd_desc =3D idxd_alloc_desc(wq, IDXD_OP_BLOCK); + if (IS_ERR(idxd_desc)) { + dev_dbg(dev, "idxd descriptor allocation failed\n"); + dev_dbg(dev, "iaa compress failed: ret=3D%ld\n", + PTR_ERR(idxd_desc)); + return PTR_ERR(idxd_desc); + } + desc =3D idxd_desc->iax_hw; + + /* Verify (optional) - decompress and check crc, suppress dest write */ + + desc->flags =3D IDXD_OP_FLAG_CRAV | IDXD_OP_FLAG_RCR | IDXD_OP_FLAG_CC; + desc->opcode =3D IAX_OPCODE_DECOMPRESS; + desc->decompr_flags =3D IAA_DECOMP_FLAGS | IAA_DECOMP_SUPPRESS_OUTPUT; + desc->priv =3D 0; + + desc->src1_addr =3D (u64)dst_addr; + desc->src1_size =3D *dlen; + desc->dst_addr =3D (u64)src_addr; + desc->max_dst_size =3D slen; + desc->completion_addr =3D idxd_desc->compl_dma; + + dev_dbg(dev, "(verify) compression mode %s," + " desc->src1_addr %llx, desc->src1_size %d," + " desc->dst_addr %llx, desc->max_dst_size %d," + " desc->src2_addr %llx, desc->src2_size %d\n", + active_compression_mode->name, + desc->src1_addr, desc->src1_size, desc->dst_addr, + desc->max_dst_size, desc->src2_addr, desc->src2_size); + + ret =3D idxd_submit_desc(wq, idxd_desc); + if (ret) { + dev_dbg(dev, "submit_desc (verify) failed ret=3D%d\n", ret); + goto err; + } + + ret =3D check_completion(dev, idxd_desc->iax_completion, false, false); + if (ret) { + dev_dbg(dev, "(verify) check_completion failed ret=3D%d\n", ret); + goto err; + } + + if (compression_crc !=3D idxd_desc->iax_completion->crc) { + ret =3D -EINVAL; + dev_dbg(dev, "(verify) iaa comp/decomp crc mismatch:" + " comp=3D0x%x, decomp=3D0x%x\n", compression_crc, + idxd_desc->iax_completion->crc); + print_hex_dump(KERN_INFO, "cmp-rec: ", DUMP_PREFIX_OFFSET, + 8, 1, idxd_desc->iax_completion, 64, 0); + goto err; + } + + idxd_free_desc(wq, idxd_desc); +out: + return ret; +err: + idxd_free_desc(wq, idxd_desc); + dev_dbg(dev, "iaa compress failed: ret=3D%d\n", ret); + + goto out; +} =20 static void iaa_desc_complete(struct idxd_desc *idxd_desc, enum idxd_complete_type comp_type, @@ -1235,133 +1369,6 @@ static int iaa_compress(struct crypto_tfm *tfm, str= uct acomp_req *req, goto out; } =20 -static int iaa_remap_for_verify(struct device *dev, struct iaa_wq *iaa_wq, - struct acomp_req *req, - dma_addr_t *src_addr, dma_addr_t *dst_addr) -{ - int ret =3D 0; - int nr_sgs; - - dma_unmap_sg(dev, req->dst, sg_nents(req->dst), DMA_FROM_DEVICE); - dma_unmap_sg(dev, req->src, sg_nents(req->src), DMA_TO_DEVICE); - - nr_sgs =3D dma_map_sg(dev, req->src, sg_nents(req->src), DMA_FROM_DEVICE); - if (nr_sgs <=3D 0 || nr_sgs > 1) { - dev_dbg(dev, "verify: couldn't map src sg for iaa device %d," - " wq %d: ret=3D%d\n", iaa_wq->iaa_device->idxd->id, - iaa_wq->wq->id, ret); - ret =3D -EIO; - goto out; - } - *src_addr =3D sg_dma_address(req->src); - dev_dbg(dev, "verify: dma_map_sg, src_addr %llx, nr_sgs %d, req->src %p," - " req->slen %d, sg_dma_len(sg) %d\n", *src_addr, nr_sgs, - req->src, req->slen, sg_dma_len(req->src)); - - nr_sgs =3D dma_map_sg(dev, req->dst, sg_nents(req->dst), DMA_TO_DEVICE); - if (nr_sgs <=3D 0 || nr_sgs > 1) { - dev_dbg(dev, "verify: couldn't map dst sg for iaa device %d," - " wq %d: ret=3D%d\n", iaa_wq->iaa_device->idxd->id, - iaa_wq->wq->id, ret); - ret =3D -EIO; - dma_unmap_sg(dev, req->src, sg_nents(req->src), DMA_FROM_DEVICE); - goto out; - } - *dst_addr =3D sg_dma_address(req->dst); - dev_dbg(dev, "verify: dma_map_sg, dst_addr %llx, nr_sgs %d, req->dst %p," - " req->dlen %d, sg_dma_len(sg) %d\n", *dst_addr, nr_sgs, - req->dst, req->dlen, sg_dma_len(req->dst)); -out: - return ret; -} - -static int iaa_compress_verify(struct crypto_tfm *tfm, struct acomp_req *r= eq, - struct idxd_wq *wq, - dma_addr_t src_addr, unsigned int slen, - dma_addr_t dst_addr, unsigned int *dlen, - u32 compression_crc) -{ - struct iaa_device_compression_mode *active_compression_mode; - struct iaa_compression_ctx *ctx =3D crypto_tfm_ctx(tfm); - struct iaa_device *iaa_device; - struct idxd_desc *idxd_desc; - struct iax_hw_desc *desc; - struct idxd_device *idxd; - struct iaa_wq *iaa_wq; - struct pci_dev *pdev; - struct device *dev; - int ret =3D 0; - - iaa_wq =3D idxd_wq_get_private(wq); - iaa_device =3D iaa_wq->iaa_device; - idxd =3D iaa_device->idxd; - pdev =3D idxd->pdev; - dev =3D &pdev->dev; - - active_compression_mode =3D get_iaa_device_compression_mode(iaa_device, c= tx->mode); - - idxd_desc =3D idxd_alloc_desc(wq, IDXD_OP_BLOCK); - if (IS_ERR(idxd_desc)) { - dev_dbg(dev, "idxd descriptor allocation failed\n"); - dev_dbg(dev, "iaa compress failed: ret=3D%ld\n", - PTR_ERR(idxd_desc)); - return PTR_ERR(idxd_desc); - } - desc =3D idxd_desc->iax_hw; - - /* Verify (optional) - decompress and check crc, suppress dest write */ - - desc->flags =3D IDXD_OP_FLAG_CRAV | IDXD_OP_FLAG_RCR | IDXD_OP_FLAG_CC; - desc->opcode =3D IAX_OPCODE_DECOMPRESS; - desc->decompr_flags =3D IAA_DECOMP_FLAGS | IAA_DECOMP_SUPPRESS_OUTPUT; - desc->priv =3D 0; - - desc->src1_addr =3D (u64)dst_addr; - desc->src1_size =3D *dlen; - desc->dst_addr =3D (u64)src_addr; - desc->max_dst_size =3D slen; - desc->completion_addr =3D idxd_desc->compl_dma; - - dev_dbg(dev, "(verify) compression mode %s," - " desc->src1_addr %llx, desc->src1_size %d," - " desc->dst_addr %llx, desc->max_dst_size %d," - " desc->src2_addr %llx, desc->src2_size %d\n", - active_compression_mode->name, - desc->src1_addr, desc->src1_size, desc->dst_addr, - desc->max_dst_size, desc->src2_addr, desc->src2_size); - - ret =3D idxd_submit_desc(wq, idxd_desc); - if (ret) { - dev_dbg(dev, "submit_desc (verify) failed ret=3D%d\n", ret); - goto err; - } - - ret =3D check_completion(dev, idxd_desc->iax_completion, false, false); - if (ret) { - dev_dbg(dev, "(verify) check_completion failed ret=3D%d\n", ret); - goto err; - } - - if (compression_crc !=3D idxd_desc->iax_completion->crc) { - ret =3D -EINVAL; - dev_dbg(dev, "(verify) iaa comp/decomp crc mismatch:" - " comp=3D0x%x, decomp=3D0x%x\n", compression_crc, - idxd_desc->iax_completion->crc); - print_hex_dump(KERN_INFO, "cmp-rec: ", DUMP_PREFIX_OFFSET, - 8, 1, idxd_desc->iax_completion, 64, 0); - goto err; - } - - idxd_free_desc(wq, idxd_desc); -out: - return ret; -err: - idxd_free_desc(wq, idxd_desc); - dev_dbg(dev, "iaa compress failed: ret=3D%d\n", ret); - - goto out; -} - static int iaa_decompress(struct crypto_tfm *tfm, struct acomp_req *req, struct idxd_wq *wq, dma_addr_t src_addr, unsigned int slen, @@ -2132,6 +2139,9 @@ static void iaa_comp_adecompress_batch( crypto_req_done, wait); } =20 +/********************************************* + * Interfaces to crypto_alg and crypto_acomp. + *********************************************/ static int iaa_comp_init_fixed(struct crypto_acomp *acomp_tfm) { struct crypto_tfm *tfm =3D crypto_acomp_tfm(acomp_tfm); --=20 2.27.0 From nobody Sun Nov 24 06:51:17 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C59EA185935; Sat, 23 Nov 2024 07:01:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732345296; cv=none; b=NBps32aFUfLDOKpipu7uOI+KA2m+q5t4C3BXj3EOnoBTxZezR/CM0HLeMR/myj7WQ3hghgJ+FjSbjsCq6cK/Z2T2FPtR93Scu+5bFWqCLJcnf8ztBMSyDLZh5p6B4538YmKO5tb6qR9LHtkbQRTc98etfEHoU2QUY5879Zrr1rE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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d="scan'208";a="91573565" Received: from unknown (HELO JF5300-B11A338T.jf.intel.com) ([10.242.51.115]) by orviesa008.jf.intel.com with ESMTP; 22 Nov 2024 23:01:29 -0800 From: Kanchana P Sridhar To: linux-kernel@vger.kernel.org, linux-mm@kvack.org, hannes@cmpxchg.org, yosryahmed@google.com, nphamcs@gmail.com, chengming.zhou@linux.dev, usamaarif642@gmail.com, ryan.roberts@arm.com, ying.huang@intel.com, 21cnbao@gmail.com, akpm@linux-foundation.org, linux-crypto@vger.kernel.org, herbert@gondor.apana.org.au, davem@davemloft.net, clabbe@baylibre.com, ardb@kernel.org, ebiggers@google.com, surenb@google.com, kristen.c.accardi@intel.com Cc: wajdi.k.feghali@intel.com, vinodh.gopal@intel.com, kanchana.p.sridhar@intel.com Subject: [PATCH v4 07/10] crypto: iaa - Map IAA devices/wqs to cores based on packages instead of NUMA. Date: Fri, 22 Nov 2024 23:01:24 -0800 Message-Id: <20241123070127.332773-8-kanchana.p.sridhar@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20241123070127.332773-1-kanchana.p.sridhar@intel.com> References: <20241123070127.332773-1-kanchana.p.sridhar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch modifies the algorithm for mapping available IAA devices and wqs to cores, as they are being discovered, based on packages instead of NUMA nodes. This leads to a more realistic mapping of IAA devices as compression/decompression resources for a package, rather than for a NUMA node. This also resolves problems that were observed during internal validation on Intel platforms with many more NUMA nodes than packages: for such cases, the earlier NUMA based allocation caused some IAAs to be over-subscribed and some to not be utilized at all. As a result of this change from NUMA to packages, some of the core functions used by the iaa_crypto driver's "probe" and "remove" API have been re-written. The new infrastructure maintains a static/global mapping of "local wqs" per IAA device, in the "struct iaa_device" itself. The earlier implementation would allocate memory per-cpu for this data, which never changes once the IAA devices/wqs have been initialized. Two main outcomes from this new iaa_crypto driver infrastructure are: 1) Resolves "task blocked for more than x seconds" errors observed during internal validation on Intel systems with the earlier NUMA node based mappings, which was root-caused to the non-optimal IAA-to-core mappings described earlier. 2) Results in a NUM_THREADS factor reduction in memory footprint cost of initializing IAA devices/wqs, due to eliminating the per-cpu copies of each IAA device's wqs. On a 384 cores Intel Granite Rapids server with 8 IAA devices, this saves 140MiB. Signed-off-by: Kanchana P Sridhar --- drivers/crypto/intel/iaa/iaa_crypto.h | 17 +- drivers/crypto/intel/iaa/iaa_crypto_main.c | 276 ++++++++++++--------- 2 files changed, 171 insertions(+), 122 deletions(-) diff --git a/drivers/crypto/intel/iaa/iaa_crypto.h b/drivers/crypto/intel/i= aa/iaa_crypto.h index 56985e395263..ca317c5aaf27 100644 --- a/drivers/crypto/intel/iaa/iaa_crypto.h +++ b/drivers/crypto/intel/iaa/iaa_crypto.h @@ -46,6 +46,7 @@ struct iaa_wq { struct idxd_wq *wq; int ref; bool remove; + bool mapped; =20 struct iaa_device *iaa_device; =20 @@ -63,6 +64,13 @@ struct iaa_device_compression_mode { dma_addr_t aecs_comp_table_dma_addr; }; =20 +struct wq_table_entry { + struct idxd_wq **wqs; + int max_wqs; + int n_wqs; + int cur_wq; +}; + /* Representation of IAA device with wqs, populated by probe */ struct iaa_device { struct list_head list; @@ -73,19 +81,14 @@ struct iaa_device { int n_wq; struct list_head wqs; =20 + struct wq_table_entry *iaa_local_wqs; + atomic64_t comp_calls; atomic64_t comp_bytes; atomic64_t decomp_calls; atomic64_t decomp_bytes; }; =20 -struct wq_table_entry { - struct idxd_wq **wqs; - int max_wqs; - int n_wqs; - int cur_wq; -}; - #define IAA_AECS_ALIGN 32 =20 /* diff --git a/drivers/crypto/intel/iaa/iaa_crypto_main.c b/drivers/crypto/in= tel/iaa/iaa_crypto_main.c index c2362e4525bd..28f2f5617bf0 100644 --- a/drivers/crypto/intel/iaa/iaa_crypto_main.c +++ b/drivers/crypto/intel/iaa/iaa_crypto_main.c @@ -30,8 +30,9 @@ /* number of iaa instances probed */ static unsigned int nr_iaa; static unsigned int nr_cpus; -static unsigned int nr_nodes; -static unsigned int nr_cpus_per_node; +static unsigned int nr_packages; +static unsigned int nr_cpus_per_package; +static unsigned int nr_iaa_per_package; =20 /* Number of physical cpus sharing each iaa instance */ static unsigned int cpus_per_iaa; @@ -462,17 +463,46 @@ static void remove_device_compression_modes(struct ia= a_device *iaa_device) * Functions for use in crypto probe and remove interfaces: * allocate/init/query/deallocate devices/wqs. ***********************************************************/ -static struct iaa_device *iaa_device_alloc(void) +static struct iaa_device *iaa_device_alloc(struct idxd_device *idxd) { + struct wq_table_entry *local; struct iaa_device *iaa_device; =20 iaa_device =3D kzalloc(sizeof(*iaa_device), GFP_KERNEL); if (!iaa_device) - return NULL; + goto err; + + iaa_device->idxd =3D idxd; + + /* IAA device's local wqs. */ + iaa_device->iaa_local_wqs =3D kzalloc(sizeof(struct wq_table_entry), GFP_= KERNEL); + if (!iaa_device->iaa_local_wqs) + goto err; + + local =3D iaa_device->iaa_local_wqs; + + local->wqs =3D kzalloc(iaa_device->idxd->max_wqs * sizeof(struct wq *), G= FP_KERNEL); + if (!local->wqs) + goto err; + + local->max_wqs =3D iaa_device->idxd->max_wqs; + local->n_wqs =3D 0; =20 INIT_LIST_HEAD(&iaa_device->wqs); =20 return iaa_device; + +err: + if (iaa_device) { + if (iaa_device->iaa_local_wqs) { + if (iaa_device->iaa_local_wqs->wqs) + kfree(iaa_device->iaa_local_wqs->wqs); + kfree(iaa_device->iaa_local_wqs); + } + kfree(iaa_device); + } + + return NULL; } =20 static bool iaa_has_wq(struct iaa_device *iaa_device, struct idxd_wq *wq) @@ -491,12 +521,10 @@ static struct iaa_device *add_iaa_device(struct idxd_= device *idxd) { struct iaa_device *iaa_device; =20 - iaa_device =3D iaa_device_alloc(); + iaa_device =3D iaa_device_alloc(idxd); if (!iaa_device) return NULL; =20 - iaa_device->idxd =3D idxd; - list_add_tail(&iaa_device->list, &iaa_devices); =20 nr_iaa++; @@ -537,6 +565,7 @@ static int add_iaa_wq(struct iaa_device *iaa_device, st= ruct idxd_wq *wq, iaa_wq->wq =3D wq; iaa_wq->iaa_device =3D iaa_device; idxd_wq_set_private(wq, iaa_wq); + iaa_wq->mapped =3D false; =20 list_add_tail(&iaa_wq->list, &iaa_device->wqs); =20 @@ -580,6 +609,13 @@ static void free_iaa_device(struct iaa_device *iaa_dev= ice) return; =20 remove_device_compression_modes(iaa_device); + + if (iaa_device->iaa_local_wqs) { + if (iaa_device->iaa_local_wqs->wqs) + kfree(iaa_device->iaa_local_wqs->wqs); + kfree(iaa_device->iaa_local_wqs); + } + kfree(iaa_device); } =20 @@ -716,9 +752,14 @@ static int save_iaa_wq(struct idxd_wq *wq) if (WARN_ON(nr_iaa =3D=3D 0)) return -EINVAL; =20 - cpus_per_iaa =3D (nr_nodes * nr_cpus_per_node) / nr_iaa; + cpus_per_iaa =3D (nr_packages * nr_cpus_per_package) / nr_iaa; if (!cpus_per_iaa) cpus_per_iaa =3D 1; + + nr_iaa_per_package =3D nr_iaa / nr_packages; + if (!nr_iaa_per_package) + nr_iaa_per_package =3D 1; + out: return 0; } @@ -735,53 +776,45 @@ static void remove_iaa_wq(struct idxd_wq *wq) } =20 if (nr_iaa) { - cpus_per_iaa =3D (nr_nodes * nr_cpus_per_node) / nr_iaa; + cpus_per_iaa =3D (nr_packages * nr_cpus_per_package) / nr_iaa; if (!cpus_per_iaa) cpus_per_iaa =3D 1; - } else + + nr_iaa_per_package =3D nr_iaa / nr_packages; + if (!nr_iaa_per_package) + nr_iaa_per_package =3D 1; + } else { cpus_per_iaa =3D 1; + nr_iaa_per_package =3D 1; + } } =20 /*************************************************************** * Mapping IAA devices and wqs to cores with per-cpu wq_tables. ***************************************************************/ -static void wq_table_free_entry(int cpu) -{ - struct wq_table_entry *entry =3D per_cpu_ptr(wq_table, cpu); - - kfree(entry->wqs); - memset(entry, 0, sizeof(*entry)); -} - -static void wq_table_clear_entry(int cpu) -{ - struct wq_table_entry *entry =3D per_cpu_ptr(wq_table, cpu); - - entry->n_wqs =3D 0; - entry->cur_wq =3D 0; - memset(entry->wqs, 0, entry->max_wqs * sizeof(struct idxd_wq *)); -} - -static void clear_wq_table(void) +/* + * Given a cpu, find the closest IAA instance. The idea is to try to + * choose the most appropriate IAA instance for a caller and spread + * available workqueues around to clients. + */ +static inline int cpu_to_iaa(int cpu) { - int cpu; - - for (cpu =3D 0; cpu < nr_cpus; cpu++) - wq_table_clear_entry(cpu); + int package_id, base_iaa, iaa =3D 0; =20 - pr_debug("cleared wq table\n"); -} + if (!nr_packages || !nr_iaa_per_package) + return 0; =20 -static void free_wq_table(void) -{ - int cpu; + package_id =3D topology_logical_package_id(cpu); + base_iaa =3D package_id * nr_iaa_per_package; + iaa =3D base_iaa + ((cpu % nr_cpus_per_package) / cpus_per_iaa); =20 - for (cpu =3D 0; cpu < nr_cpus; cpu++) - wq_table_free_entry(cpu); + pr_debug("cpu =3D %d, package_id =3D %d, base_iaa =3D %d, iaa =3D %d", + cpu, package_id, base_iaa, iaa); =20 - free_percpu(wq_table); + if (iaa >=3D 0 && iaa < nr_iaa) + return iaa; =20 - pr_debug("freed wq table\n"); + return (nr_iaa - 1); } =20 static int alloc_wq_table(int max_wqs) @@ -795,13 +828,11 @@ static int alloc_wq_table(int max_wqs) =20 for (cpu =3D 0; cpu < nr_cpus; cpu++) { entry =3D per_cpu_ptr(wq_table, cpu); - entry->wqs =3D kcalloc(max_wqs, sizeof(struct wq *), GFP_KERNEL); - if (!entry->wqs) { - free_wq_table(); - return -ENOMEM; - } =20 + entry->wqs =3D NULL; entry->max_wqs =3D max_wqs; + entry->n_wqs =3D 0; + entry->cur_wq =3D 0; } =20 pr_debug("initialized wq table\n"); @@ -809,33 +840,27 @@ static int alloc_wq_table(int max_wqs) return 0; } =20 -static void wq_table_add(int cpu, struct idxd_wq *wq) +static void wq_table_add(int cpu, struct wq_table_entry *iaa_local_wqs) { struct wq_table_entry *entry =3D per_cpu_ptr(wq_table, cpu); =20 - if (WARN_ON(entry->n_wqs =3D=3D entry->max_wqs)) - return; - - entry->wqs[entry->n_wqs++] =3D wq; + entry->wqs =3D iaa_local_wqs->wqs; + entry->max_wqs =3D iaa_local_wqs->max_wqs; + entry->n_wqs =3D iaa_local_wqs->n_wqs; + entry->cur_wq =3D 0; =20 - pr_debug("%s: added iaa wq %d.%d to idx %d of cpu %d\n", __func__, + pr_debug("%s: cpu %d: added %d iaa local wqs up to wq %d.%d\n", __func__, + cpu, entry->n_wqs, entry->wqs[entry->n_wqs - 1]->idxd->id, - entry->wqs[entry->n_wqs - 1]->id, entry->n_wqs - 1, cpu); + entry->wqs[entry->n_wqs - 1]->id); } =20 static int wq_table_add_wqs(int iaa, int cpu) { struct iaa_device *iaa_device, *found_device =3D NULL; - int ret =3D 0, cur_iaa =3D 0, n_wqs_added =3D 0; - struct idxd_device *idxd; - struct iaa_wq *iaa_wq; - struct pci_dev *pdev; - struct device *dev; + int ret =3D 0, cur_iaa =3D 0; =20 list_for_each_entry(iaa_device, &iaa_devices, list) { - idxd =3D iaa_device->idxd; - pdev =3D idxd->pdev; - dev =3D &pdev->dev; =20 if (cur_iaa !=3D iaa) { cur_iaa++; @@ -843,7 +868,8 @@ static int wq_table_add_wqs(int iaa, int cpu) } =20 found_device =3D iaa_device; - dev_dbg(dev, "getting wq from iaa_device %d, cur_iaa %d\n", + dev_dbg(&found_device->idxd->pdev->dev, + "getting wq from iaa_device %d, cur_iaa %d\n", found_device->idxd->id, cur_iaa); break; } @@ -858,29 +884,58 @@ static int wq_table_add_wqs(int iaa, int cpu) } cur_iaa =3D 0; =20 - idxd =3D found_device->idxd; - pdev =3D idxd->pdev; - dev =3D &pdev->dev; - dev_dbg(dev, "getting wq from only iaa_device %d, cur_iaa %d\n", + dev_dbg(&found_device->idxd->pdev->dev, + "getting wq from only iaa_device %d, cur_iaa %d\n", found_device->idxd->id, cur_iaa); } =20 - list_for_each_entry(iaa_wq, &found_device->wqs, list) { - wq_table_add(cpu, iaa_wq->wq); - pr_debug("rebalance: added wq for cpu=3D%d: iaa wq %d.%d\n", - cpu, iaa_wq->wq->idxd->id, iaa_wq->wq->id); - n_wqs_added++; + wq_table_add(cpu, found_device->iaa_local_wqs); + +out: + return ret; +} + +static int map_iaa_device_wqs(struct iaa_device *iaa_device) +{ + struct wq_table_entry *local; + int ret =3D 0, n_wqs_added =3D 0; + struct iaa_wq *iaa_wq; + + local =3D iaa_device->iaa_local_wqs; + + list_for_each_entry(iaa_wq, &iaa_device->wqs, list) { + if (iaa_wq->mapped && ++n_wqs_added) + continue; + + pr_debug("iaa_device %px: processing wq %d.%d\n", iaa_device, iaa_device= ->idxd->id, iaa_wq->wq->id); + + if (WARN_ON(local->n_wqs =3D=3D local->max_wqs)) + break; + + local->wqs[local->n_wqs++] =3D iaa_wq->wq; + pr_debug("iaa_device %px: added local wq %d.%d\n", iaa_device, iaa_devic= e->idxd->id, iaa_wq->wq->id); + + iaa_wq->mapped =3D true; + ++n_wqs_added; } =20 - if (!n_wqs_added) { - pr_debug("couldn't find any iaa wqs!\n"); + if (!n_wqs_added && !iaa_device->n_wq) { + pr_debug("iaa_device %d: couldn't find any iaa wqs!\n", iaa_device->idxd= ->id); ret =3D -EINVAL; - goto out; } -out: + return ret; } =20 +static void map_iaa_devices(void) +{ + struct iaa_device *iaa_device; + + list_for_each_entry(iaa_device, &iaa_devices, list) { + BUG_ON(map_iaa_device_wqs(iaa_device)); + } +} + /* * Rebalance the wq table so that given a cpu, it's easy to find the * closest IAA instance. The idea is to try to choose the most @@ -889,48 +944,42 @@ static int wq_table_add_wqs(int iaa, int cpu) */ static void rebalance_wq_table(void) { - const struct cpumask *node_cpus; - int node, cpu, iaa =3D -1; + int cpu, iaa; =20 if (nr_iaa =3D=3D 0) return; =20 - pr_debug("rebalance: nr_nodes=3D%d, nr_cpus %d, nr_iaa %d, cpus_per_iaa %= d\n", - nr_nodes, nr_cpus, nr_iaa, cpus_per_iaa); + map_iaa_devices(); =20 - clear_wq_table(); + pr_debug("rebalance: nr_packages=3D%d, nr_cpus %d, nr_iaa %d, cpus_per_ia= a %d\n", + nr_packages, nr_cpus, nr_iaa, cpus_per_iaa); =20 - if (nr_iaa =3D=3D 1) { - for (cpu =3D 0; cpu < nr_cpus; cpu++) { - if (WARN_ON(wq_table_add_wqs(0, cpu))) { - pr_debug("could not add any wqs for iaa 0 to cpu %d!\n", cpu); - return; - } + for (cpu =3D 0; cpu < nr_cpus; cpu++) { + iaa =3D cpu_to_iaa(cpu); + pr_debug("rebalance: cpu=3D%d iaa=3D%d\n", cpu, iaa); + + if (WARN_ON(iaa =3D=3D -1)) { + pr_debug("rebalance (cpu_to_iaa(%d)) failed!\n", cpu); + return; } =20 - return; + if (WARN_ON(wq_table_add_wqs(iaa, cpu))) { + pr_debug("could not add any wqs for iaa %d to cpu %d!\n", iaa, cpu); + return; + } } =20 - for_each_node_with_cpus(node) { - node_cpus =3D cpumask_of_node(node); - - for (cpu =3D 0; cpu < cpumask_weight(node_cpus); cpu++) { - int node_cpu =3D cpumask_nth(cpu, node_cpus); - - if (WARN_ON(node_cpu >=3D nr_cpu_ids)) { - pr_debug("node_cpu %d doesn't exist!\n", node_cpu); - return; - } - - if ((cpu % cpus_per_iaa) =3D=3D 0) - iaa++; + pr_debug("Finished rebalance local wqs."); +} =20 - if (WARN_ON(wq_table_add_wqs(iaa, node_cpu))) { - pr_debug("could not add any wqs for iaa %d to cpu %d!\n", iaa, cpu); - return; - } - } +static void free_wq_tables(void) +{ + if (wq_table) { + free_percpu(wq_table); + wq_table =3D NULL; } + + pr_debug("freed local wq table\n"); } =20 /*************************************************************** @@ -2281,7 +2330,7 @@ static int iaa_crypto_probe(struct idxd_dev *idxd_dev) free_iaa_wq(idxd_wq_get_private(wq)); err_save: if (first_wq) - free_wq_table(); + free_wq_tables(); err_alloc: mutex_unlock(&iaa_devices_lock); idxd_drv_disable_wq(wq); @@ -2331,7 +2380,9 @@ static void iaa_crypto_remove(struct idxd_dev *idxd_d= ev) =20 if (nr_iaa =3D=3D 0) { iaa_crypto_enabled =3D false; - free_wq_table(); + free_wq_tables(); + BUG_ON(!list_empty(&iaa_devices)); + INIT_LIST_HEAD(&iaa_devices); module_put(THIS_MODULE); =20 pr_info("iaa_crypto now DISABLED\n"); @@ -2357,16 +2408,11 @@ static struct idxd_device_driver iaa_crypto_driver = =3D { static int __init iaa_crypto_init_module(void) { int ret =3D 0; - int node; + INIT_LIST_HEAD(&iaa_devices); =20 nr_cpus =3D num_possible_cpus(); - for_each_node_with_cpus(node) - nr_nodes++; - if (!nr_nodes) { - pr_err("IAA couldn't find any nodes with cpus\n"); - return -ENODEV; - } - nr_cpus_per_node =3D nr_cpus / nr_nodes; + nr_cpus_per_package =3D topology_num_cores_per_package(); + nr_packages =3D topology_max_packages(); =20 if (crypto_has_comp("deflate-generic", 0, 0)) deflate_generic_tfm =3D crypto_alloc_comp("deflate-generic", 0, 0); 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X-CSE-ConnectionGUID: XKS9WAM5RlyC62yx2sWAiA== X-CSE-MsgGUID: ws3yTFySSDS5Lp1IfVc5Hw== X-IronPort-AV: E=McAfee;i="6700,10204,11264"; a="32435544" X-IronPort-AV: E=Sophos;i="6.12,178,1728975600"; d="scan'208";a="32435544" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Nov 2024 23:01:29 -0800 X-CSE-ConnectionGUID: 4uDe8fUhSDGkT2v19xKzeA== X-CSE-MsgGUID: bcrQTk/5RTy+gMcZzkadVQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,178,1728975600"; d="scan'208";a="91573568" Received: from unknown (HELO JF5300-B11A338T.jf.intel.com) ([10.242.51.115]) by orviesa008.jf.intel.com with ESMTP; 22 Nov 2024 23:01:29 -0800 From: Kanchana P Sridhar To: linux-kernel@vger.kernel.org, linux-mm@kvack.org, hannes@cmpxchg.org, yosryahmed@google.com, nphamcs@gmail.com, chengming.zhou@linux.dev, usamaarif642@gmail.com, ryan.roberts@arm.com, ying.huang@intel.com, 21cnbao@gmail.com, akpm@linux-foundation.org, linux-crypto@vger.kernel.org, herbert@gondor.apana.org.au, davem@davemloft.net, clabbe@baylibre.com, ardb@kernel.org, ebiggers@google.com, surenb@google.com, kristen.c.accardi@intel.com Cc: wajdi.k.feghali@intel.com, vinodh.gopal@intel.com, kanchana.p.sridhar@intel.com Subject: [PATCH v4 08/10] crypto: iaa - Distribute compress jobs from all cores to all IAAs on a package. Date: Fri, 22 Nov 2024 23:01:25 -0800 Message-Id: <20241123070127.332773-9-kanchana.p.sridhar@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20241123070127.332773-1-kanchana.p.sridhar@intel.com> References: <20241123070127.332773-1-kanchana.p.sridhar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This change enables processes running on any logical core on a package to use all the IAA devices enabled on that package for compress jobs. In other words, compressions originating from any process in a package will be distributed in round-robin manner to the available IAA devices on the same package. The main premise behind this change is to make sure that no compress engines on any IAA device are un-utilized/under-utilized/over-utilized. In other words, the compress engines on all IAA devices are considered a global resource for that package, thus maximizing compression throughput. This allows the use of all IAA devices present in a given package for (batched) compressions originating from zswap/zram, from all cores on this package. A new per-cpu "global_wq_table" implements this in the iaa_crypto driver. We can think of the global WQ per IAA as a WQ to which all cores on that package can submit compress jobs. To avail of this feature, the user must configure 2 WQs per IAA in order to enable distribution of compress jobs to multiple IAA devices. Each IAA will have 2 WQs: wq.0 (local WQ): Used for decompress jobs from cores mapped by the cpu_to_iaa() "even balancing of logical cores to IAA devices" algorithm. wq.1 (global WQ): Used for compress jobs from *all* logical cores on that package. The iaa_crypto driver will place all global WQs from all same-package IAA devices in the global_wq_table per cpu on that package. When the driver receives a compress job, it will lookup the "next" global WQ in the cpu's global_wq_table to submit the descriptor. The starting wq in the global_wq_table for each cpu is the global wq associated with the IAA nearest to it, so that we stagger the starting global wq for each process. This results in very uniform usage of all IAAs for compress jobs. Two new driver module parameters are added for this feature: g_wqs_per_iaa (default 0): /sys/bus/dsa/drivers/crypto/g_wqs_per_iaa This represents the number of global WQs that can be configured per IAA device. The recommended setting is 1 to enable the use of this feature once the user configures 2 WQs per IAA using higher level scripts as described in Documentation/driver-api/crypto/iaa/iaa-crypto.rst. g_consec_descs_per_gwq (default 1): /sys/bus/dsa/drivers/crypto/g_consec_descs_per_gwq This represents the number of consecutive compress jobs that will be submitted to the same global WQ (i.e. to the same IAA device) from a given core, before moving to the next global WQ. The default is 1, which is also the recommended setting to avail of this feature. The decompress jobs from any core will be sent to the "local" IAA, namely the one that the driver assigns with the cpu_to_iaa() mapping algorithm that evenly balances the assignment of logical cores to IAA devices on a package. On a 2-package Sapphire Rapids server where each package has 56 cores and 4 IAA devices, this is how the compress/decompress jobs will be mapped when the user configures 2 WQs per IAA device (which implies wq.1 will be added to the global WQ table for each logical core on that package): package(s): 2 package0 CPU(s): 0-55,112-167 package1 CPU(s): 56-111,168-223 Compress jobs: -------------- package 0: iaa_crypto will send compress jobs from all cpus (0-55,112-167) to all IAA devices on the package (iax1/iax3/iax5/iax7) in round-robin manner: iaa: iax1 iax3 iax5 iax7 package 1: iaa_crypto will send compress jobs from all cpus (56-111,168-223) to all IAA devices on the package (iax9/iax11/iax13/iax15) in round-robin manner: iaa: iax9 iax11 iax13 iax15 Decompress jobs: ---------------- package 0: cpu 0-13,112-125 14-27,126-139 28-41,140-153 42-55,154-167 iaa: iax1 iax3 iax5 iax7 package 1: cpu 56-69,168-181 70-83,182-195 84-97,196-209 98-111,210-223 iaa: iax9 iax11 iax13 iax15 Signed-off-by: Kanchana P Sridhar --- drivers/crypto/intel/iaa/iaa_crypto.h | 1 + drivers/crypto/intel/iaa/iaa_crypto_main.c | 385 ++++++++++++++++++++- 2 files changed, 378 insertions(+), 8 deletions(-) diff --git a/drivers/crypto/intel/iaa/iaa_crypto.h b/drivers/crypto/intel/i= aa/iaa_crypto.h index ca317c5aaf27..ca7326d6e9bf 100644 --- a/drivers/crypto/intel/iaa/iaa_crypto.h +++ b/drivers/crypto/intel/iaa/iaa_crypto.h @@ -82,6 +82,7 @@ struct iaa_device { struct list_head wqs; =20 struct wq_table_entry *iaa_local_wqs; + struct wq_table_entry *iaa_global_wqs; =20 atomic64_t comp_calls; atomic64_t comp_bytes; diff --git a/drivers/crypto/intel/iaa/iaa_crypto_main.c b/drivers/crypto/in= tel/iaa/iaa_crypto_main.c index 28f2f5617bf0..1cbf92d1b3e5 100644 --- a/drivers/crypto/intel/iaa/iaa_crypto_main.c +++ b/drivers/crypto/intel/iaa/iaa_crypto_main.c @@ -42,6 +42,18 @@ static struct crypto_comp *deflate_generic_tfm; /* Per-cpu lookup table for balanced wqs */ static struct wq_table_entry __percpu *wq_table =3D NULL; =20 +static struct wq_table_entry **pkg_global_wq_tables =3D NULL; + +/* Per-cpu lookup table for global wqs shared by all cpus. */ +static struct wq_table_entry __percpu *global_wq_table =3D NULL; + +/* + * Per-cpu counter of consecutive descriptors allocated to + * the same wq in the global_wq_table, so that we know + * when to switch to the next wq in the global_wq_table. + */ +static int __percpu *num_consec_descs_per_wq =3D NULL; + /* Verify results of IAA compress or not */ static bool iaa_verify_compress =3D false; =20 @@ -79,6 +91,16 @@ static bool async_mode =3D true; /* Use interrupts */ static bool use_irq; =20 +/* Number of global wqs per iaa*/ +static int g_wqs_per_iaa =3D 0; + +/* + * Number of consecutive descriptors to allocate from a + * given global wq before switching to the next wq in + * the global_wq_table. + */ +static int g_consec_descs_per_gwq =3D 1; + static struct iaa_compression_mode *iaa_compression_modes[IAA_COMP_MODES_M= AX]; =20 LIST_HEAD(iaa_devices); @@ -180,6 +202,60 @@ static ssize_t sync_mode_store(struct device_driver *d= river, } static DRIVER_ATTR_RW(sync_mode); =20 +static ssize_t g_wqs_per_iaa_show(struct device_driver *driver, char *buf) +{ + return sprintf(buf, "%d\n", g_wqs_per_iaa); +} + +static ssize_t g_wqs_per_iaa_store(struct device_driver *driver, + const char *buf, size_t count) +{ + int ret =3D -EBUSY; + + mutex_lock(&iaa_devices_lock); + + if (iaa_crypto_enabled) + goto out; + + ret =3D kstrtoint(buf, 10, &g_wqs_per_iaa); + if (ret) + goto out; + + ret =3D count; +out: + mutex_unlock(&iaa_devices_lock); + + return ret; +} +static DRIVER_ATTR_RW(g_wqs_per_iaa); + +static ssize_t g_consec_descs_per_gwq_show(struct device_driver *driver, c= har *buf) +{ + return sprintf(buf, "%d\n", g_consec_descs_per_gwq); +} + +static ssize_t g_consec_descs_per_gwq_store(struct device_driver *driver, + const char *buf, size_t count) +{ + int ret =3D -EBUSY; + + mutex_lock(&iaa_devices_lock); + + if (iaa_crypto_enabled) + goto out; + + ret =3D kstrtoint(buf, 10, &g_consec_descs_per_gwq); + if (ret) + goto out; + + ret =3D count; +out: + mutex_unlock(&iaa_devices_lock); + + return ret; +} +static DRIVER_ATTR_RW(g_consec_descs_per_gwq); + /**************************** * Driver compression modes. ****************************/ @@ -465,7 +541,7 @@ static void remove_device_compression_modes(struct iaa_= device *iaa_device) ***********************************************************/ static struct iaa_device *iaa_device_alloc(struct idxd_device *idxd) { - struct wq_table_entry *local; + struct wq_table_entry *local, *global; struct iaa_device *iaa_device; =20 iaa_device =3D kzalloc(sizeof(*iaa_device), GFP_KERNEL); @@ -488,6 +564,20 @@ static struct iaa_device *iaa_device_alloc(struct idxd= _device *idxd) local->max_wqs =3D iaa_device->idxd->max_wqs; local->n_wqs =3D 0; =20 + /* IAA device's global wqs. */ + iaa_device->iaa_global_wqs =3D kzalloc(sizeof(struct wq_table_entry), GFP= _KERNEL); + if (!iaa_device->iaa_global_wqs) + goto err; + + global =3D iaa_device->iaa_global_wqs; + + global->wqs =3D kzalloc(iaa_device->idxd->max_wqs * sizeof(struct wq *), = GFP_KERNEL); + if (!global->wqs) + goto err; + + global->max_wqs =3D iaa_device->idxd->max_wqs; + global->n_wqs =3D 0; + INIT_LIST_HEAD(&iaa_device->wqs); =20 return iaa_device; @@ -499,6 +589,8 @@ static struct iaa_device *iaa_device_alloc(struct idxd_= device *idxd) kfree(iaa_device->iaa_local_wqs->wqs); kfree(iaa_device->iaa_local_wqs); } + if (iaa_device->iaa_global_wqs) + kfree(iaa_device->iaa_global_wqs); kfree(iaa_device); } =20 @@ -616,6 +708,12 @@ static void free_iaa_device(struct iaa_device *iaa_dev= ice) kfree(iaa_device->iaa_local_wqs); } =20 + if (iaa_device->iaa_global_wqs) { + if (iaa_device->iaa_global_wqs->wqs) + kfree(iaa_device->iaa_global_wqs->wqs); + kfree(iaa_device->iaa_global_wqs); + } + kfree(iaa_device); } =20 @@ -817,6 +915,58 @@ static inline int cpu_to_iaa(int cpu) return (nr_iaa - 1); } =20 +static void free_global_wq_table(void) +{ + if (global_wq_table) { + free_percpu(global_wq_table); + global_wq_table =3D NULL; + } + + if (num_consec_descs_per_wq) { + free_percpu(num_consec_descs_per_wq); + num_consec_descs_per_wq =3D NULL; + } + + pr_debug("freed global wq table\n"); +} + +static int pkg_global_wq_tables_alloc(void) +{ + int i, j; + + pkg_global_wq_tables =3D kzalloc(nr_packages * sizeof(*pkg_global_wq_tabl= es), GFP_KERNEL); + if (!pkg_global_wq_tables) + return -ENOMEM; + + for (i =3D 0; i < nr_packages; ++i) { + pkg_global_wq_tables[i] =3D kzalloc(sizeof(struct wq_table_entry), GFP_K= ERNEL); + + if (!pkg_global_wq_tables[i]) { + for (j =3D 0; j < i; ++j) + kfree(pkg_global_wq_tables[j]); + kfree(pkg_global_wq_tables); + pkg_global_wq_tables =3D NULL; + return -ENOMEM; + } + pkg_global_wq_tables[i]->wqs =3D NULL; + } + + return 0; +} + +static void pkg_global_wq_tables_dealloc(void) +{ + int i; + + for (i =3D 0; i < nr_packages; ++i) { + if (pkg_global_wq_tables[i]->wqs) + kfree(pkg_global_wq_tables[i]->wqs); + kfree(pkg_global_wq_tables[i]); + } + kfree(pkg_global_wq_tables); + pkg_global_wq_tables =3D NULL; +} + static int alloc_wq_table(int max_wqs) { struct wq_table_entry *entry; @@ -835,6 +985,35 @@ static int alloc_wq_table(int max_wqs) entry->cur_wq =3D 0; } =20 + global_wq_table =3D alloc_percpu(struct wq_table_entry); + if (!global_wq_table) + return 0; + + for (cpu =3D 0; cpu < nr_cpus; cpu++) { + entry =3D per_cpu_ptr(global_wq_table, cpu); + + entry->wqs =3D NULL; + entry->max_wqs =3D max_wqs; + entry->n_wqs =3D 0; + entry->cur_wq =3D 0; + } + + num_consec_descs_per_wq =3D alloc_percpu(int); + if (!num_consec_descs_per_wq) { + free_global_wq_table(); + return 0; + } + + for (cpu =3D 0; cpu < nr_cpus; cpu++) { + int *num_consec_descs =3D per_cpu_ptr(num_consec_descs_per_wq, cpu); + *num_consec_descs =3D 0; + } + + if (pkg_global_wq_tables_alloc()) { + free_global_wq_table(); + return 0; + } + pr_debug("initialized wq table\n"); =20 return 0; @@ -895,13 +1074,120 @@ static int wq_table_add_wqs(int iaa, int cpu) return ret; } =20 +static void pkg_global_wq_tables_reinit(void) +{ + int i, cur_iaa =3D 0, pkg =3D 0, nr_pkg_wqs =3D 0; + struct iaa_device *iaa_device; + struct wq_table_entry *global; + + if (!pkg_global_wq_tables) + return; + + /* Reallocate per-package wqs. */ + list_for_each_entry(iaa_device, &iaa_devices, list) { + global =3D iaa_device->iaa_global_wqs; + nr_pkg_wqs +=3D global->n_wqs; + + if (++cur_iaa =3D=3D nr_iaa_per_package) { + nr_pkg_wqs =3D nr_pkg_wqs ? max_t(int, iaa_device->idxd->max_wqs, nr_pk= g_wqs) : 0; + + if (pkg_global_wq_tables[pkg]->wqs) { + kfree(pkg_global_wq_tables[pkg]->wqs); + pkg_global_wq_tables[pkg]->wqs =3D NULL; + } + + if (nr_pkg_wqs) + pkg_global_wq_tables[pkg]->wqs =3D kzalloc(nr_pkg_wqs * + sizeof(struct wq *), + GFP_KERNEL); + + pkg_global_wq_tables[pkg]->n_wqs =3D 0; + pkg_global_wq_tables[pkg]->cur_wq =3D 0; + pkg_global_wq_tables[pkg]->max_wqs =3D nr_pkg_wqs; + + if (++pkg =3D=3D nr_packages) + break; + cur_iaa =3D 0; + nr_pkg_wqs =3D 0; + } + } + + pkg =3D 0; + cur_iaa =3D 0; + + /* Re-initialize per-package wqs. */ + list_for_each_entry(iaa_device, &iaa_devices, list) { + global =3D iaa_device->iaa_global_wqs; + + if (pkg_global_wq_tables[pkg]->wqs) + for (i =3D 0; i < global->n_wqs; ++i) + pkg_global_wq_tables[pkg]->wqs[pkg_global_wq_tables[pkg]->n_wqs++] =3D= global->wqs[i]; + + pr_debug("pkg_global_wq_tables[%d] has %d wqs", pkg, pkg_global_wq_table= s[pkg]->n_wqs); + + if (++cur_iaa =3D=3D nr_iaa_per_package) { + if (++pkg =3D=3D nr_packages) + break; + cur_iaa =3D 0; + } + } +} + +static void global_wq_table_add(int cpu, struct wq_table_entry *pkg_global= _wq_table) +{ + struct wq_table_entry *entry =3D per_cpu_ptr(global_wq_table, cpu); + + /* This could be NULL. */ + entry->wqs =3D pkg_global_wq_table->wqs; + entry->max_wqs =3D pkg_global_wq_table->max_wqs; + entry->n_wqs =3D pkg_global_wq_table->n_wqs; + entry->cur_wq =3D 0; + + if (entry->wqs) + pr_debug("%s: cpu %d: added %d iaa global wqs up to wq %d.%d\n", __func_= _, + cpu, entry->n_wqs, + entry->wqs[entry->n_wqs - 1]->idxd->id, + entry->wqs[entry->n_wqs - 1]->id); +} + +static void global_wq_table_set_start_wq(int cpu) +{ + struct wq_table_entry *entry =3D per_cpu_ptr(global_wq_table, cpu); + int start_wq =3D g_wqs_per_iaa * (cpu_to_iaa(cpu) % nr_iaa_per_package); + + if ((start_wq >=3D 0) && (start_wq < entry->n_wqs)) + entry->cur_wq =3D start_wq; +} + +static void global_wq_table_add_wqs(void) +{ + int cpu; + + if (!pkg_global_wq_tables) + return; + + for (cpu =3D 0; cpu < nr_cpus; cpu +=3D nr_cpus_per_package) { + /* cpu's on the same package get the same global_wq_table. */ + int package_id =3D topology_logical_package_id(cpu); + int pkg_cpu; + + for (pkg_cpu =3D cpu; pkg_cpu < cpu + nr_cpus_per_package; ++pkg_cpu) { + if (pkg_global_wq_tables[package_id]->n_wqs > 0) { + global_wq_table_add(pkg_cpu, pkg_global_wq_tables[package_id]); + global_wq_table_set_start_wq(pkg_cpu); + } + } + } +} + static int map_iaa_device_wqs(struct iaa_device *iaa_device) { - struct wq_table_entry *local; + struct wq_table_entry *local, *global; int ret =3D 0, n_wqs_added =3D 0; struct iaa_wq *iaa_wq; =20 local =3D iaa_device->iaa_local_wqs; + global =3D iaa_device->iaa_global_wqs; =20 list_for_each_entry(iaa_wq, &iaa_device->wqs, list) { if (iaa_wq->mapped && ++n_wqs_added) @@ -909,11 +1195,18 @@ static int map_iaa_device_wqs(struct iaa_device *iaa= _device) =20 pr_debug("iaa_device %px: processing wq %d.%d\n", iaa_device, iaa_device= ->idxd->id, iaa_wq->wq->id); =20 - if (WARN_ON(local->n_wqs =3D=3D local->max_wqs)) - break; + if ((!n_wqs_added || ((n_wqs_added + g_wqs_per_iaa) < iaa_device->n_wq))= && + (local->n_wqs < local->max_wqs)) { + + local->wqs[local->n_wqs++] =3D iaa_wq->wq; + pr_debug("iaa_device %px: added local wq %d.%d\n", iaa_device, iaa_devi= ce->idxd->id, iaa_wq->wq->id); + } else { + if (WARN_ON(global->n_wqs =3D=3D global->max_wqs)) + break; =20 - local->wqs[local->n_wqs++] =3D iaa_wq->wq; - pr_debug("iaa_device %px: added local wq %d.%d\n", iaa_device, iaa_devic= e->idxd->id, iaa_wq->wq->id); + global->wqs[global->n_wqs++] =3D iaa_wq->wq; + pr_debug("iaa_device %px: added global wq %d.%d\n", iaa_device, iaa_dev= ice->idxd->id, iaa_wq->wq->id); + } =20 iaa_wq->mapped =3D true; ++n_wqs_added; @@ -969,6 +1262,10 @@ static void rebalance_wq_table(void) } } =20 + if (iaa_crypto_enabled && pkg_global_wq_tables) { + pkg_global_wq_tables_reinit(); + global_wq_table_add_wqs(); + } pr_debug("Finished rebalance local wqs."); } =20 @@ -979,7 +1276,17 @@ static void free_wq_tables(void) wq_table =3D NULL; } =20 - pr_debug("freed local wq table\n"); + if (global_wq_table) { + free_percpu(global_wq_table); + global_wq_table =3D NULL; + } + + if (num_consec_descs_per_wq) { + free_percpu(num_consec_descs_per_wq); + num_consec_descs_per_wq =3D NULL; + } + + pr_debug("freed wq tables\n"); } =20 /*************************************************************** @@ -1002,6 +1309,35 @@ static struct idxd_wq *wq_table_next_wq(int cpu) return entry->wqs[entry->cur_wq]; } =20 +/* + * Caller should make sure to call only if the + * per_cpu_ptr "global_wq_table" is non-NULL + * and has at least one wq configured. + */ +static struct idxd_wq *global_wq_table_next_wq(int cpu) +{ + struct wq_table_entry *entry =3D per_cpu_ptr(global_wq_table, cpu); + int *num_consec_descs =3D per_cpu_ptr(num_consec_descs_per_wq, cpu); + + /* + * Fall-back to local IAA's wq if there were no global wqs configured + * for any IAA device, or if there were problems in setting up global + * wqs for this cpu's package. + */ + if (!entry->wqs) + return wq_table_next_wq(cpu); + + if ((*num_consec_descs) =3D=3D g_consec_descs_per_gwq) { + if (++entry->cur_wq >=3D entry->n_wqs) + entry->cur_wq =3D 0; + *num_consec_descs =3D 0; + } + + ++(*num_consec_descs); + + return entry->wqs[entry->cur_wq]; +} + /************************************************* * Core iaa_crypto compress/decompress functions. *************************************************/ @@ -1553,6 +1889,7 @@ static int iaa_comp_acompress(struct acomp_req *req) struct idxd_wq *wq; struct device *dev; int order =3D -1; + struct wq_table_entry *entry; =20 compression_ctx =3D crypto_tfm_ctx(tfm); =20 @@ -1571,8 +1908,15 @@ static int iaa_comp_acompress(struct acomp_req *req) disable_async =3D true; =20 cpu =3D get_cpu(); - wq =3D wq_table_next_wq(cpu); + entry =3D per_cpu_ptr(global_wq_table, cpu); + + if (!entry || !entry->wqs || entry->n_wqs =3D=3D 0) { + wq =3D wq_table_next_wq(cpu); + } else { + wq =3D global_wq_table_next_wq(cpu); + } put_cpu(); + if (!wq) { pr_debug("no wq configured for cpu=3D%d\n", cpu); return -ENODEV; @@ -2380,6 +2724,7 @@ static void iaa_crypto_remove(struct idxd_dev *idxd_d= ev) =20 if (nr_iaa =3D=3D 0) { iaa_crypto_enabled =3D false; + pkg_global_wq_tables_dealloc(); free_wq_tables(); BUG_ON(!list_empty(&iaa_devices)); INIT_LIST_HEAD(&iaa_devices); @@ -2449,6 +2794,20 @@ static int __init iaa_crypto_init_module(void) goto err_sync_attr_create; } =20 + ret =3D driver_create_file(&iaa_crypto_driver.drv, + &driver_attr_g_wqs_per_iaa); + if (ret) { + pr_debug("IAA g_wqs_per_iaa attr creation failed\n"); + goto err_g_wqs_per_iaa_attr_create; + } + + ret =3D driver_create_file(&iaa_crypto_driver.drv, + &driver_attr_g_consec_descs_per_gwq); + if (ret) { + pr_debug("IAA g_consec_descs_per_gwq attr creation failed\n"); + goto err_g_consec_descs_per_gwq_attr_create; + } + if (iaa_crypto_debugfs_init()) pr_warn("debugfs init failed, stats not available\n"); =20 @@ -2456,6 +2815,12 @@ static int __init iaa_crypto_init_module(void) out: return ret; =20 +err_g_consec_descs_per_gwq_attr_create: + driver_remove_file(&iaa_crypto_driver.drv, + &driver_attr_g_wqs_per_iaa); +err_g_wqs_per_iaa_attr_create: + driver_remove_file(&iaa_crypto_driver.drv, + &driver_attr_sync_mode); err_sync_attr_create: driver_remove_file(&iaa_crypto_driver.drv, &driver_attr_verify_compress); @@ -2479,6 +2844,10 @@ static void __exit iaa_crypto_cleanup_module(void) &driver_attr_sync_mode); driver_remove_file(&iaa_crypto_driver.drv, &driver_attr_verify_compress); + driver_remove_file(&iaa_crypto_driver.drv, + &driver_attr_g_wqs_per_iaa); + driver_remove_file(&iaa_crypto_driver.drv, + &driver_attr_g_consec_descs_per_gwq); idxd_driver_unregister(&iaa_crypto_driver); iaa_aecs_cleanup_fixed(); crypto_free_comp(deflate_generic_tfm); --=20 2.27.0 From nobody Sun Nov 24 06:51:17 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D24B318A6DD; Sat, 23 Nov 2024 07:01:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="RpI12vWN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1732345296; x=1763881296; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7BRL3M7QAqVe3HBLgp+ukwHwPsCAsGa3NLBo+BVhcjM=; b=RpI12vWNAC6RX6jfWW0VcnM8dPSsJyFYyU9/Uvy4FAxatHuzyuOgstum HueWO5UrBdCUDVY6BGhX45dWbrMlqUF//PGMs/LSmz70UolQZB4m9bDPb OkaMkER0OMARZHeaqFHgJOIYDNaiK5RIywE+R1GBOhC3oTKExTSB14dth 0TEoygyRT1LA7bIjygZmnKHxxFT+iKejxrX2rS2AwfF7hEGVDBHAZvfb/ KCXtcM2Gi/sy94PNcfJAImn8LOyWmk2kIfCRg2nNGwYW+n7bd8PVcUgBp hhDO30LIo6m1s1qO2blV95UJppeg5/xwBKOvZtvuYtTUGAiHz+i8NOynD Q==; X-CSE-ConnectionGUID: LMfbRfOZQHCtGj9EMFs0SA== X-CSE-MsgGUID: r/wJtRRmTieb/jriAF3mYw== X-IronPort-AV: E=McAfee;i="6700,10204,11264"; a="32435556" X-IronPort-AV: E=Sophos;i="6.12,178,1728975600"; d="scan'208";a="32435556" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Nov 2024 23:01:30 -0800 X-CSE-ConnectionGUID: osjt3+rHSjukUyKzXXPNhQ== X-CSE-MsgGUID: lYHG2HlqS9GEU+WtlJ2VGQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,178,1728975600"; d="scan'208";a="91573571" Received: from unknown (HELO JF5300-B11A338T.jf.intel.com) ([10.242.51.115]) by orviesa008.jf.intel.com with ESMTP; 22 Nov 2024 23:01:29 -0800 From: Kanchana P Sridhar To: linux-kernel@vger.kernel.org, linux-mm@kvack.org, hannes@cmpxchg.org, yosryahmed@google.com, nphamcs@gmail.com, chengming.zhou@linux.dev, usamaarif642@gmail.com, ryan.roberts@arm.com, ying.huang@intel.com, 21cnbao@gmail.com, akpm@linux-foundation.org, linux-crypto@vger.kernel.org, herbert@gondor.apana.org.au, davem@davemloft.net, clabbe@baylibre.com, ardb@kernel.org, ebiggers@google.com, surenb@google.com, kristen.c.accardi@intel.com Cc: wajdi.k.feghali@intel.com, vinodh.gopal@intel.com, kanchana.p.sridhar@intel.com Subject: [PATCH v4 09/10] mm: zswap: Allocate pool batching resources if the crypto_alg supports batching. Date: Fri, 22 Nov 2024 23:01:26 -0800 Message-Id: <20241123070127.332773-10-kanchana.p.sridhar@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20241123070127.332773-1-kanchana.p.sridhar@intel.com> References: <20241123070127.332773-1-kanchana.p.sridhar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch does the following: 1) Modifies the definition of "struct crypto_acomp_ctx" to represent a configurable number of acomp_reqs and buffers. Adds a "nr_reqs" to "struct crypto_acomp_ctx" to contain the nr of resources that will be allocated in the cpu onlining code. 2) The zswap_cpu_comp_prepare() cpu onlining code will detect if the crypto_acomp created for the pool (in other words, the zswap compression algorithm) has registered an implementation for batch_compress() and batch_decompress(). If so, it will set "nr_reqs" to SWAP_CRYPTO_BATCH_SIZE and allocate these many reqs/buffers, and set the acomp_ctx->nr_reqs accordingly. If the crypto_acomp does not support batching, "nr_reqs" defaults to 1. 3) Adds a "bool can_batch" to "struct zswap_pool" that step (2) will set to true if the batching API are present for the crypto_acomp. SWAP_CRYPTO_BATCH_SIZE is set to 8, which will be the IAA compress batching "sub-batch" size when zswap_batch_store() is processing a large folio. This represents the nr of buffers that can be compressed/decompressed in parallel by Intel IAA hardware. Signed-off-by: Kanchana P Sridhar --- include/linux/zswap.h | 7 +++ mm/zswap.c | 120 +++++++++++++++++++++++++++++++----------- 2 files changed, 95 insertions(+), 32 deletions(-) diff --git a/include/linux/zswap.h b/include/linux/zswap.h index d961ead91bf1..9ad27ab3d222 100644 --- a/include/linux/zswap.h +++ b/include/linux/zswap.h @@ -7,6 +7,13 @@ =20 struct lruvec; =20 +/* + * For IAA compression batching: + * Maximum number of IAA acomp compress requests that will be processed + * in a batch: in parallel, if iaa_crypto async/no irq mode is enabled + * (the default); else sequentially, if iaa_crypto sync mode is in effect. + */ +#define SWAP_CRYPTO_BATCH_SIZE 8UL extern atomic_long_t zswap_stored_pages; =20 #ifdef CONFIG_ZSWAP diff --git a/mm/zswap.c b/mm/zswap.c index f6316b66fb23..173f7632990e 100644 --- a/mm/zswap.c +++ b/mm/zswap.c @@ -143,9 +143,10 @@ bool zswap_never_enabled(void) =20 struct crypto_acomp_ctx { struct crypto_acomp *acomp; - struct acomp_req *req; + struct acomp_req **reqs; + u8 **buffers; + unsigned int nr_reqs; struct crypto_wait wait; - u8 *buffer; struct mutex mutex; bool is_sleepable; }; @@ -158,6 +159,7 @@ struct crypto_acomp_ctx { */ struct zswap_pool { struct zpool *zpool; + bool can_batch; struct crypto_acomp_ctx __percpu *acomp_ctx; struct percpu_ref ref; struct list_head list; @@ -285,6 +287,8 @@ static struct zswap_pool *zswap_pool_create(char *type,= char *compressor) goto error; } =20 + pool->can_batch =3D false; + ret =3D cpuhp_state_add_instance(CPUHP_MM_ZSWP_POOL_PREPARE, &pool->node); if (ret) @@ -818,49 +822,90 @@ static int zswap_cpu_comp_prepare(unsigned int cpu, s= truct hlist_node *node) struct zswap_pool *pool =3D hlist_entry(node, struct zswap_pool, node); struct crypto_acomp_ctx *acomp_ctx =3D per_cpu_ptr(pool->acomp_ctx, cpu); struct crypto_acomp *acomp; - struct acomp_req *req; - int ret; + unsigned int nr_reqs =3D 1; + int ret =3D -ENOMEM; + int i, j; =20 mutex_init(&acomp_ctx->mutex); - - acomp_ctx->buffer =3D kmalloc_node(PAGE_SIZE * 2, GFP_KERNEL, cpu_to_node= (cpu)); - if (!acomp_ctx->buffer) - return -ENOMEM; + acomp_ctx->nr_reqs =3D 0; =20 acomp =3D crypto_alloc_acomp_node(pool->tfm_name, 0, 0, cpu_to_node(cpu)); if (IS_ERR(acomp)) { pr_err("could not alloc crypto acomp %s : %ld\n", pool->tfm_name, PTR_ERR(acomp)); - ret =3D PTR_ERR(acomp); - goto acomp_fail; + return PTR_ERR(acomp); } acomp_ctx->acomp =3D acomp; acomp_ctx->is_sleepable =3D acomp_is_async(acomp); =20 - req =3D acomp_request_alloc(acomp_ctx->acomp); - if (!req) { - pr_err("could not alloc crypto acomp_request %s\n", - pool->tfm_name); - ret =3D -ENOMEM; + /* + * Create the necessary batching resources if the crypto acomp alg + * implements the batch_compress and batch_decompress API. + */ + if (acomp_has_async_batching(acomp)) { + pool->can_batch =3D true; + nr_reqs =3D SWAP_CRYPTO_BATCH_SIZE; + pr_info_once("Creating acomp_ctx with %d reqs for batching since crypto = acomp %s\nhas registered batch_compress() and batch_decompress()\n", + nr_reqs, pool->tfm_name); + } + + acomp_ctx->buffers =3D kmalloc_node(nr_reqs * sizeof(u8 *), GFP_KERNEL, c= pu_to_node(cpu)); + if (!acomp_ctx->buffers) + goto buf_fail; + + for (i =3D 0; i < nr_reqs; ++i) { + acomp_ctx->buffers[i] =3D kmalloc_node(PAGE_SIZE * 2, GFP_KERNEL, cpu_to= _node(cpu)); + if (!acomp_ctx->buffers[i]) { + for (j =3D 0; j < i; ++j) + kfree(acomp_ctx->buffers[j]); + kfree(acomp_ctx->buffers); + ret =3D -ENOMEM; + goto buf_fail; + } + } + + acomp_ctx->reqs =3D kmalloc_node(nr_reqs * sizeof(struct acomp_req *), GF= P_KERNEL, cpu_to_node(cpu)); + if (!acomp_ctx->reqs) goto req_fail; + + for (i =3D 0; i < nr_reqs; ++i) { + acomp_ctx->reqs[i] =3D acomp_request_alloc(acomp_ctx->acomp); + if (!acomp_ctx->reqs[i]) { + pr_err("could not alloc crypto acomp_request reqs[%d] %s\n", + i, pool->tfm_name); + for (j =3D 0; j < i; ++j) + acomp_request_free(acomp_ctx->reqs[j]); + kfree(acomp_ctx->reqs); + ret =3D -ENOMEM; + goto req_fail; + } } - acomp_ctx->req =3D req; =20 + /* + * The crypto_wait is used only in fully synchronous, i.e., with scomp + * or non-poll mode of acomp, hence there is only one "wait" per + * acomp_ctx, with callback set to reqs[0], under the assumption that + * there is at least 1 request per acomp_ctx. + */ crypto_init_wait(&acomp_ctx->wait); /* * if the backend of acomp is async zip, crypto_req_done() will wakeup * crypto_wait_req(); if the backend of acomp is scomp, the callback * won't be called, crypto_wait_req() will return without blocking. */ - acomp_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, + acomp_request_set_callback(acomp_ctx->reqs[0], CRYPTO_TFM_REQ_MAY_BACKLOG, crypto_req_done, &acomp_ctx->wait); =20 + acomp_ctx->nr_reqs =3D nr_reqs; return 0; =20 req_fail: + for (i =3D 0; i < nr_reqs; ++i) + kfree(acomp_ctx->buffers[i]); + kfree(acomp_ctx->buffers); +buf_fail: crypto_free_acomp(acomp_ctx->acomp); -acomp_fail: - kfree(acomp_ctx->buffer); + pool->can_batch =3D false; return ret; } =20 @@ -870,11 +915,22 @@ static int zswap_cpu_comp_dead(unsigned int cpu, stru= ct hlist_node *node) struct crypto_acomp_ctx *acomp_ctx =3D per_cpu_ptr(pool->acomp_ctx, cpu); =20 if (!IS_ERR_OR_NULL(acomp_ctx)) { - if (!IS_ERR_OR_NULL(acomp_ctx->req)) - acomp_request_free(acomp_ctx->req); + int i; + + for (i =3D 0; i < acomp_ctx->nr_reqs; ++i) + if (!IS_ERR_OR_NULL(acomp_ctx->reqs[i])) + acomp_request_free(acomp_ctx->reqs[i]); + kfree(acomp_ctx->reqs); + + for (i =3D 0; i < acomp_ctx->nr_reqs; ++i) + kfree(acomp_ctx->buffers[i]); + kfree(acomp_ctx->buffers); + if (!IS_ERR_OR_NULL(acomp_ctx->acomp)) crypto_free_acomp(acomp_ctx->acomp); - kfree(acomp_ctx->buffer); + + acomp_ctx->nr_reqs =3D 0; + acomp_ctx =3D NULL; } =20 return 0; @@ -897,7 +953,7 @@ static bool zswap_compress(struct page *page, struct zs= wap_entry *entry, =20 mutex_lock(&acomp_ctx->mutex); =20 - dst =3D acomp_ctx->buffer; + dst =3D acomp_ctx->buffers[0]; sg_init_table(&input, 1); sg_set_page(&input, page, PAGE_SIZE, 0); =20 @@ -907,7 +963,7 @@ static bool zswap_compress(struct page *page, struct zs= wap_entry *entry, * giving the dst buffer with enough length to avoid buffer overflow. */ sg_init_one(&output, dst, PAGE_SIZE * 2); - acomp_request_set_params(acomp_ctx->req, &input, &output, PAGE_SIZE, dlen= ); + acomp_request_set_params(acomp_ctx->reqs[0], &input, &output, PAGE_SIZE, = dlen); =20 /* * it maybe looks a little bit silly that we send an asynchronous request, @@ -921,8 +977,8 @@ static bool zswap_compress(struct page *page, struct zs= wap_entry *entry, * but in different threads running on different cpu, we have different * acomp instance, so multiple threads can do (de)compression in parallel. */ - comp_ret =3D crypto_wait_req(crypto_acomp_compress(acomp_ctx->req), &acom= p_ctx->wait); - dlen =3D acomp_ctx->req->dlen; + comp_ret =3D crypto_wait_req(crypto_acomp_compress(acomp_ctx->reqs[0]), &= acomp_ctx->wait); + dlen =3D acomp_ctx->reqs[0]->dlen; if (comp_ret) goto unlock; =20 @@ -975,20 +1031,20 @@ static void zswap_decompress(struct zswap_entry *ent= ry, struct folio *folio) */ if ((acomp_ctx->is_sleepable && !zpool_can_sleep_mapped(zpool)) || !virt_addr_valid(src)) { - memcpy(acomp_ctx->buffer, src, entry->length); - src =3D acomp_ctx->buffer; + memcpy(acomp_ctx->buffers[0], src, entry->length); + src =3D acomp_ctx->buffers[0]; zpool_unmap_handle(zpool, entry->handle); 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a="32435568" X-IronPort-AV: E=Sophos;i="6.12,178,1728975600"; d="scan'208";a="32435568" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Nov 2024 23:01:30 -0800 X-CSE-ConnectionGUID: qCe775yiSni/CxtTRPBmJQ== X-CSE-MsgGUID: Aa7lpLhRRe+MyuU+gGClTA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,178,1728975600"; d="scan'208";a="91573574" Received: from unknown (HELO JF5300-B11A338T.jf.intel.com) ([10.242.51.115]) by orviesa008.jf.intel.com with ESMTP; 22 Nov 2024 23:01:29 -0800 From: Kanchana P Sridhar To: linux-kernel@vger.kernel.org, linux-mm@kvack.org, hannes@cmpxchg.org, yosryahmed@google.com, nphamcs@gmail.com, chengming.zhou@linux.dev, usamaarif642@gmail.com, ryan.roberts@arm.com, ying.huang@intel.com, 21cnbao@gmail.com, akpm@linux-foundation.org, linux-crypto@vger.kernel.org, herbert@gondor.apana.org.au, davem@davemloft.net, clabbe@baylibre.com, ardb@kernel.org, ebiggers@google.com, surenb@google.com, kristen.c.accardi@intel.com Cc: wajdi.k.feghali@intel.com, vinodh.gopal@intel.com, kanchana.p.sridhar@intel.com Subject: [PATCH v4 10/10] mm: zswap: Compress batching with Intel IAA in zswap_batch_store() of large folios. Date: Fri, 22 Nov 2024 23:01:27 -0800 Message-Id: <20241123070127.332773-11-kanchana.p.sridhar@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20241123070127.332773-1-kanchana.p.sridhar@intel.com> References: <20241123070127.332773-1-kanchana.p.sridhar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch adds two new zswap API: 1) bool zswap_can_batch(void); 2) void zswap_batch_store(struct folio_batch *batch, int *errors); Higher level mm code, for instance, swap_writepage(), can query if the current zswap pool supports batching, by calling zswap_can_batch(). If so it can invoke zswap_batch_store() to swapout a large folio much more efficiently to zswap, instead of calling zswap_store(). Hence, on systems with Intel IAA hardware compress/decompress accelerators, swap_writepage() will invoke zswap_batch_store() for large folios. zswap_batch_store() will call crypto_acomp_batch_compress() to compress up to SWAP_CRYPTO_BATCH_SIZE (i.e. 8) pages in large folios in parallel using the multiple compress engines available in IAA. On platforms with multiple IAA devices per package, compress jobs from all cores in a package will be distributed among all IAA devices in the package by the iaa_crypto driver. The newly added zswap_batch_store() follows the general structure of zswap_store(). Some amount of restructuring and optimization is done to minimize failure points for a batch, fail early and maximize the zswap store pipeline occupancy with SWAP_CRYPTO_BATCH_SIZE pages, potentially from multiple folios in future. This is intended to maximize reclaim throughput with the IAA hardware parallel compressions. Suggested-by: Johannes Weiner Suggested-by: Yosry Ahmed Signed-off-by: Kanchana P Sridhar --- include/linux/zswap.h | 12 + mm/page_io.c | 16 +- mm/zswap.c | 639 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 666 insertions(+), 1 deletion(-) diff --git a/include/linux/zswap.h b/include/linux/zswap.h index 9ad27ab3d222..a05f59139a6e 100644 --- a/include/linux/zswap.h +++ b/include/linux/zswap.h @@ -4,6 +4,7 @@ =20 #include #include +#include =20 struct lruvec; =20 @@ -33,6 +34,8 @@ struct zswap_lruvec_state { =20 unsigned long zswap_total_pages(void); bool zswap_store(struct folio *folio); +bool zswap_can_batch(void); +void zswap_batch_store(struct folio_batch *batch, int *errors); bool zswap_load(struct folio *folio); void zswap_invalidate(swp_entry_t swp); int zswap_swapon(int type, unsigned long nr_pages); @@ -51,6 +54,15 @@ static inline bool zswap_store(struct folio *folio) return false; } =20 +static inline bool zswap_can_batch(void) +{ + return false; +} + +static inline void zswap_batch_store(struct folio_batch *batch, int *error= s) +{ +} + static inline bool zswap_load(struct folio *folio) { return false; diff --git a/mm/page_io.c b/mm/page_io.c index 4b4ea8e49cf6..271d3a40c0c1 100644 --- a/mm/page_io.c +++ b/mm/page_io.c @@ -276,7 +276,21 @@ int swap_writepage(struct page *page, struct writeback= _control *wbc) */ swap_zeromap_folio_clear(folio); } - if (zswap_store(folio)) { + + if (folio_test_large(folio) && zswap_can_batch()) { + struct folio_batch batch; + int error =3D -1; + + folio_batch_init(&batch); + folio_batch_add(&batch, folio); + zswap_batch_store(&batch, &error); + + if (!error) { + count_mthp_stat(folio_order(folio), MTHP_STAT_ZSWPOUT); + folio_unlock(folio); + return 0; + } + } else if (zswap_store(folio)) { count_mthp_stat(folio_order(folio), MTHP_STAT_ZSWPOUT); folio_unlock(folio); return 0; diff --git a/mm/zswap.c b/mm/zswap.c index 173f7632990e..53c8e39b778b 100644 --- a/mm/zswap.c +++ b/mm/zswap.c @@ -229,6 +229,80 @@ static DEFINE_MUTEX(zswap_init_lock); /* init completed, but couldn't create the initial pool */ static bool zswap_has_pool; =20 +/* + * struct zswap_batch_store_sub_batch: + * + * This represents a sub-batch of SWAP_CRYPTO_BATCH_SIZE pages during IAA + * compress batching of a folio or (conceptually, a reclaim batch of) foli= os. + * The new zswap_batch_store() API will break down the batch of folios bei= ng + * reclaimed into sub-batches of SWAP_CRYPTO_BATCH_SIZE pages, batch compr= ess + * the pages by calling the iaa_crypto driver API crypto_acomp_batch_compr= ess(); + * and storing the sub-batch in zpool/xarray before updating objcg/vm/zswap + * stats. + * + * Although the page itself is represented directly, the structure adds a + * "u8 folio_id" to represent an index for the folio in a conceptual + * "reclaim batch of folios" that can be passed to zswap_store(). Conceptu= ally, + * this allows for up to 256 folios that can be passed to zswap_store(). + * Even though the folio_id seems redundant in the context of a single lar= ge + * folio being stored by zswap, it does simplify error handling and redund= ant + * computes/rewinding state, all of which can add latency. Since the + * zswap_batch_store() of a large folio can fail for any of these reasons = -- + * compress errors, zpool malloc errors, xarray store errors -- the proced= ures + * that detect these errors for a sub-batch, can all call a single cleanup + * procedure, zswap_batch_cleanup(), which will de-allocate zpool memory a= nd + * zswap_entries for the sub-batch and set the "errors[folio_id]" to -EINV= AL. + * All subsequent procedures that operate on a sub-batch will do nothing i= f the + * errors[folio_id] is non-0. Hence, the folio_id facilitates the use of t= he + * "errors" passed to zswap_batch_store() as a global folio error status f= or a + * single folio (which could also be a folio in the folio_batch). + * + * The sub-batch concept could be further evolved to use pipelining to + * overlap CPU computes with IAA computes. For instance, we could stage + * the post-compress computes for sub-batch "N-1" to happen in parallel wi= th + * IAA batch compression of sub-batch "N". + * + * We begin by developing the concept of compress batching. Pipelining with + * overlap can be future work. + * + * @pages: The individual pages in the sub-batch. There are no assumptions + * about all of them belonging to the same folio. + * @dsts: The destination buffers for batch compress of the sub-batch. + * @dlens: The destination length constraints, and eventual compressed len= gths + * of successful compressions. + * @comp_errors: The compress error status for each page in the sub-batch,= set + * by crypto_acomp_batch_compress(). + * @folio_ids: The containing folio_id of each sub-batch page. + * @swpentries: The page_swap_entry() for each corresponding sub-batch pag= e. + * @objcgs: The objcg for each corresponding sub-batch page. + * @entries: The zswap_entry for each corresponding sub-batch page. + * @nr_pages: Total number of pages in @sub_batch. + * @pool: A valid zswap_pool that can_batch. + * + * Note: + * The max sub-batch size is SWAP_CRYPTO_BATCH_SIZE, currently 8UL. + * Hence, if SWAP_CRYPTO_BATCH_SIZE exceeds 256, @nr_pages needs to become= u16. + * The sub-batch representation is future-proofed to a small extent to be = able + * to easily scale the zswap_batch_store() implementation to handle a conc= eptual + * "reclaim batch of folios"; without addding too much complexity, while + * benefiting from simpler error handling, localized sub-batch resources c= leanup + * and avoiding expensive rewinding state. If this conceptual number of re= claim + * folios sent to zswap_batch_store() exceeds 256, @folio_ids needs to + * become u16. + */ +struct zswap_batch_store_sub_batch { + struct page *pages[SWAP_CRYPTO_BATCH_SIZE]; + u8 *dsts[SWAP_CRYPTO_BATCH_SIZE]; + unsigned int dlens[SWAP_CRYPTO_BATCH_SIZE]; + int comp_errors[SWAP_CRYPTO_BATCH_SIZE]; /* folio error status. */ + u8 folio_ids[SWAP_CRYPTO_BATCH_SIZE]; + swp_entry_t swpentries[SWAP_CRYPTO_BATCH_SIZE]; + struct obj_cgroup *objcgs[SWAP_CRYPTO_BATCH_SIZE]; + struct zswap_entry *entries[SWAP_CRYPTO_BATCH_SIZE]; + u8 nr_pages; + struct zswap_pool *pool; +}; + /********************************* * helpers and fwd declarations **********************************/ @@ -1705,6 +1779,571 @@ void zswap_invalidate(swp_entry_t swp) zswap_entry_free(entry); } =20 +/****************************************************** + * zswap_batch_store() with compress batching. + ******************************************************/ + +/* + * Note: If SWAP_CRYPTO_BATCH_SIZE exceeds 256, change the + * u8 stack variables in the next several functions, to u16. + */ +bool zswap_can_batch(void) +{ + struct zswap_pool *pool; + bool ret =3D false; + + pool =3D zswap_pool_current_get(); + + if (!pool) + return ret; + + if (pool->can_batch) + ret =3D true; + + zswap_pool_put(pool); + + return ret; +} + +/* + * If the zswap store fails or zswap is disabled, we must invalidate + * the possibly stale entries which were previously stored at the + * offsets corresponding to each page of the folio. Otherwise, + * writeback could overwrite the new data in the swapfile. + */ +static void zswap_delete_stored_entries(struct folio *folio) +{ + swp_entry_t swp =3D folio->swap; + unsigned type =3D swp_type(swp); + pgoff_t offset =3D swp_offset(swp); + struct zswap_entry *entry; + struct xarray *tree; + long index; + + for (index =3D 0; index < folio_nr_pages(folio); ++index) { + tree =3D swap_zswap_tree(swp_entry(type, offset + index)); + entry =3D xa_erase(tree, offset + index); + if (entry) + zswap_entry_free(entry); + } +} + +static __always_inline void zswap_batch_reset(struct zswap_batch_store_sub= _batch *sb) +{ + sb->nr_pages =3D 0; +} + +/* + * Upon encountering the first sub-batch page in a folio with an error due= to + * any of the following: + * - compression + * - zpool malloc + * - xarray store + * , cleanup the sub-batch resources (zpool memory, zswap_entry) for all o= ther + * sub_batch elements belonging to the same folio, using the "error_folio_= id". + * + * Set the "errors[error_folio_id] to signify to all downstream computes in + * zswap_batch_store(), that no further processing is required for the fol= io + * with "error_folio_id" in the batch: this folio's zswap store status will + * be considered an error, and existing zswap_entries in the xarray will be + * deleted before zswap_batch_store() exits. + */ +static void zswap_batch_cleanup(struct zswap_batch_store_sub_batch *sb, + int *errors, + u8 error_folio_id) +{ + u8 i; + + if (errors[error_folio_id]) + return; + + for (i =3D 0; i < sb->nr_pages; ++i) { + if (sb->folio_ids[i] =3D=3D error_folio_id) { + if (sb->entries[i]) { + if (!IS_ERR_VALUE(sb->entries[i]->handle)) + zpool_free(sb->pool->zpool, sb->entries[i]->handle); + + zswap_entry_cache_free(sb->entries[i]); + sb->entries[i] =3D NULL; + } + } + } + + errors[error_folio_id] =3D -EINVAL; +} + +/* + * Returns true if the entry was successfully + * stored in the xarray, and false otherwise. + */ +static bool zswap_store_entry(swp_entry_t page_swpentry, struct zswap_entr= y *entry) +{ + struct zswap_entry *old =3D xa_store(swap_zswap_tree(page_swpentry), + swp_offset(page_swpentry), + entry, GFP_KERNEL); + if (xa_is_err(old)) { + int err =3D xa_err(old); + + WARN_ONCE(err !=3D -ENOMEM, "unexpected xarray error: %d\n", err); + zswap_reject_alloc_fail++; + return false; + } + + /* + * We may have had an existing entry that became stale when + * the folio was redirtied and now the new version is being + * swapped out. Get rid of the old. + */ + if (old) + zswap_entry_free(old); + + return true; +} + +/* + * The stats accounting makes no assumptions about all pages in the sub-ba= tch + * belonging to the same folio, or having the same objcg; while still doing + * the updates in aggregation. + */ +static void zswap_batch_xarray_stats(struct zswap_batch_store_sub_batch *s= b, + int *errors) +{ + int nr_objcg_pages =3D 0, nr_pages =3D 0; + struct obj_cgroup *objcg =3D NULL; + size_t compressed_bytes =3D 0; + u8 i; + + for (i =3D 0; i < sb->nr_pages; ++i) { + if (errors[sb->folio_ids[i]]) + continue; + + if (!zswap_store_entry(sb->swpentries[i], sb->entries[i])) { + zswap_batch_cleanup(sb, errors, sb->folio_ids[i]); + continue; + } + + /* + * The entry is successfully compressed and stored in the tree, + * there is no further possibility of failure. Grab refs to the + * pool and objcg. These refs will be dropped by + * zswap_entry_free() when the entry is removed from the tree. + */ + zswap_pool_get(sb->pool); + if (sb->objcgs[i]) + obj_cgroup_get(sb->objcgs[i]); + + /* + * We finish initializing the entry while it's already in xarray. + * This is safe because: + * + * 1. Concurrent stores and invalidations are excluded by folio + * lock. + * + * 2. Writeback is excluded by the entry not being on the LRU yet. + * The publishing order matters to prevent writeback from seeing + * an incoherent entry. + */ + sb->entries[i]->pool =3D sb->pool; + sb->entries[i]->swpentry =3D sb->swpentries[i]; + sb->entries[i]->objcg =3D sb->objcgs[i]; + sb->entries[i]->referenced =3D true; + if (sb->entries[i]->length) { + INIT_LIST_HEAD(&(sb->entries[i]->lru)); + zswap_lru_add(&zswap_list_lru, sb->entries[i]); + } + + if (!objcg && sb->objcgs[i]) { + objcg =3D sb->objcgs[i]; + } else if (objcg && sb->objcgs[i] && (objcg !=3D sb->objcgs[i])) { + obj_cgroup_charge_zswap(objcg, compressed_bytes); + count_objcg_events(objcg, ZSWPOUT, nr_objcg_pages); + compressed_bytes =3D 0; + nr_objcg_pages =3D 0; + objcg =3D sb->objcgs[i]; + } + + if (sb->objcgs[i]) { + compressed_bytes +=3D sb->entries[i]->length; + ++nr_objcg_pages; + } + + ++nr_pages; + } /* for sub-batch pages. */ + + if (objcg) { + obj_cgroup_charge_zswap(objcg, compressed_bytes); + count_objcg_events(objcg, ZSWPOUT, nr_objcg_pages); + } + + atomic_long_add(nr_pages, &zswap_stored_pages); + count_vm_events(ZSWPOUT, nr_pages); +} + +static void zswap_batch_zpool_store(struct zswap_batch_store_sub_batch *sb, + int *errors) +{ + u8 i; + + for (i =3D 0; i < sb->nr_pages; ++i) { + struct zpool *zpool; + unsigned long handle; + char *buf; + gfp_t gfp; + int err; + + /* Skip pages belonging to folios that had compress errors. */ + if (errors[sb->folio_ids[i]]) + continue; + + zpool =3D sb->pool->zpool; + gfp =3D __GFP_NORETRY | __GFP_NOWARN | __GFP_KSWAPD_RECLAIM; + if (zpool_malloc_support_movable(zpool)) + gfp |=3D __GFP_HIGHMEM | __GFP_MOVABLE; + err =3D zpool_malloc(zpool, sb->dlens[i], gfp, &handle); + + if (err) { + if (err =3D=3D -ENOSPC) + zswap_reject_compress_poor++; + else + zswap_reject_alloc_fail++; + + /* + * A zpool malloc error should trigger cleanup for + * other same-folio pages in the sub-batch, and zpool + * resources/zswap_entries for those pages should be + * de-allocated. + */ + zswap_batch_cleanup(sb, errors, sb->folio_ids[i]); + continue; + } + + buf =3D zpool_map_handle(zpool, handle, ZPOOL_MM_WO); + memcpy(buf, sb->dsts[i], sb->dlens[i]); + zpool_unmap_handle(zpool, handle); + + sb->entries[i]->handle =3D handle; + sb->entries[i]->length =3D sb->dlens[i]; + } +} + +static void zswap_batch_proc_comp_errors(struct zswap_batch_store_sub_batc= h *sb, + int *errors) +{ + u8 i; + + for (i =3D 0; i < sb->nr_pages; ++i) { + if (sb->comp_errors[i]) { + if (sb->comp_errors[i] =3D=3D -ENOSPC) + zswap_reject_compress_poor++; + else + zswap_reject_compress_fail++; + + if (!errors[sb->folio_ids[i]]) + zswap_batch_cleanup(sb, errors, sb->folio_ids[i]); + } + } +} + +/* + * Batch compress up to SWAP_CRYPTO_BATCH_SIZE pages with IAA. + * It is important to note that the SWAP_CRYPTO_BATCH_SIZE resources + * resources are allocated for the pool's per-cpu acomp_ctx during cpu + * hotplug only if the crypto_acomp has registered either + * batch_compress() and batch_decompress(). + * The iaa_crypto driver registers implementations for both these API. + * Hence, if IAA is the zswap compressor, the call to + * crypto_acomp_batch_compress() will compress the pages in parallel, + * resulting in significant performance improvements as compared to + * software compressors. + */ +static void zswap_batch_compress(struct zswap_batch_store_sub_batch *sb, + int *errors) +{ + struct crypto_acomp_ctx *acomp_ctx =3D raw_cpu_ptr(sb->pool->acomp_ctx); + u8 i; + + mutex_lock(&acomp_ctx->mutex); + + BUG_ON(acomp_ctx->nr_reqs !=3D SWAP_CRYPTO_BATCH_SIZE); + + for (i =3D 0; i < sb->nr_pages; ++i) { + sb->dsts[i] =3D acomp_ctx->buffers[i]; + sb->dlens[i] =3D PAGE_SIZE; + } + + /* + * Batch compress sub-batch "N". If IAA is the compressor, the + * hardware will compress multiple pages in parallel. + */ + crypto_acomp_batch_compress( + acomp_ctx->reqs, + &acomp_ctx->wait, + sb->pages, + sb->dsts, + sb->dlens, + sb->comp_errors, + sb->nr_pages); + + /* + * Scan the sub-batch for any compression errors, + * and invalidate pages with errors, along with other + * pages belonging to the same folio as the error page(s). + * Set the folio's error status in "errors" so that no + * further zswap_batch_store() processing is done for + * the folio(s) with compression errors. + */ + zswap_batch_proc_comp_errors(sb, errors); + + zswap_batch_zpool_store(sb, errors); + + mutex_unlock(&acomp_ctx->mutex); +} + +static void zswap_batch_add_pages(struct zswap_batch_store_sub_batch *sb, + struct folio *folio, + u8 folio_id, + struct obj_cgroup *objcg, + struct zswap_entry *entries[], + long start_idx, + u8 nr) +{ + long index; + + for (index =3D start_idx; index < (start_idx + nr); ++index) { + u8 i =3D sb->nr_pages; + struct page *page =3D folio_page(folio, index); + sb->pages[i] =3D page; + sb->swpentries[i] =3D page_swap_entry(page); + sb->folio_ids[i] =3D folio_id; + sb->objcgs[i] =3D objcg; + sb->entries[i] =3D entries[index - start_idx]; + sb->comp_errors[i] =3D 0; + ++sb->nr_pages; + } +} + +/* Allocate entries for the next sub-batch. */ +static int zswap_batch_alloc_entries(struct zswap_entry *entries[], int no= de_id, u8 nr) +{ + u8 i; + + for (i =3D 0; i < nr; ++i) { + entries[i] =3D zswap_entry_cache_alloc(GFP_KERNEL, node_id); + if (!entries[i]) { + u8 j; + + zswap_reject_kmemcache_fail++; + for (j =3D 0; j < i; ++j) + zswap_entry_cache_free(entries[j]); + return -EINVAL; + } + + entries[i]->handle =3D (unsigned long)ERR_PTR(-EINVAL); + } + + return 0; +} + +static bool zswap_batch_comp_folio(struct folio *folio, int *errors, u8 fo= lio_id, + struct obj_cgroup *objcg, + struct zswap_batch_store_sub_batch *sub_batch, + bool last) +{ + long folio_start_idx =3D 0, nr_folio_pages =3D folio_nr_pages(folio); + struct zswap_entry *entries[SWAP_CRYPTO_BATCH_SIZE]; + int node_id =3D folio_nid(folio); + + /* + * Iterate over the pages in the folio passed in. Construct compress + * sub-batches of up to SWAP_CRYPTO_BATCH_SIZE pages. Process each + * sub-batch with IAA batch compression. Detect errors from batch + * compression and set the folio's error status. + */ + while (nr_folio_pages > 0) { + u8 add_nr_pages; + + /* + * If we have accumulated SWAP_CRYPTO_BATCH_SIZE + * pages, process the sub-batch. + */ + if (sub_batch->nr_pages =3D=3D SWAP_CRYPTO_BATCH_SIZE) { + zswap_batch_compress(sub_batch, errors); + zswap_batch_xarray_stats(sub_batch, errors); + zswap_batch_reset(sub_batch); + /* + * Stop processing this folio if it had compress errors. + */ + if (errors[folio_id]) + goto ret_folio; + } + + /* Add pages from the folio to the compress sub-batch. */ + add_nr_pages =3D min3(( + (long)SWAP_CRYPTO_BATCH_SIZE - + (long)sub_batch->nr_pages), + nr_folio_pages, + (long)SWAP_CRYPTO_BATCH_SIZE); + + /* + * Allocate zswap entries for this sub-batch. If we get errors + * while doing so, we can fail early and flag an error for the + * folio. + */ + if (zswap_batch_alloc_entries(entries, node_id, add_nr_pages)) { + zswap_batch_reset(sub_batch); + errors[folio_id] =3D -EINVAL; + goto ret_folio; + } + + zswap_batch_add_pages(sub_batch, folio, folio_id, objcg, + entries, folio_start_idx, add_nr_pages); + + nr_folio_pages -=3D add_nr_pages; + folio_start_idx +=3D add_nr_pages; + } /* this folio has pages to be compressed. */ + + /* + * Process last sub-batch: it could contain pages from multiple folios. + */ + if (last && sub_batch->nr_pages) { + zswap_batch_compress(sub_batch, errors); + zswap_batch_xarray_stats(sub_batch, errors); + } + +ret_folio: + return (!errors[folio_id]); +} + +/* + * Store a large folio and/or a batch of any-order folio(s) in zswap + * using IAA compress batching API. + * + * This the main procedure for batching within large folios and for batchi= ng + * of folios. Each large folio will be broken into sub-batches of + * SWAP_CRYPTO_BATCH_SIZE pages, the sub-batch pages will be compressed by + * IAA hardware compress engines in parallel, then stored in zpool/xarray. + * + * This procedure should only be called if zswap supports batching of stor= es. + * Otherwise, the sequential implementation for storing folios as in the + * current zswap_store() should be used. The code handles the unlikely eve= nt + * that the zswap pool changes from batching to non-batching between + * swap_writepage() and the start of zswap_batch_store(). + * + * The signature of this procedure is meant to allow the calling function, + * (for instance, swap_writepage()) to pass a batch of folios @batch + * (the "reclaim batch") to be stored in zswap. + * + * @batch and @errors have folio_batch_count(@batch) number of entries, + * with one-one correspondence (@errors[i] represents the error status of + * @batch->folios[i], for i in folio_batch_count(@batch)). Please also + * see comments preceding "struct zswap_batch_store_sub_batch" definition + * above. + * + * The calling function (for instance, swap_writepage()) should initialize + * @errors[i] to a non-0 value. + * If zswap successfully stores @batch->folios[i], it will set @errors[i] = to 0. + * If there is an error in zswap, it will set @errors[i] to -EINVAL. + * + * @batch: folio_batch of folios to be batch compressed. + * @errors: zswap_batch_store() error status for the folios in @batch. + */ +void zswap_batch_store(struct folio_batch *batch, int *errors) +{ + struct zswap_batch_store_sub_batch sub_batch; + struct zswap_pool *pool; + u8 i; + + /* + * If zswap is disabled, we must invalidate the possibly stale entry + * which was previously stored at this offset. Otherwise, writeback + * could overwrite the new data in the swapfile. + */ + if (!zswap_enabled) + goto check_old; + + pool =3D zswap_pool_current_get(); + + if (!pool) { + if (zswap_check_limits()) + queue_work(shrink_wq, &zswap_shrink_work); + goto check_old; + } + + if (!pool->can_batch) { + for (i =3D 0; i < folio_batch_count(batch); ++i) + if (zswap_store(batch->folios[i])) + errors[i] =3D 0; + else + errors[i] =3D -EINVAL; + /* + * Seems preferable to release the pool ref after the calls to + * zswap_store(), so that the non-batching pool cannot be + * deleted, can be used for sequential stores, and the zswap pool + * cannot morph into a batching pool. + */ + zswap_pool_put(pool); + return; + } + + zswap_batch_reset(&sub_batch); + sub_batch.pool =3D pool; + + for (i =3D 0; i < folio_batch_count(batch); ++i) { + struct folio *folio =3D batch->folios[i]; + struct obj_cgroup *objcg =3D NULL; + struct mem_cgroup *memcg =3D NULL; + bool ret; + + VM_WARN_ON_ONCE(!folio_test_locked(folio)); + VM_WARN_ON_ONCE(!folio_test_swapcache(folio)); + + objcg =3D get_obj_cgroup_from_folio(folio); + if (objcg && !obj_cgroup_may_zswap(objcg)) { + memcg =3D get_mem_cgroup_from_objcg(objcg); + if (shrink_memcg(memcg)) { + mem_cgroup_put(memcg); + goto put_objcg; + } + mem_cgroup_put(memcg); + } + + if (zswap_check_limits()) + goto put_objcg; + + if (objcg) { + memcg =3D get_mem_cgroup_from_objcg(objcg); + if (memcg_list_lru_alloc(memcg, &zswap_list_lru, GFP_KERNEL)) { + mem_cgroup_put(memcg); + goto put_objcg; + } + mem_cgroup_put(memcg); + } + + /* + * By default, set zswap error status in "errors" to "success" + * for use in swap_writepage() when this returns. In case of + * errors encountered in any sub-batch in which this folio's + * pages are batch-compressed, a negative error number will + * over-write this when zswap_batch_cleanup() is called. + */ + errors[i] =3D 0; + ret =3D zswap_batch_comp_folio(folio, errors, i, objcg, &sub_batch, + (i =3D=3D folio_batch_count(batch) - 1)); + +put_objcg: + obj_cgroup_put(objcg); + if (!ret && zswap_pool_reached_full) + queue_work(shrink_wq, &zswap_shrink_work); + } /* for batch folios */ + + zswap_pool_put(pool); + +check_old: + for (i =3D 0; i < folio_batch_count(batch); ++i) + if (errors[i]) + zswap_delete_stored_entries(batch->folios[i]); +} + int zswap_swapon(int type, unsigned long nr_pages) { struct xarray *trees, *tree; --=20 2.27.0