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Fri, 22 Nov 2024 21:45:03 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53dd24457e1sm740143e87.34.2024.11.22.21.45.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Nov 2024 21:45:02 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 23 Nov 2024 07:44:54 +0200 Subject: [PATCH v2 1/3] drm/msm/mdss: define bitfields for the UBWC_STATIC register Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241123-msm-mdss-ubwc-v2-1-41344bc6ef9c@linaro.org> References: <20241123-msm-mdss-ubwc-v2-0-41344bc6ef9c@linaro.org> In-Reply-To: <20241123-msm-mdss-ubwc-v2-0-41344bc6ef9c@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , Connor Abbott , David Airlie , Simona Vetter Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5924; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=Y68Ugbn4mNiWYoL63ZWT5oQDamfsA6evrZEL1K8NhkE=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnQWvax+ERF5jWnoJ2D5csc83mmx3JD2vw5Eoms uXY7FLT8QWJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ0Fr2gAKCRCLPIo+Aiko 1UZBB/45xpSd2K4g1tGqC0fO7jL9S+4VJS9xjljQccCOrTeJuqqpnlre/xgbYxLWh0uVQwgR5KC 2sTB8byJ384FGqyK4mwOxKEa3UP7jsQUYECX73tQrVyPPQS7Yj3s+dkJND+bU/h8/2REK+3+PFr DoJbdGpQ9jvHySdJW6oF5FF64pOx6kP2eiC2y+2k1iRHFkdHyTGVT1vlix/Wi2Hp6l34JPpfrq3 JXxOnreX/vtQYG053n+RPGI+anQ/Sf0llf0CsIMaYTVgjuhgcCBvp9SXdLbV2bOZ5NFxFEw+u5L SVj7ibE6LGutfSSRWWyv2lKtRr5Zn3++rKnpfCYb/gvtyexG X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Rather than hand-coding UBWC_STATIC value calculation, define corresponding bitfields and use them to setup the register value. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_mdss.c | 38 +++++++++++++++-------= ---- drivers/gpu/drm/msm/msm_mdss.h | 3 +- drivers/gpu/drm/msm/registers/display/mdss.xml | 11 +++++++- 3 files changed, 34 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index b7bd899ead44bf86998e7295bccb31a334fa6811..4b57f39bec4e6232a0f5b4d49f8= ae1200e74ac78 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -173,15 +173,17 @@ static void msm_mdss_setup_ubwc_dec_20(struct msm_mds= s *msm_mdss) static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss) { const struct msm_mdss_data *data =3D msm_mdss->mdss_data; - u32 value =3D (data->ubwc_swizzle & 0x1) | - (data->highest_bank_bit & 0x3) << 4 | - (data->macrotile_mode & 0x1) << 12; + u32 value =3D MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle & 0x1) | + MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); + + if (data->macrotile_mode) + value |=3D MDSS_UBWC_STATIC_MACROTILE_MODE; =20 if (data->ubwc_enc_version =3D=3D UBWC_3_0) - value |=3D BIT(10); + value |=3D MDSS_UBWC_STATIC_UBWC_AMSBC; =20 if (data->ubwc_enc_version =3D=3D UBWC_1_0) - value |=3D BIT(8); + value |=3D MDSS_UBWC_STATIC_UBWC_MIN_ACC_LEN; =20 writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); } @@ -189,10 +191,14 @@ static void msm_mdss_setup_ubwc_dec_30(struct msm_mds= s *msm_mdss) static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss) { const struct msm_mdss_data *data =3D msm_mdss->mdss_data; - u32 value =3D (data->ubwc_swizzle & 0x7) | - (data->ubwc_static & 0x1) << 3 | - (data->highest_bank_bit & 0x7) << 4 | - (data->macrotile_mode & 0x1) << 12; + u32 value =3D MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | + MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); + + if (data->ubwc_bank_spread) + value |=3D MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; + + if (data->macrotile_mode) + value |=3D MDSS_UBWC_STATIC_MACROTILE_MODE; =20 writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); =20 @@ -572,7 +578,7 @@ static const struct msm_mdss_data sa8775p_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_0, .ubwc_swizzle =3D 4, - .ubwc_static =3D 1, + .ubwc_bank_spread =3D true, .highest_bank_bit =3D 0, .macrotile_mode =3D 1, .reg_bus_bw =3D 74000, @@ -590,7 +596,7 @@ static const struct msm_mdss_data sc7280_data =3D { .ubwc_enc_version =3D UBWC_3_0, .ubwc_dec_version =3D UBWC_4_0, .ubwc_swizzle =3D 6, - .ubwc_static =3D 1, + .ubwc_bank_spread =3D true, .highest_bank_bit =3D 1, .macrotile_mode =3D 1, .reg_bus_bw =3D 74000, @@ -608,7 +614,7 @@ static const struct msm_mdss_data sc8280xp_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_0, .ubwc_swizzle =3D 6, - .ubwc_static =3D 1, + .ubwc_bank_spread =3D true, .highest_bank_bit =3D 3, .macrotile_mode =3D 1, .reg_bus_bw =3D 76800, @@ -671,7 +677,7 @@ static const struct msm_mdss_data sm8250_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_0, .ubwc_swizzle =3D 6, - .ubwc_static =3D 1, + .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ .highest_bank_bit =3D 3, .macrotile_mode =3D 1, @@ -682,7 +688,7 @@ static const struct msm_mdss_data sm8350_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_0, .ubwc_swizzle =3D 6, - .ubwc_static =3D 1, + .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ .highest_bank_bit =3D 3, .macrotile_mode =3D 1, @@ -693,7 +699,7 @@ static const struct msm_mdss_data sm8550_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_3, .ubwc_swizzle =3D 6, - .ubwc_static =3D 1, + .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ .highest_bank_bit =3D 3, .macrotile_mode =3D 1, @@ -704,7 +710,7 @@ static const struct msm_mdss_data x1e80100_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_3, .ubwc_swizzle =3D 6, - .ubwc_static =3D 1, + .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ .highest_bank_bit =3D 3, .macrotile_mode =3D 1, diff --git a/drivers/gpu/drm/msm/msm_mdss.h b/drivers/gpu/drm/msm/msm_mdss.h index 3afef4b1786d28902799333ff66c8b3ad0ab77fa..715e1426093de5a4f3b7d2b66b8= 89573c30b7b5c 100644 --- a/drivers/gpu/drm/msm/msm_mdss.h +++ b/drivers/gpu/drm/msm/msm_mdss.h @@ -13,7 +13,8 @@ struct msm_mdss_data { u32 ubwc_swizzle; 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Fri, 22 Nov 2024 21:45:05 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53dd24457e1sm740143e87.34.2024.11.22.21.45.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Nov 2024 21:45:04 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 23 Nov 2024 07:44:55 +0200 Subject: [PATCH v2 2/3] drm/msm/mdss: reuse defined bitfields for UBWC 2.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241123-msm-mdss-ubwc-v2-2-41344bc6ef9c@linaro.org> References: <20241123-msm-mdss-ubwc-v2-0-41344bc6ef9c@linaro.org> In-Reply-To: <20241123-msm-mdss-ubwc-v2-0-41344bc6ef9c@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , Connor Abbott , David Airlie , Simona Vetter Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_mdss.c | 17 +++++++++++++---- drivers/gpu/drm/msm/msm_mdss.h | 1 - 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 4b57f39bec4e6232a0f5b4d49f8ae1200e74ac78..2fdad0fa4bc159e9a10755da2c0= 402fd87734aee 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -166,8 +166,16 @@ static int _msm_mdss_irq_domain_add(struct msm_mdss *m= sm_mdss) static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss) { const struct msm_mdss_data *data =3D msm_mdss->mdss_data; + u32 value =3D MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | + MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); =20 - writel_relaxed(data->ubwc_static, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); + if (data->ubwc_bank_spread) + value |=3D MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; + + if (data->ubwc_enc_version =3D=3D UBWC_1_0) + value |=3D MDSS_UBWC_STATIC_UBWC_MIN_ACC_LEN; + + writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); } =20 static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss) @@ -587,7 +595,8 @@ static const struct msm_mdss_data sa8775p_data =3D { static const struct msm_mdss_data sc7180_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, - .ubwc_static =3D 0x1e, + .ubwc_swizzle =3D 6, + .ubwc_bank_spread =3D true, .highest_bank_bit =3D 0x1, .reg_bus_bw =3D 76800, }; @@ -638,7 +647,7 @@ static const struct msm_mdss_data sm6350_data =3D { .ubwc_enc_version =3D UBWC_2_0, .ubwc_dec_version =3D UBWC_2_0, .ubwc_swizzle =3D 6, - .ubwc_static =3D 0x1e, + .ubwc_bank_spread =3D true, .highest_bank_bit =3D 1, .reg_bus_bw =3D 76800, }; @@ -661,7 +670,7 @@ static const struct msm_mdss_data sm6115_data =3D { .ubwc_enc_version =3D UBWC_1_0, .ubwc_dec_version =3D UBWC_2_0, .ubwc_swizzle =3D 7, - .ubwc_static =3D 0x11f, + .ubwc_bank_spread =3D true, .highest_bank_bit =3D 0x1, .reg_bus_bw =3D 76800, }; diff --git a/drivers/gpu/drm/msm/msm_mdss.h b/drivers/gpu/drm/msm/msm_mdss.h index 715e1426093de5a4f3b7d2b66b889573c30b7b5c..14dc53704314558841ee1fe08d9= 3309fd2233812 100644 --- a/drivers/gpu/drm/msm/msm_mdss.h +++ b/drivers/gpu/drm/msm/msm_mdss.h @@ -11,7 +11,6 @@ struct msm_mdss_data { /* can be read from register 0x58 */ u32 ubwc_dec_version; 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Fri, 22 Nov 2024 21:45:07 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53dd24457e1sm740143e87.34.2024.11.22.21.45.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Nov 2024 21:45:07 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 23 Nov 2024 07:44:56 +0200 Subject: [PATCH v2 3/3] drm/msm/mdss: use boolean values for macrotile_mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241123-msm-mdss-ubwc-v2-3-41344bc6ef9c@linaro.org> References: <20241123-msm-mdss-ubwc-v2-0-41344bc6ef9c@linaro.org> In-Reply-To: <20241123-msm-mdss-ubwc-v2-0-41344bc6ef9c@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , Connor Abbott , David Airlie , Simona Vetter Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2536; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=gdM2PmIA7KXreNC4e0p5DKW62M8digF3+8KzLk+7N4s=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnQWvaGO+Y6FoVYTBQaZpzt8UIWJKd7OgPZXoQb 1CWB/ILgCCJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ0Fr2gAKCRCLPIo+Aiko 1aiHCACm2sH3vJTnYnx5BmVp1ztQ3EUYnPTFk6PpxdglQX8AeznE9hDRIEelD+LPW43iHWofTU6 pkI62suQqYHajFWAEqWMO18EwqVqy8xODNIIV0GBVjgYSpuWvZlSix4uU/5q/T/Kwi9ygdrhe2z sNdynfWUQE2Ey1w1uwdNpWI2v/n4ETEGp+y50kNNaroNRRgX0nJOy4Qt4zwdij2pr6Fg/QvqHi5 6DpG0F50H4ZDjhi8BmRCgHDpijcmR2jRVWR9JaGB2LlmjHrVbRK0IiWFItjDK72fIio18UrkFxZ Ek0kVpOmVc/k+s/ED6PQDFAFrTg+2vnXABrRLWw9SGP24yXx X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The macrotile_mode is a flag, not a bit value. Use true/false values to set it rather than 1/0. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/msm_mdss.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 2fdad0fa4bc159e9a10755da2c0402fd87734aee..2d9db179accb0fd8666fe80371e= a44a1fcc15e1f 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -588,7 +588,7 @@ static const struct msm_mdss_data sa8775p_data =3D { .ubwc_swizzle =3D 4, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 0, - .macrotile_mode =3D 1, + .macrotile_mode =3D true, .reg_bus_bw =3D 74000, }; =20 @@ -607,7 +607,7 @@ static const struct msm_mdss_data sc7280_data =3D { .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 1, - .macrotile_mode =3D 1, + .macrotile_mode =3D true, .reg_bus_bw =3D 74000, }; =20 @@ -615,7 +615,7 @@ static const struct msm_mdss_data sc8180x_data =3D { .ubwc_enc_version =3D UBWC_3_0, .ubwc_dec_version =3D UBWC_3_0, .highest_bank_bit =3D 3, - .macrotile_mode =3D 1, + .macrotile_mode =3D true, .reg_bus_bw =3D 76800, }; =20 @@ -625,7 +625,7 @@ static const struct msm_mdss_data sc8280xp_data =3D { .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 3, - .macrotile_mode =3D 1, + .macrotile_mode =3D true, .reg_bus_bw =3D 76800, }; =20 @@ -689,7 +689,7 @@ static const struct msm_mdss_data sm8250_data =3D { .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ .highest_bank_bit =3D 3, - .macrotile_mode =3D 1, + .macrotile_mode =3D true, .reg_bus_bw =3D 76800, }; =20 @@ -700,7 +700,7 @@ static const struct msm_mdss_data sm8350_data =3D { .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ .highest_bank_bit =3D 3, - .macrotile_mode =3D 1, + .macrotile_mode =3D true, .reg_bus_bw =3D 74000, }; =20 @@ -711,7 +711,7 @@ static const struct msm_mdss_data sm8550_data =3D { .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ .highest_bank_bit =3D 3, - .macrotile_mode =3D 1, + .macrotile_mode =3D true, .reg_bus_bw =3D 57000, }; =20 @@ -722,7 +722,7 @@ static const struct msm_mdss_data x1e80100_data =3D { .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ .highest_bank_bit =3D 3, - .macrotile_mode =3D 1, + .macrotile_mode =3D true, /* TODO: Add reg_bus_bw with real value */ }; =20 --=20 2.39.5