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Sat, 23 Nov 2024 08:52:35 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AN8qZ99002209 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 23 Nov 2024 08:52:35 GMT Received: from yijiyang-gv.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sat, 23 Nov 2024 00:52:31 -0800 From: Yijie Yang Date: Sat, 23 Nov 2024 16:51:53 +0800 Subject: [PATCH v4 1/2] arm64: dts: qcom: qcs8300: add the first 2.5G ethernet Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241123-dts_qcs8300-v4-1-b10b8ac634a9@quicinc.com> References: <20241123-dts_qcs8300-v4-0-b10b8ac634a9@quicinc.com> In-Reply-To: <20241123-dts_qcs8300-v4-0-b10b8ac634a9@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran CC: , , , , Yijie Yang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Add the internal SGMII/SerDes PHY node as well. Signed-off-by: Yijie Yang --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 43 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qc= om/qcs8300.dtsi index 2c35f96c3f289d5e2e57e0e30ef5e17cd1286188..718c2756400be884bd28a63c1ea= c5e8efe1c932d 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -772,6 +772,15 @@ lpass_ag_noc: interconnect@3c40000 { qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + serdes0: phy@8909000 { + compatible =3D "qcom,qcs8300-dwmac-sgmii-phy", "qcom,sa8775p-dwmac-sgmi= i-phy"; + reg =3D <0x0 0x8909000 0x0 0xe10>; + clocks =3D <&gcc GCC_SGMI_CLKREF_EN>; + clock-names =3D "sgmi_ref"; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + pmu@9091000 { compatible =3D "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; reg =3D <0x0 0x9091000 0x0 0x1000>; @@ -1308,6 +1317,40 @@ IPCC_MPROC_SIGNAL_GLINK_QMP }; }; =20 + ethernet0: ethernet@23040000 { + compatible =3D "qcom,qcs8300-ethqos", "qcom,sa8775p-ethqos"; + reg =3D <0x0 0x23040000 0x0 0x10000>, + <0x0 0x23056000 0x0 0x100>; + reg-names =3D "stmmaceth", "rgmii"; + + interrupts =3D , + ; + interrupt-names =3D "macirq", "sfty"; + + clocks =3D <&gcc GCC_EMAC0_AXI_CLK>, + <&gcc GCC_EMAC0_SLV_AHB_CLK>, + <&gcc GCC_EMAC0_PTP_CLK>, + <&gcc GCC_EMAC0_PHY_AUX_CLK>; + clock-names =3D "stmmaceth", + "pclk", + "ptp_ref", + "phyaux"; + power-domains =3D <&gcc GCC_EMAC0_GDSC>; + + phys =3D <&serdes0>; + phy-names =3D "serdes"; + + iommus =3D <&apps_smmu 0x120 0xf>; + dma-coherent; + + snps,tso; + snps,pbl =3D <32>; + rx-fifo-depth =3D <16384>; + tx-fifo-depth =3D <20480>; + + status =3D "disabled"; + }; + nspa_noc: interconnect@260c0000 { compatible =3D "qcom,qcs8300-nspa-noc"; reg =3D <0x0 0x260c0000 0x0 0x16080>; --=20 2.34.1