From nobody Sat Nov 23 18:33:22 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73C0D1632D5; Fri, 22 Nov 2024 06:46:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732257968; cv=none; b=YPIdBnbAE+NKGNvImNEuZUSa18nPFUwUnR3s3gl4IyOaPcrZNPGO4XlxS9uAA4vCREIn7CN/laGUQMm8VwfVgD8Iwa7W7ZzI16lpHJ2LV41Yj1tYtOxTGJO5Fq4FLWKfUfKYNfz9Mz7S6Q03lYIsAsTOLmoahGzR1927XhavICM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732257968; c=relaxed/simple; bh=tqwZVoQfJTWgCncELtIfAH9iuolvIFuLbX5HLziKDQ4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HyBc6iT4RkRqqT1YftVYZ1FQNDkSkE5jpXPUSyEzgHJ/1CsdYGm66EHqROCmosXi+FeeOHSiROkoTNGDiwrLV+UsGg3Mr8br7/HvNrcoqNro4V+EFsDO+03WL1y6EoWpyTffke4g7rGMH6IWKSXGi3vYbcf6ZuIjkcWgS1rKagI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=cSNiFMh3; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="cSNiFMh3" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4AM4ooej003258; Fri, 22 Nov 2024 06:45:40 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= k+rjlpTl4NWq4W6NIHYQ7VGNR0BZQknKSjnyAik8NdI=; b=cSNiFMh33vZYId6b 9cm83PdTD9xIcM2+lyYTlqkPjBNZ51CHeTW1DKkoazG6kooUfeq/HURDGDVMDg8D PlrH7Fl1j/xBWzTJBdG7KTH1ADEGSlhkfinr03yRVT7fu6zKMyZoRKMAEHWggkW3 AvZQy7ozMoAtpsAOdKpOeOzRWvZf2/DlJXDtdIHkar3LMiYpkVKX+FqLiwgSE2HI hzZkeVk0OTZHzWeg6FODmWuFpTYj//9asX1/iauXwf79SGQWUHxlIWm5MkHnGKBc Fhnp6R0FsUiNwSQOA43dGPQ0P6Z2J5I31fDmhnU/DV00eVJQee/1UWX9e6uPT5X7 c/sRJA== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4326csa640-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Nov 2024 06:45:39 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AM6jc7h031466 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Nov 2024 06:45:38 GMT Received: from liuxin-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 21 Nov 2024 22:45:32 -0800 From: Xin Liu To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Bjorn Andersson , Konrad Dybcio CC: Vinod Koul , Kishon Vijay Abraham I , Alim Akhtar , Avri Altman , Bart Van Assche , Andy Gross , , , , , , , , , Subject: [PATCH v3 2/3] arm64: dts: qcom: qcs615: add UFS node Date: Fri, 22 Nov 2024 14:44:27 +0800 Message-ID: <20241122064428.278752-3-quic_liuxin@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241122064428.278752-1-quic_liuxin@quicinc.com> References: <20241122064428.278752-1-quic_liuxin@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Qoz2J7EAY2l1M3-wh09jQ_c_OlWmrq5S X-Proofpoint-ORIG-GUID: Qoz2J7EAY2l1M3-wh09jQ_c_OlWmrq5S X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 malwarescore=0 phishscore=0 impostorscore=0 bulkscore=0 mlxlogscore=999 adultscore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411220054 Content-Type: text/plain; charset="utf-8" From: Sayali Lokhande Add the UFS Host Controller node and its PHY for QCS615 SoC. Signed-off-by: Sayali Lokhande Co-developed-by: Xin Liu Signed-off-by: Xin Liu --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 114 +++++++++++++++++++++++++++ 1 file changed, 114 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qco= m/qcs615.dtsi index 590beb37f441..5e501511e6db 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -458,6 +458,120 @@ mmss_noc: interconnect@1740000 { qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + ufs_mem_hc: ufshc@1d84000 { + compatible =3D "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; + reg =3D <0x0 0x01d84000 0x0 0x3000>, + <0x0 0x01d90000 0x0 0x8000>; + reg-names =3D "std", + "ice"; + + interrupts =3D ; + + clocks =3D <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; + clock-names =3D "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + + resets =3D <&gcc GCC_UFS_PHY_BCR>; + reset-names =3D "rst"; + + operating-points-v2 =3D <&ufs_opp_table>; + interconnects =3D <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "ufs-ddr", + "cpu-ufs"; + + power-domains =3D <&gcc UFS_PHY_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + iommus =3D <&apps_smmu 0x300 0x0>; + dma-coherent; + + lanes-per-direction =3D <1>; + + phys =3D <&ufs_mem_phy>; + phy-names =3D "ufsphy"; + + #reset-cells =3D <1>; + + status =3D "disabled"; + + ufs_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-50000000 { + opp-hz =3D /bits/ 64 <50000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <37500000>, + /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <75000000>, + /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <150000000>, + /bits/ 64 <300000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + ufs_mem_phy: phy@1d87000 { + compatible =3D "qcom,qcs615-qmp-ufs-phy", "qcom,sm6115-qmp-ufs-phy"; + reg =3D <0x0 0x01d87000 0x0 0xe00>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>; + clock-names =3D "ref", + "ref_aux", + "qref"; + + power-domains =3D <&gcc UFS_PHY_GDSC>; + + resets =3D <&ufs_mem_hc 0>; + reset-names =3D "ufsphy"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible =3D "qcom,tcsr-mutex"; reg =3D <0x0 0x01f40000 0x0 0x20000>; --=20 2.34.1