From nobody Tue Feb 10 10:18:45 2026 Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FF1015853D; Fri, 22 Nov 2024 06:20:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.255 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732256459; cv=none; b=ZMOTXR0cCdi97NBcGdrBwRr2rB0D23nCVLKAL8Ny278al9rsLbRPMh6LFjCx5n6R4+OLHUK+lWauDKjFO8aezQQtYUjwEaOkvrMz6FMj73u/YnBdm6hxjH64QIlFnLjwn2/pBmZPUYl4StjngidZgBF3grfF8xJjlRchrbStoGg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732256459; c=relaxed/simple; bh=TuWRusM6SJhP4LkvkK2EuhpbQ/CrQn2lGnTikUVBTro=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ov/mKvcyJ2NmuGbMn4tQuX6DYnEuSSko446JqnABkD3M/nPtWm6xMy+vn5jfOq9Qxfr8PqXiScW0MLjYLPnkFFVpa29l6851qkLiiJimlF7gWlHl58m7j/WuJOxj+dDJ5ckv/mZGSjgVfJZj+DBUs/ruEmrk3eUaS2EUd6AX84k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.255 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.194]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4XvlK06j40z1V4pg; Fri, 22 Nov 2024 14:18:12 +0800 (CST) Received: from kwepemh100008.china.huawei.com (unknown [7.202.181.93]) by mail.maildlp.com (Postfix) with ESMTPS id 88D251401F4; Fri, 22 Nov 2024 14:20:53 +0800 (CST) Received: from localhost.huawei.com (10.50.165.33) by kwepemh100008.china.huawei.com (7.202.181.93) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Fri, 22 Nov 2024 14:20:52 +0800 From: Lifeng Zheng To: , , , CC: , , , , , , , , , , Subject: [PATCH v2 1/3] ACPI: CPPC: Refactor register get and set ABIs Date: Fri, 22 Nov 2024 14:20:49 +0800 Message-ID: <20241122062051.3658577-2-zhenglifeng1@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20241122062051.3658577-1-zhenglifeng1@huawei.com> References: <20241122062051.3658577-1-zhenglifeng1@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To kwepemh100008.china.huawei.com (7.202.181.93) Content-Type: text/plain; charset="utf-8" Refactor register get and set ABIs using cppc_get_reg() and cppc_set_reg(). Rename cppc_get_perf() to cppc_get_reg() as a generic function to read cppc registers, with two changes: 1. Change the error kind to "no such device" when pcc_ss_id < 0, which means that this cpu cannot get a valid pcc_ss_id. 2. Add a check to verify if the register is a cpc supported one before using it. Add cppc_set_reg() as a generic function for setting cppc registers. Unlike other set reg ABIs, this function checks CPC_SUPPORTED right after getting the register, because the rest of the operations are meaningless if this register is not a cpc supported one. Signed-off-by: Lifeng Zheng --- drivers/acpi/cppc_acpi.c | 191 +++++++++++++++------------------------ 1 file changed, 72 insertions(+), 119 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index c1f3568d0c50..9aab22d8136a 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1179,10 +1179,13 @@ static int cpc_write(int cpu, struct cpc_register_r= esource *reg_res, u64 val) return ret_val; } =20 -static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf) +static int cppc_get_reg(int cpunum, enum cppc_regs reg_idx, u64 *val) { struct cpc_desc *cpc_desc =3D per_cpu(cpc_desc_ptr, cpunum); + struct cppc_pcc_data *pcc_ss_data =3D NULL; struct cpc_register_resource *reg; + int pcc_ss_id; + int ret =3D 0; =20 if (!cpc_desc) { pr_debug("No CPC descriptor for CPU:%d\n", cpunum); @@ -1191,20 +1194,23 @@ static int cppc_get_perf(int cpunum, enum cppc_regs= reg_idx, u64 *perf) =20 reg =3D &cpc_desc->cpc_regs[reg_idx]; =20 + if (!CPC_SUPPORTED(reg)) { + pr_debug("CPC register (reg_idx=3D%d) is not supported\n", reg_idx); + return -EOPNOTSUPP; + } + if (CPC_IN_PCC(reg)) { - int pcc_ss_id =3D per_cpu(cpu_pcc_subspace_idx, cpunum); - struct cppc_pcc_data *pcc_ss_data =3D NULL; - int ret =3D 0; + pcc_ss_id =3D per_cpu(cpu_pcc_subspace_idx, cpunum); =20 if (pcc_ss_id < 0) - return -EIO; + return -ENODEV; =20 pcc_ss_data =3D pcc_data[pcc_ss_id]; =20 down_write(&pcc_ss_data->pcc_lock); =20 if (send_pcc_cmd(pcc_ss_id, CMD_READ) >=3D 0) - cpc_read(cpunum, reg, perf); + cpc_read(cpunum, reg, val); else ret =3D -EIO; =20 @@ -1213,21 +1219,65 @@ static int cppc_get_perf(int cpunum, enum cppc_regs= reg_idx, u64 *perf) return ret; } =20 - cpc_read(cpunum, reg, perf); + cpc_read(cpunum, reg, val); =20 return 0; } =20 +static int cppc_set_reg(int cpu, enum cppc_regs reg_idx, u64 val) +{ + struct cpc_desc *cpc_desc =3D per_cpu(cpc_desc_ptr, cpu); + struct cppc_pcc_data *pcc_ss_data =3D NULL; + struct cpc_register_resource *reg; + int pcc_ss_id; + int ret; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU:%d\n", cpu); + return -ENODEV; + } + + reg =3D &cpc_desc->cpc_regs[reg_idx]; + + if (!CPC_SUPPORTED(reg)) { + pr_debug("CPC register (reg_idx=3D%d) is not supported\n", reg_idx); + return -EOPNOTSUPP; + } + + if (CPC_IN_PCC(reg)) { + pcc_ss_id =3D per_cpu(cpu_pcc_subspace_idx, cpu); + + if (pcc_ss_id < 0) { + pr_debug("Invalid pcc_ss_id\n"); + return -ENODEV; + } + + ret =3D cpc_write(cpu, reg, val); + if (ret) + return ret; + + pcc_ss_data =3D pcc_data[pcc_ss_id]; + + down_write(&pcc_ss_data->pcc_lock); + /* after writing CPC, transfer the ownership of PCC to platform */ + ret =3D send_pcc_cmd(pcc_ss_id, CMD_WRITE); + up_write(&pcc_ss_data->pcc_lock); + return ret; + } + + return cpc_write(cpu, reg, val); +} + /** * cppc_get_desired_perf - Get the desired performance register value. * @cpunum: CPU from which to get desired performance. * @desired_perf: Return address. * - * Return: 0 for success, -EIO otherwise. + * Return: 0 for success, -ERRNO otherwise. */ int cppc_get_desired_perf(int cpunum, u64 *desired_perf) { - return cppc_get_perf(cpunum, DESIRED_PERF, desired_perf); + return cppc_get_reg(cpunum, DESIRED_PERF, desired_perf); } EXPORT_SYMBOL_GPL(cppc_get_desired_perf); =20 @@ -1236,11 +1286,11 @@ EXPORT_SYMBOL_GPL(cppc_get_desired_perf); * @cpunum: CPU from which to get nominal performance. * @nominal_perf: Return address. * - * Return: 0 for success, -EIO otherwise. + * Return: 0 for success, -ERRNO otherwise. */ int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf) { - return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf); + return cppc_get_reg(cpunum, NOMINAL_PERF, nominal_perf); } =20 /** @@ -1248,11 +1298,11 @@ int cppc_get_nominal_perf(int cpunum, u64 *nominal_= perf) * @cpunum: CPU from which to get highest performance. * @highest_perf: Return address. * - * Return: 0 for success, -EIO otherwise. + * Return: 0 for success, -ERRNO otherwise. */ int cppc_get_highest_perf(int cpunum, u64 *highest_perf) { - return cppc_get_perf(cpunum, HIGHEST_PERF, highest_perf); + return cppc_get_reg(cpunum, HIGHEST_PERF, highest_perf); } EXPORT_SYMBOL_GPL(cppc_get_highest_perf); =20 @@ -1261,11 +1311,11 @@ EXPORT_SYMBOL_GPL(cppc_get_highest_perf); * @cpunum: CPU from which to get epp preference value. * @epp_perf: Return address. * - * Return: 0 for success, -EIO otherwise. + * Return: 0 for success, -ERRNO otherwise. */ int cppc_get_epp_perf(int cpunum, u64 *epp_perf) { - return cppc_get_perf(cpunum, ENERGY_PERF, epp_perf); + return cppc_get_reg(cpunum, ENERGY_PERF, epp_perf); } EXPORT_SYMBOL_GPL(cppc_get_epp_perf); =20 @@ -1545,44 +1595,14 @@ EXPORT_SYMBOL_GPL(cppc_set_epp_perf); */ int cppc_get_auto_sel_caps(int cpunum, struct cppc_perf_caps *perf_caps) { - struct cpc_desc *cpc_desc =3D per_cpu(cpc_desc_ptr, cpunum); - struct cpc_register_resource *auto_sel_reg; - u64 auto_sel; - - if (!cpc_desc) { - pr_debug("No CPC descriptor for CPU:%d\n", cpunum); - return -ENODEV; - } - - auto_sel_reg =3D &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; - - if (!CPC_SUPPORTED(auto_sel_reg)) - pr_warn_once("Autonomous mode is not unsupported!\n"); - - if (CPC_IN_PCC(auto_sel_reg)) { - int pcc_ss_id =3D per_cpu(cpu_pcc_subspace_idx, cpunum); - struct cppc_pcc_data *pcc_ss_data =3D NULL; - int ret =3D 0; - - if (pcc_ss_id < 0) - return -ENODEV; - - pcc_ss_data =3D pcc_data[pcc_ss_id]; - - down_write(&pcc_ss_data->pcc_lock); - - if (send_pcc_cmd(pcc_ss_id, CMD_READ) >=3D 0) { - cpc_read(cpunum, auto_sel_reg, &auto_sel); - perf_caps->auto_sel =3D (bool)auto_sel; - } else { - ret =3D -EIO; - } - - up_write(&pcc_ss_data->pcc_lock); + u64 auto_sel; + int ret; =20 + ret =3D cppc_get_reg(cpunum, AUTO_SEL_ENABLE, &auto_sel); + if (ret) return ret; - } =20 + perf_caps->auto_sel =3D (bool)auto_sel; return 0; } EXPORT_SYMBOL_GPL(cppc_get_auto_sel_caps); @@ -1594,43 +1614,7 @@ EXPORT_SYMBOL_GPL(cppc_get_auto_sel_caps); */ int cppc_set_auto_sel(int cpu, bool enable) { - int pcc_ss_id =3D per_cpu(cpu_pcc_subspace_idx, cpu); - struct cpc_register_resource *auto_sel_reg; - struct cpc_desc *cpc_desc =3D per_cpu(cpc_desc_ptr, cpu); - struct cppc_pcc_data *pcc_ss_data =3D NULL; - int ret =3D -EINVAL; - - if (!cpc_desc) { - pr_debug("No CPC descriptor for CPU:%d\n", cpu); - return -ENODEV; - } - - auto_sel_reg =3D &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; - - if (CPC_IN_PCC(auto_sel_reg)) { - if (pcc_ss_id < 0) { - pr_debug("Invalid pcc_ss_id\n"); - return -ENODEV; - } - - if (CPC_SUPPORTED(auto_sel_reg)) { - ret =3D cpc_write(cpu, auto_sel_reg, enable); - if (ret) - return ret; - } - - pcc_ss_data =3D pcc_data[pcc_ss_id]; - - down_write(&pcc_ss_data->pcc_lock); - /* after writing CPC, transfer the ownership of PCC to platform */ - ret =3D send_pcc_cmd(pcc_ss_id, CMD_WRITE); - up_write(&pcc_ss_data->pcc_lock); - } else { - ret =3D -ENOTSUPP; - pr_debug("_CPC in PCC is not supported\n"); - } - - return ret; + return cppc_set_reg(cpu, AUTO_SEL_ENABLE, enable); } EXPORT_SYMBOL_GPL(cppc_set_auto_sel); =20 @@ -1644,38 +1628,7 @@ EXPORT_SYMBOL_GPL(cppc_set_auto_sel); */ int cppc_set_enable(int cpu, bool enable) { - int pcc_ss_id =3D per_cpu(cpu_pcc_subspace_idx, cpu); - struct cpc_register_resource *enable_reg; - struct cpc_desc *cpc_desc =3D per_cpu(cpc_desc_ptr, cpu); - struct cppc_pcc_data *pcc_ss_data =3D NULL; - int ret =3D -EINVAL; - - if (!cpc_desc) { - pr_debug("No CPC descriptor for CPU:%d\n", cpu); - return -EINVAL; - } - - enable_reg =3D &cpc_desc->cpc_regs[ENABLE]; - - if (CPC_IN_PCC(enable_reg)) { - - if (pcc_ss_id < 0) - return -EIO; - - ret =3D cpc_write(cpu, enable_reg, enable); - if (ret) - return ret; - - pcc_ss_data =3D pcc_data[pcc_ss_id]; - - down_write(&pcc_ss_data->pcc_lock); - /* after writing CPC, transfer the ownership of PCC to platfrom */ - ret =3D send_pcc_cmd(pcc_ss_id, CMD_WRITE); - up_write(&pcc_ss_data->pcc_lock); - return ret; - } - - return cpc_write(cpu, enable_reg, enable); + return cppc_set_reg(cpu, ENABLE, enable); } EXPORT_SYMBOL_GPL(cppc_set_enable); =20 --=20 2.33.0