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charset="utf-8" From: Krishna chaitanya chundru Add dedicated schema for the PCIe controllers found on QCS615. Due to qcs615's clock-names do not match any of the existing dt-bindings, a new compatible for qcs615 is needed. Signed-off-by: Krishna chaitanya chundru Signed-off-by: Ziyue Zhang --- .../bindings/pci/qcom,pcie-qcs615.yaml | 161 ++++++++++++++++++ 1 file changed, 161 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-qcs615.= yaml diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-qcs615.yaml b/= Documentation/devicetree/bindings/pci/qcom,pcie-qcs615.yaml new file mode 100644 index 000000000000..8f7571538d23 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-qcs615.yaml @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-qcs615.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QCS615 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm QCS615 SoC (and compatible) PCIe root complex controller is bas= ed on + the Synopsys DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-qcs615 + + reg: + minItems: 6 + maxItems: 6 + + reg-names: + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 6 + maxItems: 6 + + clock-names: + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ref # REFERENCE clock + + interrupts: + minItems: 9 + maxItems: 9 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + - const: global + + resets: + minItems: 1 + maxItems: 1 + + reset-names: + items: + - const: pci # PCIe core reset + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@1c08000 { + compatible =3D "qcom,pcie-qcs615"; + reg =3D <0 0x01c08000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>, + <0 0x01c0b000 0 0x1000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config", "mhi"; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100= 000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x3d000= 00>; + + bus-range =3D <0x00 0xff>; + device_type =3D "pci"; + linux,pci-domain =3D <0>; + num-lanes =3D <1>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref"; + + dma-coherent; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7", "global"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH= >, /* int_a */ + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,= /* int_b */ + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,= /* int_c */ + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;= /* int_d */ + + interconnects =3D <&agree1_noc MASTER_PCIE 0 &mc_virt SLAVE_EB= I1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE= _PCIE_0 0>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + iommu-map =3D <0x0 &apps_smmu 0x400 0x1>, + <0x100 &apps_smmu 0x401 0x1>; + + phys =3D <&pcie_phy>; + phy-names =3D "pciephy"; + + pinctrl-0 =3D <&pcie_default_state>; + pinctrl-names =3D "default"; + + power-domains =3D <&gcc PCIE_0_GDSC>; + + resets =3D <&gcc GCC_PCIE_0_BCR>; + reset-names =3D "pci"; + + perst-gpios =3D <&tlmm 101 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 100 GPIO_ACTIVE_HIGH>; + }; + }; --=20 2.34.1