From nobody Sun Feb 8 09:32:30 2026 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4180E1D79B7 for ; Thu, 21 Nov 2024 18:53:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732215203; cv=none; b=LjNzwi0ya6caIzjHVQIR3BOAJ3iznROjYZNHfrk37JxkW23FaeRbfVqBQmKhBN4L3r9RTZgkANNPS0/WTCikymTaFDh1hgZSv0CTyhh3OI7QKaAwZflA/NmCmCqz8z6onVIY+q9Qtm/8S6KIUQ1c42wwbGSN9oT8G1h0T8jtasw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732215203; c=relaxed/simple; bh=eGhYnE5emXo94Pyg5quiuPFdiSkETv0T4xLbIt+gbbE=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=MtB2seGE0iiUxaFH6WJ2P/lXkx+pOW2Ap6cx8GBqmnO4try6BDPjf0kaFqOAcWdQcN3kJ+dw9iry/BGVoB4zA5ILnFhiY0iwDsRdsYvqHnjawdsK/Ipn/1pQv6QAjMshxNd0yKuzZ4WUOIroNwd66+WrnJjvjSI60tCD+GZAYms= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--mizhang.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=epBHLhlg; arc=none smtp.client-ip=209.85.128.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--mizhang.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="epBHLhlg" Received: by mail-yw1-f201.google.com with SMTP id 00721157ae682-6eec3cb4a81so23295097b3.1 for ; Thu, 21 Nov 2024 10:53:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1732215199; x=1732819999; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=T+9Madf5AUgYPaX6aUUL9JHycbWIRkK+aZqhIzgnbrs=; b=epBHLhlgmfnklftRQidJ2GmzQ+NWXPZW4UK+9IvFWJMBEz545B6BzS5+fs/HgOlrnx doncHJ6bH3mEZomG9hhOSpCDC+ZE+C3Mc/+aN+F+YxDoy56mOWkBuePVzTJzJM5Ze4H5 +6Qlc8xxQq9s4SlVnaaZZvNG1g3T5ZP7k8taUUxiWkBMEC/JdmAeMU6qyir8OpILwAQ9 TsYABene16OKHGimxZX0pZsTEPOdJScw+vldYYnQJ08ZAp3Lf0TvloFI6D7bEPIQLpbH EvppUyxtL6gq8rgZWbESl63tfumL8ia9OBvjtEVJCcM37Pqnj8w0BbokVSYVXEdXneHP 2y7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732215199; x=1732819999; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=T+9Madf5AUgYPaX6aUUL9JHycbWIRkK+aZqhIzgnbrs=; b=NLZQ/IDNxUM+Cq2JK9j7p9W1UHHriKx4B6dtuhRtgfF5+7+fMYyqKjSew3WkNBgRgh qMFDFaGoCp4WnFywsmPoXJGgBAmL934vsYawbjckd5Aq0iSrlaC9V6x01TykBvru29Rx 9OTXytZqvsIvHElFWfI5B1i+1YbVpsPedX+odZNxG7OMstfZBilIbSGTj1TN2Q+pUcwF J4r1oDByQ5/XrUO/dM5huqNggjkoTrN5NoFPm92YwTQAYq4j+YDYc2J8ThvfvSb6ntbQ fhSZw36BsHGHlwe1bNewLke2epLbmCb23O2F9qn3f1y8gxGRzf+ntTU2trT+OJppsop4 DzaQ== X-Forwarded-Encrypted: i=1; AJvYcCVusiNq16rmgMKycGORlQVxOnk7CeQ9TDWuLWVRbC8OTuw9GtZN2gqWvtJ87zVnFz3Zq+6A23b30WEMFf8=@vger.kernel.org X-Gm-Message-State: AOJu0Yyhc/8sduXBxMS9+mQabJjNgGbFlnWH36kelHce+tI5Mbol10x3 ua0vtwL0mc1eKM1paZeX1xdDPFk278BOJMC9E0AXz8Vyh8B9rHMXk3w8ySKwygfb6NmYYRtH5yr HTqf4bA== X-Google-Smtp-Source: AGHT+IFW1c+yo5NB9i6gITZMQ/WYNQr1/fXSlza8bauLrwlg/McJYGaXVTMf7a6D63EaXjw6XMTTYqlKnd3N X-Received: from mizhang-super.c.googlers.com ([34.105.13.176]) (user=mizhang job=sendgmr) by 2002:a25:ab92:0:b0:e30:d5cf:775a with SMTP id 3f1490d57ef6-e38f74af44emr892276.6.1732215199276; Thu, 21 Nov 2024 10:53:19 -0800 (PST) Reply-To: Mingwei Zhang Date: Thu, 21 Nov 2024 18:52:53 +0000 In-Reply-To: <20241121185315.3416855-1-mizhang@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241121185315.3416855-1-mizhang@google.com> X-Mailer: git-send-email 2.47.0.371.ga323438b13-goog Message-ID: <20241121185315.3416855-2-mizhang@google.com> Subject: [RFC PATCH 01/22] x86/aperfmperf: Introduce get_host_[am]perf() From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Huang Rui , "Gautham R. Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jim Mattson In preparation for KVM pass-through of IA32_APERF and IA32_MPERF, introduce wrappers that read these MSRs. Going forward, all kernel code that needs host APERF/MPERF values should use these wrappers instead of rdmsrl(). While these functions currently just read the MSRs directly, future patches will enhance them to handle cases where the MSRs contain guest values. Moving all host APERF/MPERF reads to use these functions now will make it easier to add this functionality later. No functional change intended. Signed-off-by: Jim Mattson Reviewed-by: Mingwei Zhang Signed-off-by: Mingwei Zhang --- arch/x86/include/asm/topology.h | 3 +++ arch/x86/kernel/cpu/aperfmperf.c | 22 ++++++++++++++++++---- drivers/cpufreq/amd-pstate.c | 4 ++-- drivers/cpufreq/intel_pstate.c | 5 +++-- 4 files changed, 26 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topolog= y.h index 92f3664dd933b..2ef9903cf85d7 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -302,6 +302,9 @@ static inline void arch_set_max_freq_ratio(bool turbo_d= isabled) { } static inline void freq_invariance_set_perf_ratio(u64 ratio, bool turbo_di= sabled) { } #endif =20 +extern u64 get_host_aperf(void); +extern u64 get_host_mperf(void); + extern void arch_scale_freq_tick(void); #define arch_scale_freq_tick arch_scale_freq_tick =20 diff --git a/arch/x86/kernel/cpu/aperfmperf.c b/arch/x86/kernel/cpu/aperfmp= erf.c index f642de2ebdac8..3be5070ba3361 100644 --- a/arch/x86/kernel/cpu/aperfmperf.c +++ b/arch/x86/kernel/cpu/aperfmperf.c @@ -40,8 +40,8 @@ static void init_counter_refs(void) { u64 aperf, mperf; =20 - rdmsrl(MSR_IA32_APERF, aperf); - rdmsrl(MSR_IA32_MPERF, mperf); + aperf =3D get_host_aperf(); + mperf =3D get_host_mperf(); =20 this_cpu_write(cpu_samples.aperf, aperf); this_cpu_write(cpu_samples.mperf, mperf); @@ -94,6 +94,20 @@ void arch_set_max_freq_ratio(bool turbo_disabled) } EXPORT_SYMBOL_GPL(arch_set_max_freq_ratio); =20 +u64 get_host_aperf(void) +{ + WARN_ON_ONCE(!irqs_disabled()); + return native_read_msr(MSR_IA32_APERF); +} +EXPORT_SYMBOL_GPL(get_host_aperf); + +u64 get_host_mperf(void) +{ + WARN_ON_ONCE(!irqs_disabled()); + return native_read_msr(MSR_IA32_MPERF); +} +EXPORT_SYMBOL_GPL(get_host_mperf); + static bool __init turbo_disabled(void) { u64 misc_en; @@ -474,8 +488,8 @@ void arch_scale_freq_tick(void) if (!cpu_feature_enabled(X86_FEATURE_APERFMPERF)) return; =20 - rdmsrl(MSR_IA32_APERF, aperf); - rdmsrl(MSR_IA32_MPERF, mperf); + aperf =3D get_host_aperf(); + mperf =3D get_host_mperf(); acnt =3D aperf - s->aperf; mcnt =3D mperf - s->mperf; =20 diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index b63863f77c677..c26092284be56 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -446,8 +446,8 @@ static inline bool amd_pstate_sample(struct amd_cpudata= *cpudata) unsigned long flags; =20 local_irq_save(flags); - rdmsrl(MSR_IA32_APERF, aperf); - rdmsrl(MSR_IA32_MPERF, mperf); + aperf =3D get_host_aperf(); + mperf =3D get_host_mperf(); tsc =3D rdtsc(); =20 if (cpudata->prev.mperf =3D=3D mperf || cpudata->prev.tsc =3D=3D tsc) { diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c index 400337f3b572d..993a66095547f 100644 --- a/drivers/cpufreq/intel_pstate.c +++ b/drivers/cpufreq/intel_pstate.c @@ -27,6 +27,7 @@ #include #include #include +#include #include =20 #include @@ -2423,8 +2424,8 @@ static inline bool intel_pstate_sample(struct cpudata= *cpu, u64 time) u64 tsc; =20 local_irq_save(flags); - rdmsrl(MSR_IA32_APERF, aperf); - rdmsrl(MSR_IA32_MPERF, mperf); + aperf =3D get_host_aperf(); + mperf =3D get_host_mperf(); tsc =3D rdtsc(); if (cpu->prev_mperf =3D=3D mperf || cpu->prev_tsc =3D=3D tsc) { local_irq_restore(flags); --=20 2.47.0.371.ga323438b13-goog From nobody Sun Feb 8 09:32:30 2026 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B72B81DE3D4 for ; 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Thu, 21 Nov 2024 10:53:20 -0800 (PST) Reply-To: Mingwei Zhang Date: Thu, 21 Nov 2024 18:52:54 +0000 In-Reply-To: <20241121185315.3416855-1-mizhang@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241121185315.3416855-1-mizhang@google.com> X-Mailer: git-send-email 2.47.0.371.ga323438b13-goog Message-ID: <20241121185315.3416855-3-mizhang@google.com> Subject: [RFC PATCH 02/22] x86/aperfmperf: Introduce set_guest_[am]perf() From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Huang Rui , "Gautham R. Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jim Mattson KVM guests need access to IA32_APERF and IA32_MPERF to observe their effective CPU frequency, but intercepting reads of these MSRs is too expensive since Linux guests read them every scheduler tick (250 Hz by default). Allow the guest to read these MSRs without interception by loading guest values into the hardware MSRs. When loading a guest value into IA32_APERF or IA32_MPERF: 1. Query the current host value 2. Record the offset between guest and host values in a per-CPU variable 3. Load the guest value into the MSR Modify get_host_[am]perf() to add the per-CPU offset to the raw MSR value, so that host kernel code can still obtain correct host values even when the MSRs contain guest values. Signed-off-by: Jim Mattson Reviewed-by: Mingwei Zhang Signed-off-by: Mingwei Zhang --- arch/x86/include/asm/topology.h | 5 +++++ arch/x86/kernel/cpu/aperfmperf.c | 31 +++++++++++++++++++++++++++++-- 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topolog= y.h index 2ef9903cf85d7..fef5846c01976 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -302,8 +302,13 @@ static inline void arch_set_max_freq_ratio(bool turbo_= disabled) { } static inline void freq_invariance_set_perf_ratio(u64 ratio, bool turbo_di= sabled) { } #endif =20 +DECLARE_PER_CPU(u64, host_aperf_offset); +DECLARE_PER_CPU(u64, host_mperf_offset); + extern u64 get_host_aperf(void); extern u64 get_host_mperf(void); +extern void set_guest_aperf(u64 aperf); +extern void set_guest_mperf(u64 mperf); =20 extern void arch_scale_freq_tick(void); #define arch_scale_freq_tick arch_scale_freq_tick diff --git a/arch/x86/kernel/cpu/aperfmperf.c b/arch/x86/kernel/cpu/aperfmp= erf.c index 3be5070ba3361..8b66872aa98c1 100644 --- a/arch/x86/kernel/cpu/aperfmperf.c +++ b/arch/x86/kernel/cpu/aperfmperf.c @@ -94,20 +94,47 @@ void arch_set_max_freq_ratio(bool turbo_disabled) } EXPORT_SYMBOL_GPL(arch_set_max_freq_ratio); =20 +DEFINE_PER_CPU(u64, host_aperf_offset); +DEFINE_PER_CPU(u64, host_mperf_offset); + u64 get_host_aperf(void) { WARN_ON_ONCE(!irqs_disabled()); - return native_read_msr(MSR_IA32_APERF); + return native_read_msr(MSR_IA32_APERF) + + this_cpu_read(host_aperf_offset); } EXPORT_SYMBOL_GPL(get_host_aperf); =20 u64 get_host_mperf(void) { WARN_ON_ONCE(!irqs_disabled()); - return native_read_msr(MSR_IA32_MPERF); + return native_read_msr(MSR_IA32_MPERF) + + this_cpu_read(host_mperf_offset); } EXPORT_SYMBOL_GPL(get_host_mperf); =20 +void set_guest_aperf(u64 guest_aperf) +{ + u64 host_aperf; + + WARN_ON_ONCE(!irqs_disabled()); + host_aperf =3D get_host_aperf(); + wrmsrl(MSR_IA32_APERF, guest_aperf); + this_cpu_write(host_aperf_offset, host_aperf - guest_aperf); +} +EXPORT_SYMBOL_GPL(set_guest_aperf); + +void set_guest_mperf(u64 guest_mperf) +{ + u64 host_mperf; + + WARN_ON_ONCE(!irqs_disabled()); + host_mperf =3D get_host_mperf(); + wrmsrl(MSR_IA32_MPERF, guest_mperf); + this_cpu_write(host_mperf_offset, host_mperf - guest_mperf); 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Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jim Mattson Round out the {host,guest}[am]perf APIs by adding functions to restore host values to the hardware MSRs. These functions: 1. Write the current host value (obtained via get_host_[am]perf()) to the corresponding MSR 2. Clear the per-CPU offset used to track the difference between guest and host values Signed-off-by: Jim Mattson --- arch/x86/include/asm/topology.h | 2 ++ arch/x86/kernel/cpu/aperfmperf.c | 16 ++++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topolog= y.h index fef5846c01976..8d4d4cd41bd84 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -309,6 +309,8 @@ extern u64 get_host_aperf(void); extern u64 get_host_mperf(void); extern void set_guest_aperf(u64 aperf); extern void set_guest_mperf(u64 mperf); +extern void restore_host_aperf(void); +extern void restore_host_mperf(void); =20 extern void arch_scale_freq_tick(void); #define arch_scale_freq_tick arch_scale_freq_tick diff --git a/arch/x86/kernel/cpu/aperfmperf.c b/arch/x86/kernel/cpu/aperfmp= erf.c index 8b66872aa98c1..4d6c0b8b39452 100644 --- a/arch/x86/kernel/cpu/aperfmperf.c +++ b/arch/x86/kernel/cpu/aperfmperf.c @@ -135,6 +135,22 @@ void set_guest_mperf(u64 guest_mperf) } EXPORT_SYMBOL_GPL(set_guest_mperf); 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Thu, 21 Nov 2024 10:53:24 -0800 (PST) Reply-To: Mingwei Zhang Date: Thu, 21 Nov 2024 18:52:56 +0000 In-Reply-To: <20241121185315.3416855-1-mizhang@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241121185315.3416855-1-mizhang@google.com> X-Mailer: git-send-email 2.47.0.371.ga323438b13-goog Message-ID: <20241121185315.3416855-5-mizhang@google.com> Subject: [RFC PATCH 04/22] x86/msr: Adjust remote reads of IA32_[AM]PERF by the per-cpu host offset From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Huang Rui , "Gautham R. Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jim Mattson When reading IA32_APERF or IA32_MPERF remotely via /dev/cpu/*/msr, account for any offset between the hardware MSR value and the true host value. This ensures tools like turbostat get correct host values even when the hardware MSRs contain guest values. Signed-off-by: Jim Mattson Reviewed-by: Mingwei Zhang Signed-off-by: Mingwei Zhang --- arch/x86/lib/msr-smp.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/x86/lib/msr-smp.c b/arch/x86/lib/msr-smp.c index acd463d887e1c..43c5d21e840fb 100644 --- a/arch/x86/lib/msr-smp.c +++ b/arch/x86/lib/msr-smp.c @@ -4,6 +4,15 @@ #include #include #include +#include + +static void adjust_host_aperfmperf(u32 msr_no, struct msr *reg) +{ + if (msr_no =3D=3D MSR_IA32_APERF) + reg->q +=3D this_cpu_read(host_aperf_offset); + else if (msr_no =3D=3D MSR_IA32_MPERF) + reg->q +=3D this_cpu_read(host_mperf_offset); +} =20 static void __rdmsr_on_cpu(void *info) { @@ -16,6 +25,7 @@ static void __rdmsr_on_cpu(void *info) reg =3D &rv->reg; =20 rdmsr(rv->msr_no, reg->l, reg->h); + adjust_host_aperfmperf(rv->msr_no, reg); } =20 static void __wrmsr_on_cpu(void *info) @@ -154,6 +164,7 @@ static void __rdmsr_safe_on_cpu(void *info) struct msr_info_completion *rv =3D info; =20 rv->msr.err =3D rdmsr_safe(rv->msr.msr_no, &rv->msr.reg.l, &rv->msr.reg.h= ); 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Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jim Mattson Factor out common code that handles the transition from HALTED/AP_RESET_HOLD to RUNNABLE state. In addition to changing mp_state, this transition has side effects (clearing pv_unhalted, apf.halted) which must be handled consistently across all code paths. As future patches add more side effects to this state transition, this helper ensures they will be applied uniformly at all transition points. No functional change intended. Signed-off-by: Jim Mattson Reviewed-by: Mingwei Zhang Signed-off-by: Mingwei Zhang --- arch/x86/include/asm/kvm_host.h | 2 ++ arch/x86/kvm/x86.c | 16 +++++++++++----- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index 6d9f763a7bb9d..04ef56d10cbb1 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -2283,6 +2283,8 @@ static inline bool kvm_is_supported_user_return_msr(u= 32 msr) return kvm_find_user_return_msr(msr) >=3D 0; } =20 +void kvm_vcpu_make_runnable(struct kvm_vcpu *vcpu); + u64 kvm_scale_tsc(u64 tsc, u64 ratio); u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc); u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multip= lier); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 83fe0a78146fc..3c6b0ca91e5f5 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -11167,6 +11167,16 @@ int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); } =20 +void kvm_vcpu_make_runnable(struct kvm_vcpu *vcpu) +{ + if (vcpu->arch.mp_state =3D=3D KVM_MP_STATE_HALTED || + vcpu->arch.mp_state =3D=3D KVM_MP_STATE_AP_RESET_HOLD) + vcpu->arch.pv.pv_unhalted =3D false; + vcpu->arch.mp_state =3D KVM_MP_STATE_RUNNABLE; + vcpu->arch.apf.halted =3D false; +} +EXPORT_SYMBOL_GPL(kvm_vcpu_make_runnable); + /* Called within kvm->srcu read side. */ static inline int vcpu_block(struct kvm_vcpu *vcpu) { @@ -11222,12 +11232,8 @@ static inline int vcpu_block(struct kvm_vcpu *vcpu) switch(vcpu->arch.mp_state) { case KVM_MP_STATE_HALTED: case KVM_MP_STATE_AP_RESET_HOLD: - vcpu->arch.pv.pv_unhalted =3D false; - vcpu->arch.mp_state =3D - KVM_MP_STATE_RUNNABLE; - fallthrough; case KVM_MP_STATE_RUNNABLE: - vcpu->arch.apf.halted =3D false; + kvm_vcpu_make_runnable(vcpu); break; case KVM_MP_STATE_INIT_RECEIVED: break; --=20 2.47.0.371.ga323438b13-goog From nobody Sun Feb 8 09:32:30 2026 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1924E1DF26F for ; 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Thu, 21 Nov 2024 10:53:28 -0800 (PST) Reply-To: Mingwei Zhang Date: Thu, 21 Nov 2024 18:52:58 +0000 In-Reply-To: <20241121185315.3416855-1-mizhang@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241121185315.3416855-1-mizhang@google.com> X-Mailer: git-send-email 2.47.0.371.ga323438b13-goog Message-ID: <20241121185315.3416855-7-mizhang@google.com> Subject: [RFC PATCH 06/22] KVM: x86: INIT may transition from HALTED to RUNNABLE From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Huang Rui , "Gautham R. Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jim Mattson When a halted vCPU is awakened by an INIT signal, it might have been the target of a previous KVM_HC_KICK_CPU hypercall, in which case pv_unhalted would be set. This flag should be cleared before the next HLT instruction, as kvm_vcpu_has_events() would otherwise return true and prevent the vCPU from entering the halt state. Use kvm_vcpu_make_runnable() to ensure consistent handling of the HALTED to RUNNABLE state transition. Fixes: 6aef266c6e17 ("kvm hypervisor : Add a hypercall to KVM hypervisor to= support pv-ticketlocks") Signed-off-by: Jim Mattson --- arch/x86/kvm/lapic.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 95c6beb8ce279..97aa634505306 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -3372,9 +3372,8 @@ int kvm_apic_accept_events(struct kvm_vcpu *vcpu) =20 if (test_and_clear_bit(KVM_APIC_INIT, &apic->pending_events)) { kvm_vcpu_reset(vcpu, true); - if (kvm_vcpu_is_bsp(apic->vcpu)) - vcpu->arch.mp_state =3D KVM_MP_STATE_RUNNABLE; - else + kvm_vcpu_make_runnable(vcpu); + if (!kvm_vcpu_is_bsp(apic->vcpu)) vcpu->arch.mp_state =3D KVM_MP_STATE_INIT_RECEIVED; } if (test_and_clear_bit(KVM_APIC_SIPI, &apic->pending_events)) { --=20 2.47.0.371.ga323438b13-goog From nobody Sun Feb 8 09:32:30 2026 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 729A91DF742 for ; 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Thu, 21 Nov 2024 10:53:29 -0800 (PST) Reply-To: Mingwei Zhang Date: Thu, 21 Nov 2024 18:52:59 +0000 In-Reply-To: <20241121185315.3416855-1-mizhang@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241121185315.3416855-1-mizhang@google.com> X-Mailer: git-send-email 2.47.0.371.ga323438b13-goog Message-ID: <20241121185315.3416855-8-mizhang@google.com> Subject: [RFC PATCH 07/22] KVM: nSVM: Nested #VMEXIT may transition from HALTED to RUNNABLE From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Huang Rui , "Gautham R. Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jim Mattson When a halted vCPU is awakened by a nested event, it might have been the target of a previous KVM_HC_KICK_CPU hypercall, in which case pv_unhalted would be set. This flag should be cleared before the next HLT instruction, as kvm_vcpu_has_events() would otherwise return true and prevent the vCPU from entering the halt state. Use kvm_vcpu_make_runnable() to ensure consistent handling of the HALTED to RUNNABLE state transition. Fixes: 38c0b192bd6d ("KVM: SVM: leave halted state on vmexit") Signed-off-by: Jim Mattson --- arch/x86/kvm/svm/nested.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/nested.c b/arch/x86/kvm/svm/nested.c index cf84103ce38b9..49e6cdfeac4da 100644 --- a/arch/x86/kvm/svm/nested.c +++ b/arch/x86/kvm/svm/nested.c @@ -994,7 +994,7 @@ int nested_svm_vmexit(struct vcpu_svm *svm) kvm_clear_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu); =20 /* in case we halted in L2 */ - svm->vcpu.arch.mp_state =3D KVM_MP_STATE_RUNNABLE; + kvm_vcpu_make_runnable(vcpu); =20 /* Give the current vmcb to the guest */ =20 --=20 2.47.0.371.ga323438b13-goog From nobody Sun Feb 8 09:32:30 2026 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 618831DF99F for ; Thu, 21 Nov 2024 18:53:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 21 Nov 2024 10:53:31 -0800 (PST) Reply-To: Mingwei Zhang Date: Thu, 21 Nov 2024 18:53:00 +0000 In-Reply-To: <20241121185315.3416855-1-mizhang@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241121185315.3416855-1-mizhang@google.com> X-Mailer: git-send-email 2.47.0.371.ga323438b13-goog Message-ID: <20241121185315.3416855-9-mizhang@google.com> Subject: [RFC PATCH 08/22] KVM: nVMX: Nested VM-exit may transition from HALTED to RUNNABLE From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Huang Rui , "Gautham R. Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jim Mattson When a halted vCPU is awakened by a nested event, it might have been the target of a previous KVM_HC_KICK_CPU hypercall, in which case pv_unhalted would be set. This flag should be cleared before the next HLT instruction, as kvm_vcpu_has_events() would otherwise return true and prevent the vCPU from entering the halt state. Use kvm_vcpu_make_runnable() to ensure consistent handling of the HALTED to RUNNABLE state transition. Fixes: b6b8a1451fc4 ("KVM: nVMX: Rework interception of IRQs and NMIs") Signed-off-by: Jim Mattson --- arch/x86/kvm/vmx/nested.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index 931a7361c30f2..202eacfd87036 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -5048,7 +5048,7 @@ void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 vm_= exit_reason, vmx->nested.need_vmcs12_to_shadow_sync =3D true; =20 /* in case we halted in L2 */ - vcpu->arch.mp_state =3D KVM_MP_STATE_RUNNABLE; + kvm_vcpu_make_runnable(vcpu); =20 if (likely(!vmx->fail)) { if (vm_exit_reason !=3D -1) --=20 2.47.0.371.ga323438b13-goog From nobody Sun Feb 8 09:32:30 2026 Received: from mail-pf1-f202.google.com (mail-pf1-f202.google.com [209.85.210.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8FAA61DFDB3 for ; Thu, 21 Nov 2024 18:53:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 21 Nov 2024 10:53:32 -0800 (PST) Reply-To: Mingwei Zhang Date: Thu, 21 Nov 2024 18:53:01 +0000 In-Reply-To: <20241121185315.3416855-1-mizhang@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241121185315.3416855-1-mizhang@google.com> X-Mailer: git-send-email 2.47.0.371.ga323438b13-goog Message-ID: <20241121185315.3416855-10-mizhang@google.com> Subject: [RFC PATCH 09/22] KVM: x86: Introduce KVM_X86_FEATURE_APERFMPERF From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Huang Rui , "Gautham R. Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The APERFMPERF feature bit appears in CPUID.6H:ECX[0], but is exposed to Linux via X86_FEATURE_APERFMPERF in a Linux-defined feature word. To enable KVM's reverse CPUID functionality for this feature, define a KVM feature word matching the hardware CPUID leaf that contains the APERFMPERF bit. This patch only adds the feature definition - enabling and advertising the feature to guests will be handled in later patches. Signed-off-by: Mingwei Zhang Co-developed-by: Jim Mattson Signed-off-by: Jim Mattson --- arch/x86/kvm/reverse_cpuid.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h index 0d17d6b706396..d12e5d9ab2251 100644 --- a/arch/x86/kvm/reverse_cpuid.h +++ b/arch/x86/kvm/reverse_cpuid.h @@ -18,6 +18,7 @@ enum kvm_only_cpuid_leafs { CPUID_8000_0022_EAX, CPUID_7_2_EDX, CPUID_24_0_EBX, + CPUID_6_ECX, NR_KVM_CPU_CAPS, =20 NKVMCAPINTS =3D NR_KVM_CPU_CAPS - NCAPINTS, @@ -42,6 +43,9 @@ enum kvm_only_cpuid_leafs { #define KVM_X86_FEATURE_SGX2 KVM_X86_FEATURE(CPUID_12_EAX, 1) #define KVM_X86_FEATURE_SGX_EDECCSSA KVM_X86_FEATURE(CPUID_12_EAX, 11) =20 +/* Intel-defined sub-features, CPUID level 0x00000006 (ECX) */ +#define KVM_X86_FEATURE_APERFMPERF KVM_X86_FEATURE(CPUID_6_ECX, 0) + /* Intel-defined sub-features, CPUID level 0x00000007:1 (EDX) */ #define X86_FEATURE_AVX_VNNI_INT8 KVM_X86_FEATURE(CPUID_7_1_EDX, 4) #define X86_FEATURE_AVX_NE_CONVERT KVM_X86_FEATURE(CPUID_7_1_EDX, 5) @@ -98,6 +102,7 @@ static const struct cpuid_reg reverse_cpuid[] =3D { [CPUID_8000_0022_EAX] =3D {0x80000022, 0, CPUID_EAX}, [CPUID_7_2_EDX] =3D { 7, 2, CPUID_EDX}, [CPUID_24_0_EBX] =3D { 0x24, 0, CPUID_EBX}, + [CPUID_6_ECX] =3D { 6, 0, CPUID_ECX}, }; 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Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jim Mattson KVM must verify both host support and guest CPUID enumeration before enabling guest access to APERFMPERF. This verification is deferred until the implementation of guest APERFMPERF is complete. This declaration enables "guest_can_use(vcpu, X86_FEATURE_APERFMPERF)". Otherwise, that expression results in a compile-time error. Signed-off-by: Jim Mattson Reviewed-by: Mingwei Zhang Signed-off-by: Mingwei Zhang --- arch/x86/kvm/governed_features.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/kvm/governed_features.h b/arch/x86/kvm/governed_featu= res.h index ad463b1ed4e4a..fa77d655d2355 100644 --- a/arch/x86/kvm/governed_features.h +++ b/arch/x86/kvm/governed_features.h @@ -17,6 +17,7 @@ KVM_GOVERNED_X86_FEATURE(PFTHRESHOLD) KVM_GOVERNED_X86_FEATURE(VGIF) KVM_GOVERNED_X86_FEATURE(VNMI) KVM_GOVERNED_X86_FEATURE(LAM) +KVM_GOVERNED_X86_FEATURE(APERFMPERF) =20 #undef KVM_GOVERNED_X86_FEATURE #undef KVM_GOVERNED_FEATURE --=20 2.47.0.371.ga323438b13-goog From nobody Sun Feb 8 09:32:30 2026 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 863CA1E04AC for ; Thu, 21 Nov 2024 18:53:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 21 Nov 2024 10:53:36 -0800 (PST) Reply-To: Mingwei Zhang Date: Thu, 21 Nov 2024 18:53:03 +0000 In-Reply-To: <20241121185315.3416855-1-mizhang@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241121185315.3416855-1-mizhang@google.com> X-Mailer: git-send-email 2.47.0.371.ga323438b13-goog Message-ID: <20241121185315.3416855-12-mizhang@google.com> Subject: [RFC PATCH 11/22] KVM: x86: Initialize guest [am]perf at vcpu power-on From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Huang Rui , "Gautham R. Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jim Mattson The guest's IA32_APERF and IA32_MPERF MSRs start at zero. However, IA32_MPERF should be incremented whenever the vCPU is in C0, just as the host's IA32_MPERF MSR is incremented by hardware. Record the host TSC at vcpu_reset() to start tracking time spent in C0. Later patches will add the host TSC delta to the guest's stored IA32_MPERF value at appropriate points. Signed-off-by: Jim Mattson --- arch/x86/include/asm/kvm_host.h | 9 +++++++++ arch/x86/kvm/x86.c | 7 +++++++ 2 files changed, 16 insertions(+) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index 04ef56d10cbb1..067e6ec7f7e9c 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -738,6 +738,13 @@ struct kvm_queued_exception { bool has_payload; }; =20 +struct kvm_vcpu_aperfmperf { + u64 guest_aperf; + u64 guest_mperf; + u64 host_tsc; + bool loaded_while_running; +}; + struct kvm_vcpu_arch { /* * rip and regs accesses must go through @@ -1040,6 +1047,8 @@ struct kvm_vcpu_arch { #if IS_ENABLED(CONFIG_HYPERV) hpa_t hv_root_tdp; #endif + + struct kvm_vcpu_aperfmperf aperfmperf; }; =20 struct kvm_lpage_info { diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 3c6b0ca91e5f5..d66cccff13347 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -12476,6 +12476,13 @@ void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool in= it_event) =20 __kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP); __kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true); + + /* + * IA32_MPERF should start running now. Record the host TSC + * so that we can add the host TSC delta the next time that + * we load the guest [am]perf values into the hardware MSRs. + */ + vcpu->arch.aperfmperf.host_tsc =3D rdtsc(); } =20 /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */ --=20 2.47.0.371.ga323438b13-goog From nobody Sun Feb 8 09:32:30 2026 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBA2D1E0DA7 for ; Thu, 21 Nov 2024 18:53:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732215221; cv=none; b=kPo6jSQ5t5QMdQ2pyCjWRGKkFa0TwRsIQAo6dUYIRouMZRvamnHXnwZs9Xgfevd0O5X7ML535D+VNZn9ZK9tsuBoaXgK8YX8U33ROYDu0vhDYJfgtFwdKYn8Z/smR5r8wwi9BHI+ohHpqMrvJlR8DNebPxCoC9+9bH9th3b9V0w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732215221; c=relaxed/simple; bh=J443xY11+FlsZ1O8RFSn4sEVsfffWxAMll4hKwD4QB4=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=ftlCS6cZZHH/hwSfnH1BDhpD04Brur8jDaMEIgauPxxplHwsn9LZl1ChJVgMYyBs9mkFG3OcQmKV5Y2JjV+w3xTqDq0lCJ/FhX5GpslbsQ+/pwYvdT55kwo1ccadtxVg4815fZt5oFApJHRqR4Hbyk9/yQoFJyYyvVibKZX1KP8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--mizhang.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=iulUX1QA; arc=none smtp.client-ip=209.85.216.73 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--mizhang.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="iulUX1QA" Received: by mail-pj1-f73.google.com with SMTP id 98e67ed59e1d1-2ea2dd29d16so1313088a91.0 for ; Thu, 21 Nov 2024 10:53:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1732215219; x=1732820019; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=Zf8fZX+l+VoLEVD4pNXnS0cuADuy19dfjl6m0H+bXqc=; b=iulUX1QAMitX/+jSG7NTRLVmmstFGc9S3316onneVgEP3o2ky+RLaubbFAwI5YuF99 pzzIuOpS4a7CU8YORBBJk5K8V33wOgsvhmDz7Oi0yapJl40bXYVWAhop83ZKm/2/wnQs SbQSmekbTyBNge6FRpJuuFFY0LrTmjjSfgX2khX7Cyu07Hdurr6kCps+SgUU0t+0XCTs lAVET9aMiYtuGVb/pDbhV8Igxi46+FmA1LXu2mQeUlXwDD/CO4hQc6wiP31QZLPo2jNR bceTLjHcBLaenZEOhhh44hDyF5k8hZopkLy2Q3+odumVLfY8YKP8G0TB7U4XrsxoiIgK LKOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732215219; x=1732820019; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Zf8fZX+l+VoLEVD4pNXnS0cuADuy19dfjl6m0H+bXqc=; b=ow4TzwV98E+xH81xNy+xVrCf5ECM+wUtoxsyn6iZl+BrWO8znm2uK2SXZGE9ZfXDFN +vZe6E5qvTUEh1RVNMZJSbn1oNFi5j2/iYqQYqdtV7HSIl1xc2dsVCjfToWqpyj3jecX FQtUJXBg7AXTIheJhEVM6xNI0nbTMZ5Z+Q/oD0KIhYWpgJgQ7GCJXPeIZYTTnDRgUXKm M0MjMByahCfCZwwVMU/RNmxHvqUilXIAFHz+TqVNsWK4Trch1Z55+3x0l3eV0jHCefAx 6BdAqYN1L8blksoyzpqCtKCw0HQTLZsXKvgr8EUdT+gj1c2412sAhVSNFx+iLgefkdq6 LjuA== X-Forwarded-Encrypted: i=1; AJvYcCUeOtGtULj4OD6HIO9w/e9GAEnDBau6XfqOf0tlTAwEaCc7x3qxCSJMVq1ITwEV/UoG8j1sGhoSZO1souM=@vger.kernel.org X-Gm-Message-State: AOJu0Yzy4RuihkAbxZQKQqk/ZEKWf8Huj4yYbaNImP4CTVkrHRdzn6l7 I9Eue1HjlfWv3dnJ2K2lzCfsQJzwdrIlVZk8c4XCLJKf7zObg1pDwOBZudYzKLvpBSixwOxbDsB /OkroJg== X-Google-Smtp-Source: AGHT+IGYnMzeEjpt0TlemIbCUyvIDYTH0IyT6CjbExrl/UtCJsQ1yD4xmFeiL/4fw9BWaodK87t0RCsIAwvu X-Received: from mizhang-super.c.googlers.com ([35.247.89.60]) (user=mizhang job=sendgmr) by 2002:a17:90b:3694:b0:2ea:8548:3818 with SMTP id 98e67ed59e1d1-2eaca7fa74fmr3986a91.7.1732215218148; Thu, 21 Nov 2024 10:53:38 -0800 (PST) Reply-To: Mingwei Zhang Date: Thu, 21 Nov 2024 18:53:04 +0000 In-Reply-To: <20241121185315.3416855-1-mizhang@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241121185315.3416855-1-mizhang@google.com> X-Mailer: git-send-email 2.47.0.371.ga323438b13-goog Message-ID: <20241121185315.3416855-13-mizhang@google.com> Subject: [RFC PATCH 12/22] KVM: x86: Load guest [am]perf into hardware MSRs at vcpu_load() From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Huang Rui , "Gautham R. Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For vCPUs with APERFMPERF and in KVM_RUN, load the guest IA32_APERF and IA32_MPERF values into the hardware MSRs when loading the vCPU, but only if the vCPU is not halted. For running vCPUs, first add in any "background" C0 cycles accumulated since the last checkpoint. Note that for host TSC measurements of background C0 cycles, we assume IA32_MPERF increments at the same frequency as TSC. While this is true for all known processors with these MSRs, it is not architecturally guaranteed. Signed-off-by: Mingwei Zhang Co-developed-by: Jim Mattson Signed-off-by: Jim Mattson --- arch/x86/kvm/x86.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index d66cccff13347..b914578718d9c 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1918,6 +1918,22 @@ static int kvm_set_msr_ignored_check(struct kvm_vcpu= *vcpu, _kvm_set_msr); } =20 +/* + * Add elapsed TSC ticks to guest IA32_MPERF while vCPU is in C0 but + * not running. Uses TSC instead of host MPERF to include time when + * physical CPU is in lower C-states, as guest MPERF should count + * whenever vCPU is in C0. Assumes TSC and MPERF frequencies match. + */ +static void kvm_accumulate_background_guest_mperf(struct kvm_vcpu *vcpu) +{ + u64 now =3D rdtsc(); + s64 tsc_delta =3D now - vcpu->arch.aperfmperf.host_tsc; + + if (tsc_delta > 0) + vcpu->arch.aperfmperf.guest_mperf +=3D tsc_delta; + vcpu->arch.aperfmperf.host_tsc =3D now; +} + /* * Read the MSR specified by @index into @data. Select MSR specific fault * checks are bypassed if @host_initiated is %true. @@ -4980,6 +4996,19 @@ static bool need_emulate_wbinvd(struct kvm_vcpu *vcp= u) return kvm_arch_has_noncoherent_dma(vcpu->kvm); } =20 +static void kvm_load_guest_aperfmperf(struct kvm_vcpu *vcpu, bool update_m= perf) +{ + unsigned long flags; + + local_irq_save(flags); + if (update_mperf) + kvm_accumulate_background_guest_mperf(vcpu); + set_guest_aperf(vcpu->arch.aperfmperf.guest_aperf); + set_guest_mperf(vcpu->arch.aperfmperf.guest_mperf); + vcpu->arch.aperfmperf.loaded_while_running =3D true; + local_irq_restore(flags); +} + void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) { struct kvm_pmu *pmu =3D vcpu_to_pmu(vcpu); @@ -5039,6 +5068,12 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int c= pu) vcpu->cpu =3D cpu; } =20 + if (vcpu->wants_to_run && + guest_can_use(vcpu, X86_FEATURE_APERFMPERF) && + (vcpu->scheduled_out ? vcpu->arch.aperfmperf.loaded_while_running : + (vcpu->arch.mp_state !=3D KVM_MP_STATE_HALTED))) + kvm_load_guest_aperfmperf(vcpu, true); + kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); } =20 --=20 2.47.0.371.ga323438b13-goog From nobody Sun Feb 8 09:32:30 2026 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E81B1E0E0F for ; Thu, 21 Nov 2024 18:53:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732215223; cv=none; b=I1ezD/u7mnjqR0uAsDm78qELqmVisf99d97z5QOcs3oQ+r1UnN7RvgfMog2lSU9BrL+8Qlg5bwRK8IE7a8RQvvrWewu9waDXbDG4GGom5phCm11++dtCTVa93KwtFeGCCNvLvZ+t5Op2xuk7PG7nv+6tgFKNV+VwtTvlTkHYMfc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732215223; c=relaxed/simple; bh=Ia47x5eqWq7m7XvirgYoICFMCzP4YkrxFKv1nGHdVnI=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; 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Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jim Mattson When a vCPU transitions from HALTED to RUNNABLE, it resumes time keeping: its virtual IA32_MPERF MSR should start accumulating C0 cycles again. Load the guest values into the hardware MSRs for direct guest access. Background cycle accumulation is unnecessary at this point since the vCPU has been in C1, so the guest's IA32_MPERF has been stopped. Signed-off-by: Jim Mattson --- arch/x86/kvm/x86.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index b914578718d9c..acfa9ecc5bc36 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -11204,9 +11204,16 @@ int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) =20 void kvm_vcpu_make_runnable(struct kvm_vcpu *vcpu) { - if (vcpu->arch.mp_state =3D=3D KVM_MP_STATE_HALTED || - vcpu->arch.mp_state =3D=3D KVM_MP_STATE_AP_RESET_HOLD) + switch (vcpu->arch.mp_state) { + case KVM_MP_STATE_HALTED: + if (guest_can_use(vcpu, X86_FEATURE_APERFMPERF) && + vcpu->wants_to_run) + kvm_load_guest_aperfmperf(vcpu, false); + fallthrough; + case KVM_MP_STATE_AP_RESET_HOLD: vcpu->arch.pv.pv_unhalted =3D false; + break; + } vcpu->arch.mp_state =3D KVM_MP_STATE_RUNNABLE; vcpu->arch.apf.halted =3D false; } --=20 2.47.0.371.ga323438b13-goog From nobody Sun Feb 8 09:32:30 2026 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B1641E1302 for ; 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Thu, 21 Nov 2024 10:53:42 -0800 (PST) Reply-To: Mingwei Zhang Date: Thu, 21 Nov 2024 18:53:06 +0000 In-Reply-To: <20241121185315.3416855-1-mizhang@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241121185315.3416855-1-mizhang@google.com> X-Mailer: git-send-email 2.47.0.371.ga323438b13-goog Message-ID: <20241121185315.3416855-15-mizhang@google.com> Subject: [RFC PATCH 14/22] KVM: x86: Introduce kvm_user_return_notifier_register() From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Huang Rui , "Gautham R. Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jim Mattson Factor out user return notifier registration logic from kvm_set_user_return_msr() into a separate helper function to prepare for the registration of KVM's user return notifier from kvm_load_guest_aperfmperf(). No functional change intended. Signed-off-by: Jim Mattson --- arch/x86/kvm/x86.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index acfa9ecc5bc36..6df8f21b83eb1 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -637,6 +637,15 @@ static void kvm_user_return_msr_cpu_online(void) } } =20 +static void kvm_user_return_notifier_register(struct kvm_user_return_msrs = *msrs) +{ + if (!msrs->registered) { + msrs->urn.on_user_return =3D kvm_on_user_return; + user_return_notifier_register(&msrs->urn); + msrs->registered =3D true; + } +} + int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) { struct kvm_user_return_msrs *msrs =3D this_cpu_ptr(user_return_msrs); @@ -650,11 +659,7 @@ int kvm_set_user_return_msr(unsigned slot, u64 value, = u64 mask) return 1; =20 msrs->values[slot].curr =3D value; - if (!msrs->registered) { - msrs->urn.on_user_return =3D kvm_on_user_return; - user_return_notifier_register(&msrs->urn); - msrs->registered =3D true; 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Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jim Mattson Add support for restoring host IA32_APERF and IA32_MPERF values when returning to userspace. While not strictly necessary since reads of /dev/cpu/*/msr now reconstruct host values, restoring the host values maintains cleaner system state. Leverage KVM's existing user return notifier infrastructure but add a separate flag since these MSRs require dynamic value restoration rather than static value restoration. Restoration is only performed when guest values have been loaded into the hardware MSRs. Signed-off-by: Jim Mattson --- arch/x86/kvm/x86.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 6df8f21b83eb1..ad5351673362c 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -207,6 +207,7 @@ module_param(mitigate_smt_rsb, bool, 0444); struct kvm_user_return_msrs { struct user_return_notifier urn; bool registered; + bool restore_aperfmperf; struct kvm_user_return_msr_values { u64 host; u64 curr; @@ -571,6 +572,11 @@ static void kvm_on_user_return(struct user_return_noti= fier *urn) * interrupted and executed through kvm_arch_disable_virtualization_cpu() */ local_irq_save(flags); + if (msrs->restore_aperfmperf) { + restore_host_aperf(); + restore_host_mperf(); + msrs->restore_aperfmperf =3D false; + } if (msrs->registered) { msrs->registered =3D false; user_return_notifier_unregister(urn); @@ -5003,6 +5009,7 @@ static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) =20 static void kvm_load_guest_aperfmperf(struct kvm_vcpu *vcpu, bool update_m= perf) { + struct kvm_user_return_msrs *msrs; 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Thu, 21 Nov 2024 10:53:45 -0800 (PST) Reply-To: Mingwei Zhang Date: Thu, 21 Nov 2024 18:53:08 +0000 In-Reply-To: <20241121185315.3416855-1-mizhang@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241121185315.3416855-1-mizhang@google.com> X-Mailer: git-send-email 2.47.0.371.ga323438b13-goog Message-ID: <20241121185315.3416855-17-mizhang@google.com> Subject: [RFC PATCH 16/22] KVM: x86: Save guest [am]perf checkpoint on HLT From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Huang Rui , "Gautham R. Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When the guest executes HLT, the vCPU transitions from virtual C0 to C1 state. Its virtual IA32_APERF and IA32_MPERF MSRs should stop counting at this point, just as the host's MSRs stop when it enters C1. Save a checkpoint of the current hardware MSR values and host TSC. Later, if/when the vCPU becomes runnable again, we will start accumulating C0 cycles from this checkpoint. To avoid complications, also restore host MSR values at this time, Signed-off-by: Mingwei Zhang Co-developed-by: Jim Mattson Signed-off-by: Jim Mattson --- arch/x86/kvm/x86.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index ad5351673362c..793f5d2afeb2b 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -5139,6 +5139,21 @@ static void kvm_steal_time_set_preempted(struct kvm_= vcpu *vcpu) mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); } =20 +static void kvm_put_guest_aperfmperf(struct kvm_vcpu *vcpu) +{ + unsigned long flags; + + local_irq_save(flags); + if (vcpu->arch.aperfmperf.loaded_while_running) { + rdmsrl(MSR_IA32_APERF, vcpu->arch.aperfmperf.guest_aperf); + rdmsrl(MSR_IA32_MPERF, vcpu->arch.aperfmperf.guest_mperf); + vcpu->arch.aperfmperf.host_tsc =3D rdtsc(); + if (vcpu->arch.mp_state =3D=3D KVM_MP_STATE_HALTED) + vcpu->arch.aperfmperf.loaded_while_running =3D false; + } + local_irq_restore(flags); +} + void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) { int idx; @@ -11363,10 +11378,13 @@ static int __kvm_emulate_halt(struct kvm_vcpu *vc= pu, int state, int reason) */ ++vcpu->stat.halt_exits; if (lapic_in_kernel(vcpu)) { - if (kvm_vcpu_has_events(vcpu)) + if (kvm_vcpu_has_events(vcpu)) { vcpu->arch.pv.pv_unhalted =3D false; - else + } else { vcpu->arch.mp_state =3D state; + if (guest_can_use(vcpu, X86_FEATURE_APERFMPERF)) + kvm_put_guest_aperfmperf(vcpu); + } return 1; } else { vcpu->run->exit_reason =3D reason; --=20 2.47.0.371.ga323438b13-goog From nobody Sun Feb 8 09:32:30 2026 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CCB31E2311 for ; Thu, 21 Nov 2024 18:53:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.201 ARC-Seal: i=1; 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Thu, 21 Nov 2024 10:53:47 -0800 (PST) Reply-To: Mingwei Zhang Date: Thu, 21 Nov 2024 18:53:09 +0000 In-Reply-To: <20241121185315.3416855-1-mizhang@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241121185315.3416855-1-mizhang@google.com> X-Mailer: git-send-email 2.47.0.371.ga323438b13-goog Message-ID: <20241121185315.3416855-18-mizhang@google.com> Subject: [RFC PATCH 17/22] KVM: x86: Save guest [am]perf checkpoint on vcpu_put() From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Huang Rui , "Gautham R. Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For vCPUs with APERFMPERF that are in KVM_RUN and not halted, checkpoint the current hardware MSR values along with the host TSC when unloading the vCPU. While still in virtual C0 state, the vCPU will no longer run on this physical CPU, requiring different handling for each counter: - IA32_APERF should stop accumulating since no actual CPU cycles are being spent on behalf of the guest - IA32_MPERF should continue accumulating cycles since the guest is still in C0 state Later when the vCPU is reloaded, we'll use this checkpoint and the host TSC delta to properly account for any "background" cycles that should be reflected in the guest's IA32_MPERF value. Signed-off-by: Mingwei Zhang Co-developed-by: Jim Mattson Signed-off-by: Jim Mattson --- arch/x86/kvm/x86.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 793f5d2afeb2b..7c22bda3b1f7b 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -5173,6 +5173,11 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) srcu_read_unlock(&vcpu->kvm->srcu, idx); } =20 + if (vcpu->wants_to_run && + guest_can_use(vcpu, X86_FEATURE_APERFMPERF) && + vcpu->arch.aperfmperf.loaded_while_running) + kvm_put_guest_aperfmperf(vcpu); + kvm_x86_call(vcpu_put)(vcpu); vcpu->arch.last_host_tsc =3D rdtsc(); } --=20 2.47.0.371.ga323438b13-goog From nobody Sun Feb 8 09:32:30 2026 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 954551E1C3E for ; Thu, 21 Nov 2024 18:53:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 21 Nov 2024 10:53:48 -0800 (PST) Reply-To: Mingwei Zhang Date: Thu, 21 Nov 2024 18:53:10 +0000 In-Reply-To: <20241121185315.3416855-1-mizhang@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241121185315.3416855-1-mizhang@google.com> X-Mailer: git-send-email 2.47.0.371.ga323438b13-goog Message-ID: <20241121185315.3416855-19-mizhang@google.com> Subject: [RFC PATCH 18/22] KVM: x86: Update aperfmperf on host-initiated MP_STATE transitions From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Huang Rui , "Gautham R. Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jim Mattson When the host modifies a vCPU's MP_STATE after the vCPU has started running, maintain the accuracy of guest aperfmperf tracking: 1. For transitions from !HALTED to HALTED, add any accumulated "background" TSC ticks to the guest_mperf checkpoint before stopping the counter. 2. For transitions from HALTED to !HALTED, record the current TSC in host_tsc to begin accumulating background cycles in guest_mperf. This ensures the guest MPERF counter properly reflects time spent in C0 vs C1 states, even when state transitions are initiated by the host rather than the guest. Signed-off-by: Jim Mattson Reviewed-by: Mingwei Zhang Signed-off-by: Mingwei Zhang --- arch/x86/kvm/x86.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 7c22bda3b1f7b..cd1f1ae86f83f 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -11904,6 +11904,18 @@ int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcp= u *vcpu, mp_state->mp_state =3D=3D KVM_MP_STATE_INIT_RECEIVED)) goto out; =20 + if (kvm_vcpu_has_run(vcpu) && + guest_can_use(vcpu, X86_FEATURE_APERFMPERF)) { + if (mp_state->mp_state =3D=3D KVM_MP_STATE_HALTED && + vcpu->arch.mp_state !=3D KVM_MP_STATE_HALTED) { + kvm_accumulate_background_guest_mperf(vcpu); + vcpu->arch.aperfmperf.loaded_while_running =3D false; + } else if (mp_state->mp_state !=3D KVM_MP_STATE_HALTED && + vcpu->arch.mp_state =3D=3D KVM_MP_STATE_HALTED) { + vcpu->arch.aperfmperf.host_tsc =3D rdtsc(); + } + } + if (mp_state->mp_state =3D=3D KVM_MP_STATE_SIPI_RECEIVED) { vcpu->arch.mp_state =3D KVM_MP_STATE_INIT_RECEIVED; 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AJvYcCWc1YXwGX7YeMaTRRm0nsrxofwkvt9B6Bx6ppnOlponAWiZJBSruOEo4lgxBggXI11t4xdqkrh0IjmMhN4=@vger.kernel.org X-Gm-Message-State: AOJu0YzhXtqUdTpSSkOQwWgEml5omjNUBl0c6blZe1hK+6WHZVSu0JPT OQL6VTMcKM4DJ9zuqVfhNfO42nrD111VAe+AHSieu60OVcx+HjAkah49NWxOHYn1V0X/0mwiPqQ OUsFxdw== X-Google-Smtp-Source: AGHT+IG4i7fOAFePg97UFWHvr+E2Z6FO0kC5FD9Us3UIujj+wD5TBePM+4bKH0fL2aTTdEKp0RfkKSC8TCCi X-Received: from mizhang-super.c.googlers.com ([34.105.13.176]) (user=mizhang job=sendgmr) by 2002:a25:ba4c:0:b0:e38:10a7:808e with SMTP id 3f1490d57ef6-e38f889f2ddmr1276.0.1732215230445; Thu, 21 Nov 2024 10:53:50 -0800 (PST) Reply-To: Mingwei Zhang Date: Thu, 21 Nov 2024 18:53:11 +0000 In-Reply-To: <20241121185315.3416855-1-mizhang@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241121185315.3416855-1-mizhang@google.com> X-Mailer: git-send-email 2.47.0.371.ga323438b13-goog Message-ID: <20241121185315.3416855-20-mizhang@google.com> Subject: [RFC PATCH 19/22] KVM: x86: Allow host and guest access to IA32_[AM]PERF From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Huang Rui , "Gautham R. Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Implement MSR read/write handlers for IA32_APERF and IA32_MPERF to support both host and guest access: - Host userspace access via KVM_[GS]ET_MSRS only reads/writes the snapshot values in vcpu->arch.aperfmperf - Guest writes update both the hardware MSRs (via set_guest_[am]perf) and the snapshots - For host-initiated writes of IA32_MPERF, record the current TSC to establish a new baseline for background cycle accumulation - Guest reads don't reach these handlers as they access the MSRs directly Add both MSRs to msrs_to_save_base[] to ensure they are properly serialized during vCPU state save/restore operations. Signed-off-by: Mingwei Zhang Co-developed-by: Jim Mattson Signed-off-by: Jim Mattson --- arch/x86/kvm/x86.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index cd1f1ae86f83f..4394ecb291401 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -334,6 +334,7 @@ static const u32 msrs_to_save_base[] =3D { MSR_IA32_UMWAIT_CONTROL, =20 MSR_IA32_XFD, MSR_IA32_XFD_ERR, + MSR_IA32_APERF, MSR_IA32_MPERF, }; =20 static const u32 msrs_to_save_pmu[] =3D { @@ -4151,6 +4152,26 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct= msr_data *msr_info) return 1; vcpu->arch.msr_misc_features_enables =3D data; break; + case MSR_IA32_APERF: + if ((data || !msr_info->host_initiated) && + !guest_can_use(vcpu, X86_FEATURE_APERFMPERF)) + return 1; + + vcpu->arch.aperfmperf.guest_aperf =3D data; + if (unlikely(!msr_info->host_initiated)) + set_guest_aperf(data); + break; + case MSR_IA32_MPERF: + if ((data || !msr_info->host_initiated) && + !guest_can_use(vcpu, X86_FEATURE_APERFMPERF)) + return 1; + + vcpu->arch.aperfmperf.guest_mperf =3D data; + if (likely(msr_info->host_initiated)) + vcpu->arch.aperfmperf.host_tsc =3D rdtsc(); + else + set_guest_mperf(data); + break; #ifdef CONFIG_X86_64 case MSR_IA32_XFD: if (!msr_info->host_initiated && @@ -4524,6 +4545,22 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct= msr_data *msr_info) msr_info->data =3D vcpu->arch.guest_fpu.xfd_err; break; #endif + case MSR_IA32_APERF: + /* Guest read access should never reach here. */ + if (!msr_info->host_initiated) + return 1; + + msr_info->data =3D vcpu->arch.aperfmperf.guest_aperf; + break; + case MSR_IA32_MPERF: + /* Guest read access should never reach here. */ + if (!msr_info->host_initiated) + return 1; + + if (vcpu->arch.mp_state !=3D KVM_MP_STATE_HALTED) + kvm_accumulate_background_guest_mperf(vcpu); + msr_info->data =3D vcpu->arch.aperfmperf.guest_mperf; + break; default: if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) return kvm_pmu_get_msr(vcpu, msr_info); @@ -7535,6 +7572,11 @@ static void kvm_probe_msr_to_save(u32 msr_index) if (!(kvm_get_arch_capabilities() & ARCH_CAP_TSX_CTRL_MSR)) return; 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Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allow direct guest rdmsr access to IA32_APERF and IA32_MPERF while continuing to intercept guest wrmsr. Direct read access reduces overhead for guests that poll these MSRs frequently (e.g. every scheduler tick), while write interception remains necessary to maintain proper host offset tracking. Signed-off-by: Mingwei Zhang Co-developed-by: Jim Mattson Signed-off-by: Jim Mattson --- arch/x86/kvm/vmx/vmx.c | 7 +++++++ arch/x86/kvm/vmx/vmx.h | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index d28618e9277ed..07f013912370e 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -186,6 +186,8 @@ static u32 vmx_possible_passthrough_msrs[MAX_POSSIBLE_P= ASSTHROUGH_MSRS] =3D { MSR_CORE_C3_RESIDENCY, MSR_CORE_C6_RESIDENCY, MSR_CORE_C7_RESIDENCY, + MSR_IA32_APERF, + MSR_IA32_MPERF, }; =20 /* @@ -7871,6 +7873,11 @@ void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) vmx_set_intercept_for_msr(vcpu, MSR_IA32_FLUSH_CMD, MSR_TYPE_W, !guest_cpuid_has(vcpu, X86_FEATURE_FLUSH_L1D)); =20 + vmx_set_intercept_for_msr(vcpu, MSR_IA32_APERF, MSR_TYPE_R, + !guest_can_use(vcpu, X86_FEATURE_APERFMPERF)); + vmx_set_intercept_for_msr(vcpu, MSR_IA32_MPERF, MSR_TYPE_R, + !guest_can_use(vcpu, X86_FEATURE_APERFMPERF)); + set_cr4_guest_host_mask(vmx); =20 vmx_write_encls_bitmap(vcpu, NULL); diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index 2325f773a20be..929f153cdcbae 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -356,7 +356,7 @@ struct vcpu_vmx { struct lbr_desc lbr_desc; =20 /* Save desired MSR intercept (read: pass-through) state */ -#define MAX_POSSIBLE_PASSTHROUGH_MSRS 16 +#define MAX_POSSIBLE_PASSTHROUGH_MSRS 18 struct { DECLARE_BITMAP(read, MAX_POSSIBLE_PASSTHROUGH_MSRS); DECLARE_BITMAP(write, MAX_POSSIBLE_PASSTHROUGH_MSRS); --=20 2.47.0.371.ga323438b13-goog From nobody Sun Feb 8 09:32:30 2026 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73FF91E376B for ; Thu, 21 Nov 2024 18:53:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.201 ARC-Seal: i=1; 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Thu, 21 Nov 2024 10:53:53 -0800 (PST) Reply-To: Mingwei Zhang Date: Thu, 21 Nov 2024 18:53:13 +0000 In-Reply-To: <20241121185315.3416855-1-mizhang@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241121185315.3416855-1-mizhang@google.com> X-Mailer: git-send-email 2.47.0.371.ga323438b13-goog Message-ID: <20241121185315.3416855-22-mizhang@google.com> Subject: [RFC PATCH 21/22] KVM: SVM: Pass through guest reads of IA32_[AM]PERF From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Huang Rui , "Gautham R. Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allow direct guest rdmsr access to IA32_APERF and IA32_MPERF while continuing to intercept guest wrmsr. Direct read access reduces overhead for guests that poll these MSRs frequently (e.g. every scheduler tick), while write interception remains necessary to maintain proper host offset tracking. Signed-off-by: Mingwei Zhang Co-developed-by: Jim Mattson Signed-off-by: Jim Mattson --- arch/x86/kvm/svm/svm.c | 7 +++++++ arch/x86/kvm/svm/svm.h | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 9df3e1e5ae81a..332947e0e9670 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -142,6 +142,8 @@ static const struct svm_direct_access_msrs { { .index =3D X2APIC_MSR(APIC_TMICT), .always =3D false }, { .index =3D X2APIC_MSR(APIC_TMCCT), .always =3D false }, { .index =3D X2APIC_MSR(APIC_TDCR), .always =3D false }, + { .index =3D MSR_IA32_APERF, .always =3D false }, + { .index =3D MSR_IA32_MPERF, .always =3D false }, { .index =3D MSR_INVALID, .always =3D false }, }; =20 @@ -1231,6 +1233,11 @@ static inline void init_vmcb_after_set_cpuid(struct = kvm_vcpu *vcpu) set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 1, 1); set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 1, 1); } + + set_msr_interception(vcpu, svm->msrpm, MSR_IA32_APERF, + guest_can_use(vcpu, X86_FEATURE_APERFMPERF), 0); + set_msr_interception(vcpu, svm->msrpm, MSR_IA32_MPERF, + guest_can_use(vcpu, X86_FEATURE_APERFMPERF), 0); } =20 static void init_vmcb(struct kvm_vcpu *vcpu) diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 43fa6a16eb191..5ae5a13b9771a 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -44,7 +44,7 @@ static inline struct page *__sme_pa_to_page(unsigned long= pa) #define IOPM_SIZE PAGE_SIZE * 3 #define MSRPM_SIZE PAGE_SIZE * 2 =20 -#define MAX_DIRECT_ACCESS_MSRS 48 +#define MAX_DIRECT_ACCESS_MSRS 50 #define MSRPM_OFFSETS 32 extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; extern bool npt_enabled; --=20 2.47.0.371.ga323438b13-goog From nobody Sun Feb 8 09:32:30 2026 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 090EB1E3DF1 for ; Thu, 21 Nov 2024 18:53:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 21 Nov 2024 10:53:55 -0800 (PST) Reply-To: Mingwei Zhang Date: Thu, 21 Nov 2024 18:53:14 +0000 In-Reply-To: <20241121185315.3416855-1-mizhang@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241121185315.3416855-1-mizhang@google.com> X-Mailer: git-send-email 2.47.0.371.ga323438b13-goog Message-ID: <20241121185315.3416855-23-mizhang@google.com> Subject: [RFC PATCH 22/22] KVM: x86: Enable guest usage of X86_FEATURE_APERFMPERF From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Huang Rui , "Gautham R. Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable support for IA32_APERF/IA32_MPERF performance monitoring in KVM guests. These MSRs allow guests to measure their effective CPU frequency by comparing actual CPU cycles (APERF) against reference cycles (MPERF). Only expose X86_FEATURE_APERFMPERF to guests when the host has both CONSTANT_TSC and NONSTOP_TSC. These features ensure the TSC frequency remains stable across C-states and P-states, which is necessary for "background" MPERF accounting. Guest TSC scaling via KVM_SET_TSC_KHZ is not supported: - On Intel, IA32_MPERF ticks at host rate regardless of guest TSC scaling, making passthrough impossible without intercepting reads - On AMD, guest TSC scaling does affect IA32_MPERF reads, but handling it would significantly complicate cycle accounting Record host support in kvm_cpu_caps[], advertise the feature to userspace via CPUID.06H:ECX, and enable the governed feature when supported by both host and guest CPUID. Signed-off-by: Mingwei Zhang Co-developed-by: Jim Mattson Signed-off-by: Jim Mattson --- arch/x86/kvm/cpuid.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 41786b834b163..309fa7fef6b7b 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -399,6 +399,10 @@ static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *= vcpu) kvm_hv_set_cpuid(vcpu, kvm_cpuid_has_hyperv(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent)); =20 + if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC) && + boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) + kvm_governed_feature_check_and_set(vcpu, X86_FEATURE_APERFMPERF); + /* Invoke the vendor callback only after the above state is updated. */ kvm_x86_call(vcpu_after_set_cpuid)(vcpu); =20 @@ -697,6 +701,12 @@ void kvm_set_cpu_caps(void) if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); =20 + if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC) && + boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) + kvm_cpu_cap_init_kvm_defined(CPUID_6_ECX, F(APERFMPERF)); + else + kvm_cpu_cap_init_kvm_defined(CPUID_6_ECX, 0); + kvm_cpu_cap_mask(CPUID_7_1_EAX, F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) | F(FZRM) | F(FSRS) | F(FSRC) | @@ -993,7 +1003,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_arr= ay *array, u32 function) case 6: /* Thermal management */ entry->eax =3D 0x4; /* allow ARAT */ entry->ebx =3D 0; - entry->ecx =3D 0; + cpuid_entry_override(entry, CPUID_6_ECX); entry->edx =3D 0; break; /* function 7 has additional index. */ --=20 2.47.0.371.ga323438b13-goog