From nobody Fri Nov 22 08:40:02 2024 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 140BE1D90BC; Thu, 21 Nov 2024 13:22:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732195341; cv=none; b=qSvTFr1BZoJGcXNcUTb26E8ZOcqypqORz5DC06kiJ9ug47AdQFubtmZ5wg9uZCXBbZ2m0vbsFB2WJT9Fd0DMMSegldncq5iJprKUbVEogixdmrNWcNomnFucQIeqgDIrEKii/oy8hG2UGVuSWvxlfAvD5mUJLnIJznfJ74OJ5sk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732195341; c=relaxed/simple; bh=CTQetKNlzwCMRDezxXu+21CNWvmxzreYOgRj0hCbpf4=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=EKlP2BKxEdRVxXSCyOK40xwzXDypoFaEyfY0GdN4gu/RVQKIJJaIOo3xWcMY9VGsdCsz1FxHb0oNsuLxRvT/LselZtb1Lv31SShij/yUc7dUo5yOtnTKe09P3QDhy/jI2mmR/z1KDVYk72+L/BRG6rS2WNe5xcAXXPExhyeW+3c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=wGNVmgNe; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="wGNVmgNe" Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4ALAXHH1002018; Thu, 21 Nov 2024 14:21:59 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= q6VXupjnTEVVWDbEaH7UOHhbUPZqhwx1VwGrB1UH9yU=; b=wGNVmgNeT2/V4w9V my1uP2fOyC4FGUIydvyH99C0JUWz4p8howTZsncn324xTCNAiuzWAsh8dcAlr1aq krW/hVjCnP0wnl/1khp0bYYpOJcqganzOPGc+H9cUKNiAZiDgOejLfQhGOdEePxe LtZgRxy3FVIjRMubb3j9RgHDXlPqhCU928UP/Ol4ZPkqJqWrzK4mswJ62zvKpyOX Yqu6WZSkug3Q1Sq1RbHsXBMm7sOZ+LGcRVLvngbbwSvOkJvclt2Av5YBcyUFegqu lZ4vhp+Cl9bG3lvSxpvTu7Ck+E2hgxTPEVeVHb6pWugFaktS4t+Vv2HuRU2tsfUg Pjq7JA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 42y77nmea8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Nov 2024 14:21:59 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id C5D484004A; Thu, 21 Nov 2024 14:20:15 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 9D9A32843CC; Thu, 21 Nov 2024 14:19:08 +0100 (CET) Received: from localhost (10.48.86.208) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Thu, 21 Nov 2024 14:19:08 +0100 From: Hugues Fruchet To: Mauro Carvalho Chehab , Ezequiel Garcia , Philipp Zabel , Alexandre Torgue , Hugues Fruchet , Sebastian Fricke , Ricardo Ribalda , Erling Ljunggren , Hans Verkuil , Laurent Pinchart , Sakari Ailus , Jacopo Mondi , Jean-Michel Hautbois , Benjamin Gaignard , , , , , Subject: [PATCH v3 2/3] media: verisilicon: add WebP decoding support Date: Thu, 21 Nov 2024 14:19:03 +0100 Message-ID: <20241121131904.261230-3-hugues.fruchet@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241121131904.261230-1-hugues.fruchet@foss.st.com> References: <20241121131904.261230-1-hugues.fruchet@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Content-Type: text/plain; charset="utf-8" Add WebP picture decoding support to VP8 stateless decoder. Signed-off-by: Hugues Fruchet --- .../media/platform/verisilicon/hantro_g1_regs.h | 1 + .../platform/verisilicon/hantro_g1_vp8_dec.c | 14 ++++++++++++++ .../media/platform/verisilicon/hantro_v4l2.c | 2 ++ .../platform/verisilicon/stm32mp25_vpu_hw.c | 17 +++++++++++++++-- 4 files changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/verisilicon/hantro_g1_regs.h b/drivers/= media/platform/verisilicon/hantro_g1_regs.h index c623b3b0be18..e7d4db788e57 100644 --- a/drivers/media/platform/verisilicon/hantro_g1_regs.h +++ b/drivers/media/platform/verisilicon/hantro_g1_regs.h @@ -232,6 +232,7 @@ #define G1_REG_DEC_CTRL7_DCT7_START_BIT(x) (((x) & 0x3f) << 0) #define G1_REG_ADDR_STR 0x030 #define G1_REG_ADDR_DST 0x034 +#define G1_REG_ADDR_DST_CHROMA 0x038 #define G1_REG_ADDR_REF(i) (0x038 + ((i) * 0x4)) #define G1_REG_ADDR_REF_FIELD_E BIT(1) #define G1_REG_ADDR_REF_TOPC_E BIT(0) diff --git a/drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c b/drive= rs/media/platform/verisilicon/hantro_g1_vp8_dec.c index 851eb67f19f5..c83ee6f5edc8 100644 --- a/drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c +++ b/drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c @@ -307,6 +307,12 @@ static void cfg_parts(struct hantro_ctx *ctx, G1_REG_DEC_CTRL3_STREAM_LEN(dct_part_total_len), G1_REG_DEC_CTRL3); =20 + if (ctx->vpu_src_fmt->fourcc =3D=3D V4L2_PIX_FMT_WEBP_FRAME) + vdpu_write_relaxed(vpu, + G1_REG_DEC_CTRL3_STREAM_LEN_EXT + (dct_part_total_len >> 24), + G1_REG_DEC_CTRL3); + /* DCT partitions base address */ for (i =3D 0; i < hdr->num_dct_parts; i++) { u32 byte_offset =3D dct_part_offset + dct_size_part_size + count; @@ -427,6 +433,12 @@ static void cfg_buffers(struct hantro_ctx *ctx, =20 dst_dma =3D hantro_get_dec_buf_addr(ctx, &vb2_dst->vb2_buf); vdpu_write_relaxed(vpu, dst_dma, G1_REG_ADDR_DST); + + if (ctx->vpu_src_fmt->fourcc =3D=3D V4L2_PIX_FMT_WEBP_FRAME) + vdpu_write_relaxed(vpu, dst_dma + + ctx->dst_fmt.plane_fmt[0].bytesperline * + ctx->dst_fmt.height, + G1_REG_ADDR_DST_CHROMA); } =20 int hantro_g1_vp8_dec_run(struct hantro_ctx *ctx) @@ -471,6 +483,8 @@ int hantro_g1_vp8_dec_run(struct hantro_ctx *ctx) reg |=3D G1_REG_DEC_CTRL0_SKIP_MODE; if (hdr->lf.level =3D=3D 0) reg |=3D G1_REG_DEC_CTRL0_FILTERING_DIS; + if (ctx->vpu_src_fmt->fourcc =3D=3D V4L2_PIX_FMT_WEBP_FRAME) + reg |=3D G1_REG_DEC_CTRL0_WEBP_E; vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL0); =20 /* Frame dimensions */ diff --git a/drivers/media/platform/verisilicon/hantro_v4l2.c b/drivers/med= ia/platform/verisilicon/hantro_v4l2.c index 2513adfbd825..7075b2ba1ec2 100644 --- a/drivers/media/platform/verisilicon/hantro_v4l2.c +++ b/drivers/media/platform/verisilicon/hantro_v4l2.c @@ -470,6 +470,7 @@ hantro_update_requires_request(struct hantro_ctx *ctx, = u32 fourcc) break; case V4L2_PIX_FMT_MPEG2_SLICE: case V4L2_PIX_FMT_VP8_FRAME: + case V4L2_PIX_FMT_WEBP_FRAME: case V4L2_PIX_FMT_H264_SLICE: case V4L2_PIX_FMT_HEVC_SLICE: case V4L2_PIX_FMT_VP9_FRAME: @@ -492,6 +493,7 @@ hantro_update_requires_hold_capture_buf(struct hantro_c= tx *ctx, u32 fourcc) case V4L2_PIX_FMT_JPEG: case V4L2_PIX_FMT_MPEG2_SLICE: case V4L2_PIX_FMT_VP8_FRAME: + case V4L2_PIX_FMT_WEBP_FRAME: case V4L2_PIX_FMT_HEVC_SLICE: case V4L2_PIX_FMT_VP9_FRAME: vq->subsystem_flags &=3D ~(VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF); diff --git a/drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c b/driver= s/media/platform/verisilicon/stm32mp25_vpu_hw.c index 833821120b20..c291b1560e20 100644 --- a/drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c +++ b/drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c @@ -22,10 +22,10 @@ static const struct hantro_fmt stm32mp25_vdec_fmts[] = =3D { .codec_mode =3D HANTRO_MODE_NONE, .frmsize =3D { .min_width =3D FMT_MIN_WIDTH, - .max_width =3D FMT_FHD_WIDTH, + .max_width =3D FMT_4K_WIDTH, .step_width =3D MB_DIM, .min_height =3D FMT_MIN_HEIGHT, - .max_height =3D FMT_FHD_HEIGHT, + .max_height =3D FMT_4K_HEIGHT, .step_height =3D MB_DIM, }, }, @@ -42,6 +42,19 @@ static const struct hantro_fmt stm32mp25_vdec_fmts[] =3D= { .step_height =3D MB_DIM, }, }, + { + .fourcc =3D V4L2_PIX_FMT_WEBP_FRAME, + .codec_mode =3D HANTRO_MODE_VP8_DEC, + .max_depth =3D 2, + .frmsize =3D { + .min_width =3D FMT_MIN_WIDTH, + .max_width =3D FMT_4K_WIDTH, + .step_width =3D MB_DIM, + .min_height =3D FMT_MIN_HEIGHT, + .max_height =3D FMT_4K_HEIGHT, + .step_height =3D MB_DIM, + }, + }, { .fourcc =3D V4L2_PIX_FMT_H264_SLICE, .codec_mode =3D HANTRO_MODE_H264_DEC, --=20 2.25.1