From nobody Fri Nov 22 03:06:50 2024 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 394671D8A08; Thu, 21 Nov 2024 13:22:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732195341; cv=none; b=iUJfL5/iN2Nqp6ITegO6raFVnq4qkTevbq10hAvPd6zACKOi12Fl28DjtmoIsVtI6FtraU6Rb9lQBUmSV7Xhp1FEWdOVcuptEkl0B6ubkAz92kEaeQjC1KR/w0hFvU4Gw1Gzkz0Lkk1vyvT/9OUNLo+ADONhJoLKS0zPuoSH5vA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732195341; c=relaxed/simple; bh=EB19uHX/YB85zhyt6+8/eAmqNwUwzHo7pwUq2OaMchU=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TBv+sB0Pmjfzo8DjaL81wa7D+XvWecn6rp5ifazVoQc1fzkFcL51axzZ6lBOa74WsdGUqR6R8AaA6pQEipFHxqA6mMRZt3MmXSXD6ENCdLMBU/z2HQYRaaJJmkbdRmumLSSLm0uUxPmIRY2fmKECegSwsiHyrufKMtdYCsJBirY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=p6FrRAAC; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="p6FrRAAC" Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4ALBeQQh032344; Thu, 21 Nov 2024 14:21:59 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= e8LQCstHdgkhmoXO872hDxjShUfxudEBRkObGgEdqWo=; b=p6FrRAACkwPjjSPA 11INp/FuzrKreawEA7zwbc9yrlJLSbr0jj8vXerS/5MDbBqw73VHXTgTPYnHNwZV 0+5E1pHvGV4Ltbp8wYeJx92nC3IkzPxxOFVD1NQkqmJLXyn7timay4tVcwRZtjWp i09uToGmr272+PNOpS+DM+5Pj2JX4eN0+8aPUuOniExrZ7uNt4p0b1L9sVtAuj6c HzD3kHTp1duHnxuS2xEY5vzDYe3LE9IbiXREQoc4Uq+SUo+W/KIkSpxjAsaWvzfA bAV2ZHeRgQHhWT3Hiltyc0lQDmRK+VLujHyJksDU8POm1L0utw5HjmBF08S0f1iQ PkymNw== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 42xkqf6rsr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Nov 2024 14:21:59 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id C22244002D; Thu, 21 Nov 2024 14:20:15 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id D65D22843D2; Thu, 21 Nov 2024 14:19:07 +0100 (CET) Received: from localhost (10.48.86.208) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Thu, 21 Nov 2024 14:19:07 +0100 From: Hugues Fruchet To: Mauro Carvalho Chehab , Ezequiel Garcia , Philipp Zabel , Alexandre Torgue , Hugues Fruchet , Sebastian Fricke , Ricardo Ribalda , Erling Ljunggren , Hans Verkuil , Laurent Pinchart , Sakari Ailus , Jacopo Mondi , Jean-Michel Hautbois , Benjamin Gaignard , , , , , Subject: [PATCH v3 1/3] media: uapi: add WebP uAPI Date: Thu, 21 Nov 2024 14:19:02 +0100 Message-ID: <20241121131904.261230-2-hugues.fruchet@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241121131904.261230-1-hugues.fruchet@foss.st.com> References: <20241121131904.261230-1-hugues.fruchet@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Content-Type: text/plain; charset="utf-8" This patch adds the WebP picture decoding kernel uAPI. This design is based on currently available VP8 API implementation and aims to support the development of WebP stateless video codecs on Linux. Signed-off-by: Hugues Fruchet --- .../userspace-api/media/v4l/biblio.rst | 9 +++++++++ .../media/v4l/pixfmt-compressed.rst | 17 +++++++++++++++++ drivers/media/v4l2-core/v4l2-ioctl.c | 1 + include/uapi/linux/videodev2.h | 1 + 4 files changed, 28 insertions(+) diff --git a/Documentation/userspace-api/media/v4l/biblio.rst b/Documentati= on/userspace-api/media/v4l/biblio.rst index 35674eeae20d..df3e963fc54f 100644 --- a/Documentation/userspace-api/media/v4l/biblio.rst +++ b/Documentation/userspace-api/media/v4l/biblio.rst @@ -447,3 +447,12 @@ AV1 :title: AV1 Bitstream & Decoding Process Specification =20 :author: Peter de Rivaz, Argon Design Ltd, Jack Haughton, Argon Design = Ltd + +.. _webp: + +WEBP +=3D=3D=3D=3D + +:title: WEBP picture Bitstream & Decoding Process Specification + +:author: Google (https://developers.google.com/speed/webp) diff --git a/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst b/= Documentation/userspace-api/media/v4l/pixfmt-compressed.rst index 806ed73ac474..08a989511e7d 100644 --- a/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst +++ b/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst @@ -169,6 +169,23 @@ Compressed Formats this pixel format. The output buffer must contain the appropriate number of macroblocks to decode a full corresponding frame to the matching capture buffer. + * .. _V4L2-PIX-FMT-WEBP-FRAME: + + - ``V4L2_PIX_FMT_WEBP_FRAME`` + - 'WEBP' + - WEBP VP8 parsed frame, excluding WEBP RIFF header, keeping only th= e VP8 + bitstream including the frame header, as extracted from the container. + This format is adapted for stateless video decoders that implement a + WEBP pipeline with the :ref:`stateless_decoder`. + Metadata associated with the frame to decode is required to be passed + through the ``V4L2_CID_STATELESS_VP8_FRAME`` control. + See the :ref:`associated Codec Control IDs `. + Because of key frames only bitstream, ``V4L2_VP8_FRAME_FLAG_KEY_FRAME`` + flag must be set, see :ref:`Frame Flags `. + Exactly one output and one capture buffer must be provided for use with + this pixel format. The output buffer must contain the appropriate number + of macroblocks to decode a full corresponding frame to the matching + capture buffer. =20 * .. _V4L2-PIX-FMT-VP9: =20 diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core= /v4l2-ioctl.c index 0304daa8471d..e2ff03d0d773 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c @@ -1501,6 +1501,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) case V4L2_PIX_FMT_VC1_ANNEX_L: descr =3D "VC-1 (SMPTE 412M Annex L)"; br= eak; case V4L2_PIX_FMT_VP8: descr =3D "VP8"; break; case V4L2_PIX_FMT_VP8_FRAME: descr =3D "VP8 Frame"; break; + case V4L2_PIX_FMT_WEBP_FRAME: descr =3D "WEBP VP8 Frame"; break; case V4L2_PIX_FMT_VP9: descr =3D "VP9"; break; case V4L2_PIX_FMT_VP9_FRAME: descr =3D "VP9 Frame"; break; case V4L2_PIX_FMT_HEVC: descr =3D "HEVC"; break; /* aka H.265 */ diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index e7c4dce39007..09fff269e852 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -757,6 +757,7 @@ struct v4l2_pix_format { #define V4L2_PIX_FMT_VC1_ANNEX_L v4l2_fourcc('V', 'C', '1', 'L') /* SMPTE = 421M Annex L compliant stream */ #define V4L2_PIX_FMT_VP8 v4l2_fourcc('V', 'P', '8', '0') /* VP8 */ #define V4L2_PIX_FMT_VP8_FRAME v4l2_fourcc('V', 'P', '8', 'F') /* VP8 pars= ed frame */ +#define V4L2_PIX_FMT_WEBP_FRAME v4l2_fourcc('W', 'B', 'P', 'F') /* WEBP VP= 8 parsed frame */ #define V4L2_PIX_FMT_VP9 v4l2_fourcc('V', 'P', '9', '0') /* VP9 */ #define V4L2_PIX_FMT_VP9_FRAME v4l2_fourcc('V', 'P', '9', 'F') /* VP9 pars= ed frame */ #define V4L2_PIX_FMT_HEVC v4l2_fourcc('H', 'E', 'V', 'C') /* HEVC aka = H.265 */ --=20 2.25.1 From nobody Fri Nov 22 03:06:50 2024 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 140BE1D90BC; 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charset="utf-8" Add WebP picture decoding support to VP8 stateless decoder. Signed-off-by: Hugues Fruchet --- .../media/platform/verisilicon/hantro_g1_regs.h | 1 + .../platform/verisilicon/hantro_g1_vp8_dec.c | 14 ++++++++++++++ .../media/platform/verisilicon/hantro_v4l2.c | 2 ++ .../platform/verisilicon/stm32mp25_vpu_hw.c | 17 +++++++++++++++-- 4 files changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/verisilicon/hantro_g1_regs.h b/drivers/= media/platform/verisilicon/hantro_g1_regs.h index c623b3b0be18..e7d4db788e57 100644 --- a/drivers/media/platform/verisilicon/hantro_g1_regs.h +++ b/drivers/media/platform/verisilicon/hantro_g1_regs.h @@ -232,6 +232,7 @@ #define G1_REG_DEC_CTRL7_DCT7_START_BIT(x) (((x) & 0x3f) << 0) #define G1_REG_ADDR_STR 0x030 #define G1_REG_ADDR_DST 0x034 +#define G1_REG_ADDR_DST_CHROMA 0x038 #define G1_REG_ADDR_REF(i) (0x038 + ((i) * 0x4)) #define G1_REG_ADDR_REF_FIELD_E BIT(1) #define G1_REG_ADDR_REF_TOPC_E BIT(0) diff --git a/drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c b/drive= rs/media/platform/verisilicon/hantro_g1_vp8_dec.c index 851eb67f19f5..c83ee6f5edc8 100644 --- a/drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c +++ b/drivers/media/platform/verisilicon/hantro_g1_vp8_dec.c @@ -307,6 +307,12 @@ static void cfg_parts(struct hantro_ctx *ctx, G1_REG_DEC_CTRL3_STREAM_LEN(dct_part_total_len), G1_REG_DEC_CTRL3); =20 + if (ctx->vpu_src_fmt->fourcc =3D=3D V4L2_PIX_FMT_WEBP_FRAME) + vdpu_write_relaxed(vpu, + G1_REG_DEC_CTRL3_STREAM_LEN_EXT + (dct_part_total_len >> 24), + G1_REG_DEC_CTRL3); + /* DCT partitions base address */ for (i =3D 0; i < hdr->num_dct_parts; i++) { u32 byte_offset =3D dct_part_offset + dct_size_part_size + count; @@ -427,6 +433,12 @@ static void cfg_buffers(struct hantro_ctx *ctx, =20 dst_dma =3D hantro_get_dec_buf_addr(ctx, &vb2_dst->vb2_buf); vdpu_write_relaxed(vpu, dst_dma, G1_REG_ADDR_DST); + + if (ctx->vpu_src_fmt->fourcc =3D=3D V4L2_PIX_FMT_WEBP_FRAME) + vdpu_write_relaxed(vpu, dst_dma + + ctx->dst_fmt.plane_fmt[0].bytesperline * + ctx->dst_fmt.height, + G1_REG_ADDR_DST_CHROMA); } =20 int hantro_g1_vp8_dec_run(struct hantro_ctx *ctx) @@ -471,6 +483,8 @@ int hantro_g1_vp8_dec_run(struct hantro_ctx *ctx) reg |=3D G1_REG_DEC_CTRL0_SKIP_MODE; if (hdr->lf.level =3D=3D 0) reg |=3D G1_REG_DEC_CTRL0_FILTERING_DIS; + if (ctx->vpu_src_fmt->fourcc =3D=3D V4L2_PIX_FMT_WEBP_FRAME) + reg |=3D G1_REG_DEC_CTRL0_WEBP_E; vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL0); =20 /* Frame dimensions */ diff --git a/drivers/media/platform/verisilicon/hantro_v4l2.c b/drivers/med= ia/platform/verisilicon/hantro_v4l2.c index 2513adfbd825..7075b2ba1ec2 100644 --- a/drivers/media/platform/verisilicon/hantro_v4l2.c +++ b/drivers/media/platform/verisilicon/hantro_v4l2.c @@ -470,6 +470,7 @@ hantro_update_requires_request(struct hantro_ctx *ctx, = u32 fourcc) break; case V4L2_PIX_FMT_MPEG2_SLICE: case V4L2_PIX_FMT_VP8_FRAME: + case V4L2_PIX_FMT_WEBP_FRAME: case V4L2_PIX_FMT_H264_SLICE: case V4L2_PIX_FMT_HEVC_SLICE: case V4L2_PIX_FMT_VP9_FRAME: @@ -492,6 +493,7 @@ hantro_update_requires_hold_capture_buf(struct hantro_c= tx *ctx, u32 fourcc) case V4L2_PIX_FMT_JPEG: case V4L2_PIX_FMT_MPEG2_SLICE: case V4L2_PIX_FMT_VP8_FRAME: + case V4L2_PIX_FMT_WEBP_FRAME: case V4L2_PIX_FMT_HEVC_SLICE: case V4L2_PIX_FMT_VP9_FRAME: vq->subsystem_flags &=3D ~(VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF); diff --git a/drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c b/driver= s/media/platform/verisilicon/stm32mp25_vpu_hw.c index 833821120b20..c291b1560e20 100644 --- a/drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c +++ b/drivers/media/platform/verisilicon/stm32mp25_vpu_hw.c @@ -22,10 +22,10 @@ static const struct hantro_fmt stm32mp25_vdec_fmts[] = =3D { .codec_mode =3D HANTRO_MODE_NONE, .frmsize =3D { .min_width =3D FMT_MIN_WIDTH, - .max_width =3D FMT_FHD_WIDTH, + .max_width =3D FMT_4K_WIDTH, .step_width =3D MB_DIM, .min_height =3D FMT_MIN_HEIGHT, - .max_height =3D FMT_FHD_HEIGHT, + .max_height =3D FMT_4K_HEIGHT, .step_height =3D MB_DIM, }, }, @@ -42,6 +42,19 @@ static const struct hantro_fmt stm32mp25_vdec_fmts[] =3D= { .step_height =3D MB_DIM, }, }, + { + .fourcc =3D V4L2_PIX_FMT_WEBP_FRAME, + .codec_mode =3D HANTRO_MODE_VP8_DEC, + .max_depth =3D 2, + .frmsize =3D { + .min_width =3D FMT_MIN_WIDTH, + .max_width =3D FMT_4K_WIDTH, + .step_width =3D MB_DIM, + .min_height =3D FMT_MIN_HEIGHT, + .max_height =3D FMT_4K_HEIGHT, + .step_height =3D MB_DIM, + }, + }, { .fourcc =3D V4L2_PIX_FMT_H264_SLICE, .codec_mode =3D HANTRO_MODE_H264_DEC, --=20 2.25.1 From nobody Fri Nov 22 03:06:50 2024 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7484D1369B4; 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charset="utf-8" Support input larger than 4096x2048 using extended input width/height fields of swreg92. This is needed to decode large WebP or JPEG pictures. Signed-off-by: Hugues Fruchet --- drivers/media/platform/verisilicon/hantro.h | 2 ++ drivers/media/platform/verisilicon/hantro_g1_regs.h | 2 +- drivers/media/platform/verisilicon/hantro_postproc.c | 6 +++++- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/verisilicon/hantro.h b/drivers/media/pl= atform/verisilicon/hantro.h index 811260dc3c77..d1337f7742e4 100644 --- a/drivers/media/platform/verisilicon/hantro.h +++ b/drivers/media/platform/verisilicon/hantro.h @@ -321,6 +321,8 @@ struct hantro_postproc_regs { struct hantro_reg output_fmt; struct hantro_reg orig_width; struct hantro_reg display_width; + struct hantro_reg input_width_ext; + struct hantro_reg input_height_ext; }; =20 struct hantro_vp9_decoded_buffer_info { diff --git a/drivers/media/platform/verisilicon/hantro_g1_regs.h b/drivers/= media/platform/verisilicon/hantro_g1_regs.h index e7d4db788e57..f6e5bbeb1914 100644 --- a/drivers/media/platform/verisilicon/hantro_g1_regs.h +++ b/drivers/media/platform/verisilicon/hantro_g1_regs.h @@ -351,7 +351,7 @@ #define G1_REG_PP_CONTROL_OUT_WIDTH(v) (((v) << 4) & GENMASK(14, 4)) #define G1_REG_PP_MASK1_ORIG_WIDTH G1_SWREG(88) #define G1_REG_PP_ORIG_WIDTH(v) (((v) << 23) & GENMASK(31, 23)) -#define G1_REG_PP_DISPLAY_WIDTH G1_SWREG(92) +#define G1_REG_PP_DISPLAY_WIDTH_IN_EXT G1_SWREG(92) #define G1_REG_PP_FUSE G1_SWREG(99) =20 #endif /* HANTRO_G1_REGS_H_ */ diff --git a/drivers/media/platform/verisilicon/hantro_postproc.c b/drivers= /media/platform/verisilicon/hantro_postproc.c index 232c93eea7ee..84c8e287470d 100644 --- a/drivers/media/platform/verisilicon/hantro_postproc.c +++ b/drivers/media/platform/verisilicon/hantro_postproc.c @@ -49,7 +49,9 @@ static const struct hantro_postproc_regs hantro_g1_postpr= oc_regs =3D { .input_fmt =3D {G1_REG_PP_CONTROL, 29, 0x7}, .output_fmt =3D {G1_REG_PP_CONTROL, 26, 0x7}, .orig_width =3D {G1_REG_PP_MASK1_ORIG_WIDTH, 23, 0x1ff}, - .display_width =3D {G1_REG_PP_DISPLAY_WIDTH, 0, 0xfff}, + .display_width =3D {G1_REG_PP_DISPLAY_WIDTH_IN_EXT, 0, 0xfff}, + .input_width_ext =3D {G1_REG_PP_DISPLAY_WIDTH_IN_EXT, 26, 0x7}, + .input_height_ext =3D {G1_REG_PP_DISPLAY_WIDTH_IN_EXT, 29, 0x7}, }; =20 bool hantro_needs_postproc(const struct hantro_ctx *ctx, @@ -103,6 +105,8 @@ static void hantro_postproc_g1_enable(struct hantro_ctx= *ctx) HANTRO_PP_REG_WRITE(vpu, output_height, ctx->dst_fmt.height); HANTRO_PP_REG_WRITE(vpu, orig_width, MB_WIDTH(ctx->dst_fmt.width)); HANTRO_PP_REG_WRITE(vpu, display_width, ctx->dst_fmt.width); + HANTRO_PP_REG_WRITE(vpu, input_width_ext, MB_WIDTH(ctx->dst_fmt.width) >>= 9); + HANTRO_PP_REG_WRITE(vpu, input_height_ext, MB_HEIGHT(ctx->dst_fmt.height = >> 8)); } =20 static int down_scale_factor(struct hantro_ctx *ctx) --=20 2.25.1