From nobody Sat Nov 23 20:24:04 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8AB21D89E3; Thu, 21 Nov 2024 13:02:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732194126; cv=none; b=e8Zadh3b5xPd07Sh4XwGiuOyG52VIjT606UasBNmeFF/SPgtVJYRC7xsfM/wKco0U18p9dzURSVNziGJ/sgk3FFWHMV9X2IGBoHSLLlYXFDOcftHmrrN5r9uwdpiAEGOc4oYDmrlnZfdXyc/ApOtXQvckHGLwysVCGquF6hql7A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732194126; c=relaxed/simple; bh=MOye4Rv/CGaoopShXXmDC1S1nGm1R9L5HrCkKIMgdz8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=OFKdN/SXlyhnMndiXckzya0ZXTFd5MQbhuxy4NZv1GE8WgpOaS3jRy11wZMn2JUY6lFLwkg4KSIEP7e2NIGU7kgCemkPVxrrszf3QUAxyLWPLNirB2TG+nHw36HVNj5MAit2y9BlVyBCQqjEYIi9SyU/NS1lRY8XKbKGshsDXFc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=MCwLyuuy; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="MCwLyuuy" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4ALAYAb5028002; Thu, 21 Nov 2024 13:01:58 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-type:date:from:in-reply-to:message-id:mime-version :references:subject:to; s=qcppdkim1; bh=fcV24CP8p8ZKQbyl5/VFsxFA jZC6tzjZ4McjekVadAw=; b=MCwLyuuyl9RXTOujosvnYav2mHpDr6nyxaGPousX y7Z5p3YwV0E6l0KHNbmEdQl0uAwMHhTjuB0XOGe0btCFlA6IaOmExRhbuE3/ODuZ wxDoYos3Si0YoY+WrMq/TNw4Ag0kzU19yWk/ufvRcAV76dsjHGZMvvJNJhoXugsJ qmuurYr1e9najDzZ002wxAMY+Not6MSi6sdzfDkvlANY33mf8pQFR6gvpxFsw0u+ ZFTnwxBzZxzGy+weiKju0guhQc0zbGyVlsTUos+DqwuFM48RTAwVdnF5cWyppbqw nPnhkwJx0b9+mlpER0Tq9BhJ3JF9pBClKiuj/QgrK46WeQ== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 431ebybrj0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Nov 2024 13:01:58 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4ALD1v1J021441 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Nov 2024 13:01:57 GMT Received: from hu-jseerapu-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 21 Nov 2024 05:01:52 -0800 From: Jyothi Kumar Seerapu To: Vinod Koul , Andi Shyti , "Sumit Semwal" , =?UTF-8?q?Christian=20K=C3=B6nig?= CC: , , , , , , , , Subject: [PATCH v3 1/3] dmaengine: qcom: gpi: Add GPI Block event interrupt support Date: Thu, 21 Nov 2024 18:31:32 +0530 Message-ID: <20241121130134.29408-2-quic_jseerapu@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241121130134.29408-1-quic_jseerapu@quicinc.com> References: <20241121130134.29408-1-quic_jseerapu@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: AZurs0eNqLY67AGMlRLkGTQ5857_x39I X-Proofpoint-ORIG-GUID: AZurs0eNqLY67AGMlRLkGTQ5857_x39I X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 malwarescore=0 mlxlogscore=999 spamscore=0 mlxscore=0 phishscore=0 suspectscore=0 bulkscore=0 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411210102 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" GSI hardware generates an interrupt for each transfer completion. For multiple messages within a single transfer, this results in N interrupts for N messages, leading to significant software interrupt latency. To mitigate this latency, utilize Block Event Interrupt (BEI) mechanism. Enabling BEI instructs the GSI hardware to prevent interrupt generation and BEI is disabled when an interrupt is necessary. When using BEI, consider splitting a single multi-message transfer into chunks of 8 internally. Interrupts are not expected for the first 7 message completions, only the last message triggers an interrupt,indicating the completion of 8 messages. This BEI mechanism enhances overall transfer efficiency. Signed-off-by: Jyothi Kumar Seerapu --- v2-> v3: - Renamed gpi_multi_desc_process to gpi_multi_xfer_timeout_handler - MIN_NUM_OF_MSGS_MULTI_DESC changed from 4 to 2 - Added documentation for newly added changes in "qcom-gpi-dma.h" file - Updated commit description.=20 v1 -> v2: - Changed dma_addr type from array of pointers to array. - To support BEI functionality with the TRE size of 64 defined in GPI dr= iver, updated QCOM_GPI_MAX_NUM_MSGS to 16 and NUM_MSGS_PER_IRQ to 4. =20 drivers/dma/qcom/gpi.c | 48 ++++++++++++++++++++ include/linux/dma/qcom-gpi-dma.h | 76 ++++++++++++++++++++++++++++++++ 2 files changed, 124 insertions(+) diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c index 52a7c8f2498f..5442b65b1638 100644 --- a/drivers/dma/qcom/gpi.c +++ b/drivers/dma/qcom/gpi.c @@ -1693,6 +1693,9 @@ static int gpi_create_i2c_tre(struct gchan *chan, str= uct gpi_desc *desc, =20 tre->dword[3] =3D u32_encode_bits(TRE_TYPE_DMA, TRE_FLAGS_TYPE); tre->dword[3] |=3D u32_encode_bits(1, TRE_FLAGS_IEOT); + + if (i2c->flags & QCOM_GPI_BLOCK_EVENT_IRQ) + tre->dword[3] |=3D u32_encode_bits(1, TRE_FLAGS_BEI); } =20 for (i =3D 0; i < tre_idx; i++) @@ -2098,6 +2101,51 @@ static int gpi_find_avail_gpii(struct gpi_dev *gpi_d= ev, u32 seid) return -EIO; } =20 +/** + * gpi_multi_xfer_timeout_handler() - Handle multi message transfer timeout + * @dev: pointer to the corresponding dev node + * @multi_xfer: pointer to the gpi_multi_xfer + * @num_xfers: total number of transfers + * @transfer_timeout_msecs: transfer timeout value + * @transfer_comp: completion object of the transfer + * + * This function is used to wait for the processed transfers based on + * the interrupts generated upon transfer completion. + * Return: On success returns 0, otherwise return error code (-ETIMEDOUT) + */ +int gpi_multi_xfer_timeout_handler(struct device *dev, struct gpi_multi_xf= er *multi_xfer, + u32 num_xfers, u32 transfer_timeout_msecs, + struct completion *transfer_comp) +{ + int i; + u32 max_irq_cnt, time_left; + + max_irq_cnt =3D num_xfers / NUM_MSGS_PER_IRQ; + if (num_xfers % NUM_MSGS_PER_IRQ) + max_irq_cnt++; + + /* + * Wait for the interrupts of the processed transfers in multiple + * of 8 and for the last transfer. If the hardware is fast and + * already processed all the transfers then no need to wait. + */ + for (i =3D 0; i < max_irq_cnt; i++) { + reinit_completion(transfer_comp); + if (max_irq_cnt !=3D multi_xfer->irq_cnt) { + time_left =3D wait_for_completion_timeout(transfer_comp, + transfer_timeout_msecs); + if (!time_left) { + dev_err(dev, "%s: Transfer timeout\n", __func__); + return -ETIMEDOUT; + } + } + if (num_xfers > multi_xfer->msg_idx_cnt) + return 0; + } + return 0; +} +EXPORT_SYMBOL_GPL(gpi_multi_xfer_timeout_handler); + /* gpi_of_dma_xlate: open client requested channel */ static struct dma_chan *gpi_of_dma_xlate(struct of_phandle_args *args, struct of_dma *of_dma) diff --git a/include/linux/dma/qcom-gpi-dma.h b/include/linux/dma/qcom-gpi-= dma.h index 6680dd1a43c6..f001a8ac1887 100644 --- a/include/linux/dma/qcom-gpi-dma.h +++ b/include/linux/dma/qcom-gpi-dma.h @@ -15,6 +15,38 @@ enum spi_transfer_cmd { SPI_DUPLEX, }; =20 +/** + * define QCOM_GPI_BLOCK_EVENT_IRQ - Block event interrupt support + * + * This is used to enable/disable the Block event interrupt mechanism. + */ +#define QCOM_GPI_BLOCK_EVENT_IRQ BIT(0) + +/** + * define QCOM_GPI_MAX_NUM_MSGS - maximum number of messages support + * + * This indicates maximum number of messages can allocate and + * submit to hardware. To handle more messages beyond this, + * need to unmap the processed messages. + */ +#define QCOM_GPI_MAX_NUM_MSGS 16 + +/** + * define NUM_MSGS_PER_IRQ - interrupt per messages completion + * + * This indicates that trigger an interrupt, after the completion of 8 mes= sages. + */ +#define NUM_MSGS_PER_IRQ 8 + +/** + * define MIN_NUM_OF_MSGS_MULTI_DESC - \ + * minimum number of messages to support Block evenet interrupt + * + * This indicates minimum number of messages in a trenafer required to + * process it using block event interrupt mechanism. + */ +#define MIN_NUM_OF_MSGS_MULTI_DESC 2 + /** * struct gpi_spi_config - spi config for peripheral * @@ -51,6 +83,29 @@ enum i2c_op { I2C_READ, }; =20 +/** + * struct gpi_multi_xfer - Used for multi transfer support + * + * @msg_idx_cnt: message index for the transfer + * @buf_idx: dma buffer index + * @unmap_msg_cnt: unmapped transfer index + * @freed_msg_cnt: freed transfer index + * @irq_cnt: received interrupt count + * @irq_msg_cnt: transfer message count for the received irqs + * @dma_buf: virtual addresses of the buffers + * @dma_addr: dma addresses of the buffers + */ +struct gpi_multi_xfer { + u32 msg_idx_cnt; + u32 buf_idx; + u32 unmap_msg_cnt; + u32 freed_msg_cnt; + u32 irq_cnt; + u32 irq_msg_cnt; + void *dma_buf[QCOM_GPI_MAX_NUM_MSGS]; + dma_addr_t dma_addr[QCOM_GPI_MAX_NUM_MSGS]; +}; + /** * struct gpi_i2c_config - i2c config for peripheral * @@ -65,6 +120,8 @@ enum i2c_op { * @rx_len: receive length for buffer * @op: i2c cmd * @muli-msg: is part of multi i2c r-w msgs + * @flags: true for block event interrupt support + * @multi_xfer: indicates transfer has multi messages */ struct gpi_i2c_config { u8 set_config; @@ -78,6 +135,25 @@ struct gpi_i2c_config { u32 rx_len; enum i2c_op op; bool multi_msg; + u8 flags; + struct gpi_multi_xfer multi_xfer; }; =20 +/** + * gpi_multi_timeout_handler() - Handle multi message transfer timeout + * @dev: pointer to the corresponding dev node + * @multi_xfer: pointer to the gpi_multi_xfer + * @num_xfers: total number of transfers + * @transfer_timeout_msecs: transfer timeout value + * @transfer_comp: completion object of the transfer + * + * This function is used to wait for the processed transfers based on + * the interrupts generated upon transfer completion. + * + * Return: On success returns 0, otherwise return error code (-ETIMEDOUT) + */ +int gpi_multi_xfer_timeout_handler(struct device *dev, struct gpi_multi_xf= er *multi_xfer, + u32 num_xfers, u32 tranfer_timeout_msecs, + struct completion *transfer_comp); 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Thu, 21 Nov 2024 13:02:02 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4ALD22np019261 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Nov 2024 13:02:02 GMT Received: from hu-jseerapu-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 21 Nov 2024 05:01:57 -0800 From: Jyothi Kumar Seerapu To: Vinod Koul , Andi Shyti , "Sumit Semwal" , =?UTF-8?q?Christian=20K=C3=B6nig?= CC: , , , , , , , , Subject: [PATCH v3 2/3] i2c: i2c-qcom-geni: Add Block event interrupt support Date: Thu, 21 Nov 2024 18:31:33 +0530 Message-ID: <20241121130134.29408-3-quic_jseerapu@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241121130134.29408-1-quic_jseerapu@quicinc.com> References: <20241121130134.29408-1-quic_jseerapu@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: agbUgBlmkki76Ot8EdnrNmkiAv3oSWmH X-Proofpoint-ORIG-GUID: agbUgBlmkki76Ot8EdnrNmkiAv3oSWmH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 bulkscore=0 mlxscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 malwarescore=0 mlxlogscore=999 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411210102 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The I2C driver gets an interrupt upon transfer completion. When handling multiple messages in a single transfer, this results in N interrupts for N messages, leading to significant software interrupt latency. To mitigate this latency, utilize Block Event Interrupt (BEI) mechanism. Enabling BEI instructs the hardware to prevent interrupt generation and BEI is disabled when an interrupt is necessary. Large I2C transfer can be divided into chunks of 8 messages internally. Interrupts are not expected for the first 7 message completions, only the last message triggers an interrupt, indicating the completion of 8 messages. This BEI mechanism enhances overall transfer efficiency. This optimization reduces transfer time from 168 ms to 48 ms for a series of 200 I2C write messages in a single transfer, with a clock frequency support of 100 kHz. BEI optimizations are currently implemented for I2C write transfers only, as there is no use case for multiple I2C read messages in a single transfer at this time. Signed-off-by: Jyothi Kumar Seerapu --- v2 -> v3: - In i2c_gpi_cb_result function, moved the logic of "!is_tx_multi_xfer" to else. - MIN_NUM_OF_MSGS_MULTI_DESC changed from 4 to 2 - Updated commit description v1 -> v2: - Moved gi2c_gpi_xfer->msg_idx_cnt to separate local variable. - Updated goto labels for error scenarios in geni_i2c_gpi function - memset tx_multi_xfer to 0. - Removed passing current msg index to geni_i2c_gpi - Fixed kernel test robot reported compilation issues. drivers/i2c/busses/i2c-qcom-geni.c | 203 +++++++++++++++++++++++++---- 1 file changed, 178 insertions(+), 25 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qc= om-geni.c index 7a22e1f46e60..2b5fe6e4ed45 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -100,6 +100,10 @@ struct geni_i2c_dev { struct dma_chan *rx_c; bool gpi_mode; bool abort_done; + bool is_tx_multi_xfer; + u32 num_msgs; + u32 tx_irq_cnt; + struct gpi_i2c_config *gpi_config; }; =20 struct geni_i2c_desc { @@ -500,6 +504,7 @@ static int geni_i2c_tx_one_msg(struct geni_i2c_dev *gi2= c, struct i2c_msg *msg, static void i2c_gpi_cb_result(void *cb, const struct dmaengine_result *res= ult) { struct geni_i2c_dev *gi2c =3D cb; + struct gpi_multi_xfer *tx_multi_xfer; =20 if (result->result !=3D DMA_TRANS_NOERROR) { dev_err(gi2c->se.dev, "DMA txn failed:%d\n", result->result); @@ -508,7 +513,21 @@ static void i2c_gpi_cb_result(void *cb, const struct d= maengine_result *result) dev_dbg(gi2c->se.dev, "DMA xfer has pending: %d\n", result->residue); } =20 - complete(&gi2c->done); + if (!gi2c->is_tx_multi_xfer) { + complete(&gi2c->done); + } else { + tx_multi_xfer =3D &gi2c->gpi_config->multi_xfer; + + /* + * Send Completion for last message or multiple of NUM_MSGS_PER_IRQ. + */ + if ((tx_multi_xfer->irq_msg_cnt =3D=3D gi2c->num_msgs - 1) || + (!((tx_multi_xfer->irq_msg_cnt + 1) % NUM_MSGS_PER_IRQ))) { + tx_multi_xfer->irq_cnt++; + complete(&gi2c->done); + } + tx_multi_xfer->irq_msg_cnt++; + } } =20 static void geni_i2c_gpi_unmap(struct geni_i2c_dev *gi2c, struct i2c_msg *= msg, @@ -526,7 +545,42 @@ static void geni_i2c_gpi_unmap(struct geni_i2c_dev *gi= 2c, struct i2c_msg *msg, } } =20 -static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, +/** + * gpi_i2c_multi_desc_unmap() - unmaps the buffers post multi message TX t= ransfers + * @dev: pointer to the corresponding dev node + * @gi2c: i2c dev handle + * @msgs: i2c messages array + * @peripheral: pointer to the gpi_i2c_config + */ +static void gpi_i2c_multi_desc_unmap(struct geni_i2c_dev *gi2c, struct i2c= _msg msgs[], + struct gpi_i2c_config *peripheral) +{ + u32 msg_xfer_cnt, wr_idx =3D 0; + struct gpi_multi_xfer *tx_multi_xfer =3D &peripheral->multi_xfer; + + /* + * In error case, need to unmap all messages based on the msg_idx_cnt. + * Non-error case unmap all the processed messages. + */ + if (gi2c->err) + msg_xfer_cnt =3D tx_multi_xfer->msg_idx_cnt; + else + msg_xfer_cnt =3D tx_multi_xfer->irq_cnt * NUM_MSGS_PER_IRQ; + + /* Unmap the processed DMA buffers based on the received interrupt count = */ + for (; tx_multi_xfer->unmap_msg_cnt < msg_xfer_cnt; tx_multi_xfer->unmap_= msg_cnt++) { + if (tx_multi_xfer->unmap_msg_cnt =3D=3D gi2c->num_msgs) + break; + wr_idx =3D tx_multi_xfer->unmap_msg_cnt % QCOM_GPI_MAX_NUM_MSGS; + geni_i2c_gpi_unmap(gi2c, &msgs[tx_multi_xfer->unmap_msg_cnt], + tx_multi_xfer->dma_buf[wr_idx], + tx_multi_xfer->dma_addr[wr_idx], + NULL, (dma_addr_t)NULL); + tx_multi_xfer->freed_msg_cnt++; + } +} + +static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], struct dma_slave_config *config, dma_addr_t *dma_addr_p, void **buf, unsigned int op, struct dma_chan *dma_chan) { @@ -538,26 +592,48 @@ static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, st= ruct i2c_msg *msg, enum dma_transfer_direction dma_dirn; struct dma_async_tx_descriptor *desc; int ret; + struct gpi_multi_xfer *gi2c_gpi_xfer; + dma_cookie_t cookie; + u32 msg_idx; =20 peripheral =3D config->peripheral_config; - - dma_buf =3D i2c_get_dma_safe_msg_buf(msg, 1); - if (!dma_buf) - return -ENOMEM; + gi2c_gpi_xfer =3D &peripheral->multi_xfer; + dma_buf =3D gi2c_gpi_xfer->dma_buf[gi2c_gpi_xfer->buf_idx]; + addr =3D gi2c_gpi_xfer->dma_addr[gi2c_gpi_xfer->buf_idx]; + msg_idx =3D gi2c_gpi_xfer->msg_idx_cnt; + + dma_buf =3D i2c_get_dma_safe_msg_buf(&msgs[msg_idx], 1); + if (!dma_buf) { + ret =3D -ENOMEM; + goto out; + } =20 if (op =3D=3D I2C_WRITE) map_dirn =3D DMA_TO_DEVICE; else map_dirn =3D DMA_FROM_DEVICE; =20 - addr =3D dma_map_single(gi2c->se.dev->parent, dma_buf, msg->len, map_dirn= ); + addr =3D dma_map_single(gi2c->se.dev->parent, dma_buf, + msgs[msg_idx].len, map_dirn); if (dma_mapping_error(gi2c->se.dev->parent, addr)) { - i2c_put_dma_safe_msg_buf(dma_buf, msg, false); - return -ENOMEM; + i2c_put_dma_safe_msg_buf(dma_buf, &msgs[msg_idx], false); + ret =3D -ENOMEM; + goto out; + } + + if (gi2c->is_tx_multi_xfer) { + if (((msg_idx + 1) % NUM_MSGS_PER_IRQ)) + peripheral->flags |=3D QCOM_GPI_BLOCK_EVENT_IRQ; + else + peripheral->flags &=3D ~QCOM_GPI_BLOCK_EVENT_IRQ; + + /* BEI bit to be cleared for last TRE */ + if (msg_idx =3D=3D gi2c->num_msgs - 1) + peripheral->flags &=3D ~QCOM_GPI_BLOCK_EVENT_IRQ; } =20 /* set the length as message for rx txn */ - peripheral->rx_len =3D msg->len; + peripheral->rx_len =3D msgs[msg_idx].len; peripheral->op =3D op; =20 ret =3D dmaengine_slave_config(dma_chan, config); @@ -575,7 +651,8 @@ static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, stru= ct i2c_msg *msg, else dma_dirn =3D DMA_DEV_TO_MEM; =20 - desc =3D dmaengine_prep_slave_single(dma_chan, addr, msg->len, dma_dirn, = flags); + desc =3D dmaengine_prep_slave_single(dma_chan, addr, msgs[msg_idx].len, + dma_dirn, flags); if (!desc) { dev_err(gi2c->se.dev, "prep_slave_sg failed\n"); ret =3D -EIO; @@ -585,15 +662,48 @@ static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, st= ruct i2c_msg *msg, desc->callback_result =3D i2c_gpi_cb_result; desc->callback_param =3D gi2c; =20 - dmaengine_submit(desc); - *buf =3D dma_buf; - *dma_addr_p =3D addr; + if (!((msgs[msg_idx].flags & I2C_M_RD) && op =3D=3D I2C_WRITE)) { + gi2c_gpi_xfer->msg_idx_cnt++; + gi2c_gpi_xfer->buf_idx =3D (msg_idx + 1) % QCOM_GPI_MAX_NUM_MSGS; + } + cookie =3D dmaengine_submit(desc); + if (dma_submit_error(cookie)) { + dev_err(gi2c->se.dev, + "%s: dmaengine_submit failed (%d)\n", __func__, cookie); + ret =3D -EINVAL; + goto err_config; + } =20 + if (gi2c->is_tx_multi_xfer) { + dma_async_issue_pending(gi2c->tx_c); + if ((msg_idx =3D=3D (gi2c->num_msgs - 1)) || + (gi2c_gpi_xfer->msg_idx_cnt >=3D + QCOM_GPI_MAX_NUM_MSGS + gi2c_gpi_xfer->freed_msg_cnt)) { + ret =3D gpi_multi_xfer_timeout_handler(gi2c->se.dev, gi2c_gpi_xfer, + gi2c->num_msgs, XFER_TIMEOUT, + &gi2c->done); + if (ret) { + dev_err(gi2c->se.dev, + "I2C multi write msg transfer timeout: %d\n", + ret); + gi2c->err =3D ret; + goto err_config; + } + } + } else { + /* Non multi descriptor message transfer */ + *buf =3D dma_buf; + *dma_addr_p =3D addr; + } return 0; =20 err_config: - dma_unmap_single(gi2c->se.dev->parent, addr, msg->len, map_dirn); - i2c_put_dma_safe_msg_buf(dma_buf, msg, false); + dma_unmap_single(gi2c->se.dev->parent, addr, + msgs[msg_idx].len, map_dirn); + i2c_put_dma_safe_msg_buf(dma_buf, &msgs[msg_idx], false); + +out: + gi2c->err =3D ret; return ret; } =20 @@ -605,6 +715,7 @@ static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c,= struct i2c_msg msgs[], i unsigned long time_left; dma_addr_t tx_addr, rx_addr; void *tx_buf =3D NULL, *rx_buf =3D NULL; + struct gpi_multi_xfer *tx_multi_xfer; const struct geni_i2c_clk_fld *itr =3D gi2c->clk_fld; =20 config.peripheral_config =3D &peripheral; @@ -618,6 +729,34 @@ static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c= , struct i2c_msg msgs[], i peripheral.set_config =3D 1; peripheral.multi_msg =3D false; =20 + gi2c->gpi_config =3D &peripheral; + gi2c->num_msgs =3D num; + gi2c->is_tx_multi_xfer =3D false; + gi2c->tx_irq_cnt =3D 0; + + tx_multi_xfer =3D &peripheral.multi_xfer; + memset(tx_multi_xfer, 0, sizeof(struct gpi_multi_xfer)); + + /* + * If number of write messages are two and higher then + * configure hardware for multi descriptor transfers with BEI. + */ + if (num >=3D MIN_NUM_OF_MSGS_MULTI_DESC) { + gi2c->is_tx_multi_xfer =3D true; + for (i =3D 0; i < num; i++) { + if (msgs[i].flags & I2C_M_RD) { + /* + * Multi descriptor transfer with BEI + * support is enabled for write transfers. + * TODO: Add BEI optimization support for + * read transfers later. + */ + gi2c->is_tx_multi_xfer =3D false; + break; + } + } + } + for (i =3D 0; i < num; i++) { gi2c->cur =3D &msgs[i]; gi2c->err =3D 0; @@ -628,14 +767,16 @@ static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2= c, struct i2c_msg msgs[], i peripheral.stretch =3D 1; =20 peripheral.addr =3D msgs[i].addr; + if (i > 0 && (!(msgs[i].flags & I2C_M_RD))) + peripheral.multi_msg =3D false; =20 - ret =3D geni_i2c_gpi(gi2c, &msgs[i], &config, + ret =3D geni_i2c_gpi(gi2c, msgs, &config, &tx_addr, &tx_buf, I2C_WRITE, gi2c->tx_c); if (ret) goto err; =20 if (msgs[i].flags & I2C_M_RD) { - ret =3D geni_i2c_gpi(gi2c, &msgs[i], &config, + ret =3D geni_i2c_gpi(gi2c, msgs, &config, &rx_addr, &rx_buf, I2C_READ, gi2c->rx_c); if (ret) goto err; @@ -643,18 +784,26 @@ static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2= c, struct i2c_msg msgs[], i dma_async_issue_pending(gi2c->rx_c); } =20 - dma_async_issue_pending(gi2c->tx_c); - - time_left =3D wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); - if (!time_left) - gi2c->err =3D -ETIMEDOUT; + if (!gi2c->is_tx_multi_xfer) { + dma_async_issue_pending(gi2c->tx_c); + time_left =3D wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); + if (!time_left) { + dev_err(gi2c->se.dev, "%s:I2C timeout\n", __func__); + gi2c->err =3D -ETIMEDOUT; + } + } =20 if (gi2c->err) { ret =3D gi2c->err; goto err; } =20 - geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr); + if (!gi2c->is_tx_multi_xfer) { + geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr); + } else if (gi2c->tx_irq_cnt !=3D tx_multi_xfer->irq_cnt) { + gi2c->tx_irq_cnt =3D tx_multi_xfer->irq_cnt; + gpi_i2c_multi_desc_unmap(gi2c, msgs, &peripheral); + } } =20 return num; @@ -663,7 +812,11 @@ static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c= , struct i2c_msg msgs[], i dev_err(gi2c->se.dev, "GPI transfer failed: %d\n", ret); dmaengine_terminate_sync(gi2c->rx_c); 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charset="utf-8" I2C functionality has dependencies on the GPI driver. Ensure that the GPI driver is enabled when using the I2C driver functionality. Therefore, update the I2C GENI driver to depend on the GPI driver. Signed-off-by: Jyothi Kumar Seerapu --- v2 -> v3: - Moved this change to patch3. - Updated commit description. v1 -> v2: - This patch is added in v2 to address the kernel test robot reported compilation error. ERROR: modpost: "gpi_multi_desc_process" [drivers/i2c/busses/i2c-qcom= -geni.ko] undefined! drivers/i2c/busses/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 0aa948014008..87634a682855 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -1049,6 +1049,7 @@ config I2C_QCOM_GENI tristate "Qualcomm Technologies Inc.'s GENI based I2C controller" depends on ARCH_QCOM || COMPILE_TEST depends on QCOM_GENI_SE + depends on QCOM_GPI_DMA help This driver supports GENI serial engine based I2C controller in master mode on the Qualcomm Technologies Inc.'s SoCs. If you say --=20 2.17.1