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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Nov 2024 11:35:17.5311 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 990e53de-efe3-474a-e2bf-08dd0a2092e5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.12];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6245 Content-Type: text/plain; charset="utf-8" Add clock-output-names property to all clock nodes, so that the resulting clock name do not change when clock node name is changed. Signed-off-by: Naman Trivedi --- arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/bo= ot/dts/xilinx/zynqmp-clk-ccf.dtsi index 60d1b1acf9a0..a231122002da 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -15,6 +15,7 @@ pss_ref_clk: pss_ref_clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; clock-frequency =3D <33333333>; + clock-output-names =3D "pss_ref_clk"; }; =20 video_clk: video_clk { @@ -22,6 +23,7 @@ video_clk: video_clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; clock-frequency =3D <27000000>; + clock-output-names =3D "video_clk"; }; =20 pss_alt_ref_clk: pss_alt_ref_clk { @@ -29,6 +31,7 @@ pss_alt_ref_clk: pss_alt_ref_clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; clock-frequency =3D <0>; + clock-output-names =3D "pss_alt_ref_clk"; }; =20 gt_crx_ref_clk: gt_crx_ref_clk { @@ -36,6 +39,7 @@ gt_crx_ref_clk: gt_crx_ref_clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; clock-frequency =3D <108000000>; + clock-output-names =3D "gt_crx_ref_clk"; }; =20 aux_ref_clk: aux_ref_clk { @@ -43,6 +47,7 @@ aux_ref_clk: aux_ref_clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; clock-frequency =3D <27000000>; + clock-output-names =3D "aux_ref_clk"; }; }; =20 --=20 2.25.1