From nobody Sat Nov 23 08:15:58 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC8B21CACC4; Thu, 21 Nov 2024 06:30:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732170631; cv=none; b=OGMdMbnJ8lFT0yqPsc6/gGNDvX7twrSDer4tSfwB2LY0PRsNDoAhVhOqTjvInQLsRr/JPTpWvhg/MdMc1/ixQ/R8a6Yr4QqvQOM9n0uYX5JS12h1JLSME8x76ZI4XUgMh6EDo9bgTcvDC8yG8JPMRRpv5BZoUlxW5hKVkblEFxo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732170631; c=relaxed/simple; bh=xPW90rSH8SmQPKAHOF3uVuJXGHvRIMhzWjyarRgRb1g=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Rr4UFnMW2v5CYLWxPVrDyCAMULqZgZh3i16+m0VSPSmElTDtSZZWp5AbOAUYK613m8KA12m5BZmkuObMAT0RLpoPqyePbnTJmQ451aGVU2TV8FS4tv2QC0ZNlA2V6W0B3nR+JCI/eHGvJTQWqWMk9vW7ZC0mWduVyjdgMP00YuM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=LoYXqAI1; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="LoYXqAI1" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4AL19R8w026150; Thu, 21 Nov 2024 06:30:26 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= xUtuV66OurLDWje165mF4ykr1LimvZhEUVbVE33+9OU=; b=LoYXqAI1sPG7X7oM jQ3hxcltnhoYSSucXNPNW5A/NQky1Sp1qXoyvJzhPYMHii/AEkVmmvm8+foFznPl 7ftMuziEdyoHr+bpjViZUkr7Jfqq5DOgGU7ZPDNDN/JMpMXZ3sDRtRoiET1hbesu Cx1WftQhvhmaB3X/I492EA3jxvqXSAUam75TwbGNFnag6CDKECeK8K1S94e9AYwU mm+d7GQoMwiRJlQTg8Vq+SIXEDm+9aUf8h18ysESsEOwwGR2tcCfESOfOXGgynXR gXE8j1EPGjeJVVrdwWhPmKMFwN6JOHF8lzaLg13FxYej6KLfPpDaX0kQKXqSsC3L 0c02Og== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 431ebyakxt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Nov 2024 06:30:26 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AL6UPSd027336 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Nov 2024 06:30:25 GMT Received: from hu-kriskura-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 20 Nov 2024 22:30:21 -0800 From: Krishna Kurapati To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: , , , , , Krishna Kurapati Subject: [PATCH v2 1/2] arm64: dts: qcom: Add support for usb node on QCS615 Date: Thu, 21 Nov 2024 12:00:06 +0530 Message-ID: <20241121063007.2737908-2-quic_kriskura@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241121063007.2737908-1-quic_kriskura@quicinc.com> References: <20241121063007.2737908-1-quic_kriskura@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: FsQ6VPZIfjFUG_osIKY3AnIjLA0S4tCE X-Proofpoint-ORIG-GUID: FsQ6VPZIfjFUG_osIKY3AnIjLA0S4tCE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 malwarescore=0 mlxlogscore=999 spamscore=0 mlxscore=0 phishscore=0 suspectscore=0 bulkscore=0 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411210048 Content-Type: text/plain; charset="utf-8" Add support for primary USB controller and its PHYs on QCS615. Signed-off-by: Krishna Kurapati Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 110 +++++++++++++++++++++++++++ 1 file changed, 110 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qco= m/qcs615.dtsi index 590beb37f441..d5c14c067ad6 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -397,6 +397,11 @@ qfprom: efuse@780000 { reg =3D <0x0 0x00780000 0x0 0x7000>; #address-cells =3D <1>; #size-cells =3D <1>; + + qusb2_hstx_trim: hstx-trim@1f8 { + reg =3D <0x1fb 0x1>; + bits =3D <1 4>; + }; }; =20 qupv3_id_0: geniqup@8c0000 { @@ -758,6 +763,111 @@ rpmhpd_opp_turbo_l1: opp-9 { }; }; }; + + usb_1_hsphy: phy@88e2000 { + compatible =3D "qcom,qcs615-qusb2-phy"; + reg =3D <0x0 0x88e2000 0x0 0x180>; + + clocks =3D <&gcc GCC_AHB2PHY_WEST_CLK>, <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "cfg_ahb", "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_PRIM_BCR>; + nvmem-cells =3D <&qusb2_hstx_trim>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_qmpphy: phy@88e6000 { + compatible =3D "qcom,qcs615-qmp-usb3-phy"; + reg =3D <0x0 0x88e6000 0x0 0x1000>; + + clocks =3D <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_AHB2PHY_WEST_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names =3D "aux", + "ref", + "cfg_ahb", + "pipe"; + + resets =3D <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; + reset-names =3D "phy", "phy_phy"; + + qcom,tcsr-reg =3D <&tcsr 0xb244>; + + clock-output-names =3D "usb3_phy_pipe_clk_src"; + #clock-cells =3D <0>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_1: usb@a6f8800 { + compatible =3D "qcom,qcs615-dwc3", "qcom,dwc3"; + reg =3D <0x0 0x0a6f8800 0x0 0x400>; + + clocks =3D <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks =3D <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates =3D <19200000>, <200000000>; + + interrupts-extended =3D <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 9 IRQ_TYPE_EDGE_BOTH>, + <&pdc 8 IRQ_TYPE_EDGE_BOTH>, + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains =3D <&gcc USB30_PRIM_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + resets =3D <&gcc GCC_USB30_PRIM_BCR>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + usb_1_dwc3: usb@a600000 { + compatible =3D "snps,dwc3"; + reg =3D <0x0 0x0a600000 0x0 0xcd00>; + + iommus =3D <&apps_smmu 0x140 0x0>; + interrupts =3D ; + + phys =3D <&usb_1_hsphy>, <&usb_qmpphy>; + phy-names =3D "usb2-phy", "usb3-phy"; + + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold =3D /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + }; + }; }; =20 arch_timer: timer { --=20 2.34.1 From nobody Sat Nov 23 08:15:58 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03B613DBB6; Thu, 21 Nov 2024 06:30:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732170635; cv=none; b=RinFQRn3IMmSjtLOkGizankjfb++FFvr+ywwhVBwH6dmG6y1zz491W8/WB4sPPZ4+6GH+aOMIAYEpAIU0OODWvwZVnlgdaSG6fw2M9KNHuWbleqSGm8hNz4FLvP/71Ihz7QZyfAeo0DcoS/u08tomOBlRMYEHR5B2iueutvjKYs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732170635; c=relaxed/simple; bh=r+qhFA10uVrKLXTgaNirInIM4wph+0aTAGpHG36K6WI=; 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charset="utf-8" Enable primary USB controller on QCS615 Ride platform. The primary USB controller is made "peripheral", as this is intended to be connected to a host for debugging use cases. For using the controller in host mode, changing the dr_mode and adding appropriate pinctrl nodes to provide vbus would be sufficient. Signed-off-by: Krishna Kurapati Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts= /qcom/qcs615-ride.dts index ee6cab3924a6..a25928933e2b 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -214,6 +214,29 @@ &uart0 { status =3D "okay"; }; =20 +&usb_1_hsphy { + vdd-supply =3D <&vreg_l5a>; + vdda-pll-supply =3D <&vreg_l12a>; + vdda-phy-dpdm-supply =3D <&vreg_l13a>; + + status =3D "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply =3D <&vreg_l5a>; + vdda-pll-supply =3D <&vreg_l12a>; + + status =3D "okay"; +}; + +&usb_1 { + status =3D "okay"; +}; + +&usb_1_dwc3 { + dr_mode =3D "peripheral"; +}; + &watchdog { clocks =3D <&sleep_clk>; }; --=20 2.34.1