From nobody Sun Nov 24 05:51:41 2024 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56EEE1C9DC9 for ; Thu, 21 Nov 2024 08:53:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732179203; cv=none; b=Sl/Ei5rkZ2RSANgYwf9BdpCqBCzn2pgK8ruEfWK26V65acBnPpJJzHhqt8fh0vOveSlWj1WqrLTpRikQ92ET802+rsJmgYdVqZD6RTl3GnfUAkldWhWzDJHAAocr6SsHxbEcjediaIWJxpJXQqsJ0p7V4D5YoiHq0fAvn1wNcRU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732179203; c=relaxed/simple; bh=0rkB4/JpaPliiwIivH9y29TzVUpUltIbQ7I+cmLdwJ8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GwH06mLnGeSnZ9PI6l567XoAliq5mgOfJQtSs1bCuub7GdgujRxYJj9rlN10HN4eu9cSyPuBTRB10nvap5qSI5CWQQFL7u7rBRYhP3eiTbkfE4/9Hkma4mWu5mY1oHrQWpiS+qQZBiyRc/lOhOLZyUSvVkxbUR9JEid+YgoPsOU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=2SWW/CPf; arc=none smtp.client-ip=209.85.221.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="2SWW/CPf" Received: by mail-wr1-f49.google.com with SMTP id ffacd0b85a97d-37ed3bd6114so374546f8f.2 for ; Thu, 21 Nov 2024 00:53:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1732179198; x=1732783998; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=5MCyWyyuLRYxP0oH9ltkOsqfvK0CBscNjWxECImzBCc=; b=2SWW/CPfWhoYVi1cSbqP5KTtPiWS3Oru45+H2ENNxMQBTPf+9SMs4m+dRpk66OnLQO E6NNH4WHU6F9XdnpqbIstrWHyqXxfYRFF1wF4syoWYd1CC/GwZYUQqN3oCIIcITO3bln 5C/2sHAyTB9ImDKb/OAPevbEasPWDgM7nBBkmaX7O0e1pwRhcOV5PJIIXMcX/n8Zgdk8 Xr/8mdVb3wcie4616WY8CaC9iMQnbLTmFurOVYumtdV4aV0eGSqw78SWwcvYuzh78YXo l0vpgrIgfqmZ/GkHI3yYXo+krBC/eMX6ij/BRV2kPNVYo8juqh4IVhkNmKrjd00aLiTj mU5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732179198; x=1732783998; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5MCyWyyuLRYxP0oH9ltkOsqfvK0CBscNjWxECImzBCc=; b=bwxgKFC5MUweIor45nx3hPR8llNwewR2jwULBCTG+VkUwtTRbMPX5qaUSg5O+Is9rC sH2M9q1kd/jAIx6y28v+oXUVlbuNzCeC2BvApuw9+k28fW287h/AjV6CdwAhoIdbNaWO cOhFZHxmwkY85qFrv1QtTJyapdKVwlJtHNxQUcv/3Tiju1tom5UEnbcHwVpvXQpDme96 ag0PMuYfaAxmS4dGlm/UmIVIDBlE60ESCwmgIkZl689TfAaJFIlSbS/AhFB46DNP80UR hCPClucIyIvBL2XBS0FoNKfr+50s54VEUYSM7jxX0/jddhqhMylSEtvVhWLuxaUMVuaS Yl9A== X-Forwarded-Encrypted: i=1; AJvYcCUXNNiq0ogZFnnBuhd71gEr+Ds/hGFUXtgepPsRPvA+XTqdjnWdqqEfAnjJagAvFyMI3XjV7aLi8cBeKak=@vger.kernel.org X-Gm-Message-State: AOJu0YydK82L9ONNxD4lU/gXHF7MvXSwGO8WmMKmpj1hjk5alplnOREU 8q70VmlipHHsZqRj67OIa9dNyES/0CbzwSNspMV+xpBA3hCK5SI1b0M3DB9tM24= X-Gm-Gg: ASbGncsxPI4ZU0GHX1RHFFFfMpxx6wwjhAqRDf1MqJOWo+k7s3k6OjSweGgWAwKBFGs TPFFxb2y4M1pArZNVnN91xwse4Hm79JjIY3LSndkMFNnw1aPImm6PITCDrOXFAmYfrxoZrlI1Xy BsCKhEBq2zEXy5sKFdI3VSPhWk2DRh4vmRh289v5CsdmvTI9M6wRXvH7SfwjqJvdmry6NIX1g+V 7iNDlM2QRL+9HEXwnUuU5Asm1bq5RFRRQsquUqGIJYC1EmiYxY+PprLIKwjU2kJF80dSBTuTRLe sq1/1jSx2Hy8V8XCPH+zx2qdzNL+rI/zOW5mDjqUZqw= X-Google-Smtp-Source: AGHT+IEMIkoLdPBEX/9Nv5t80VVjflIxCN9/zIPP7NEINBt57fCC+7zzZNTiyW6G4qkMw3XegNJTaQ== X-Received: by 2002:a5d:5985:0:b0:382:4a80:a616 with SMTP id ffacd0b85a97d-38254ae0006mr4981983f8f.9.1732179197597; Thu, 21 Nov 2024 00:53:17 -0800 (PST) Received: from [192.168.42.0] (2a02-842a-d52e-6101-6fd0-06c4-5d68-f0a5.rev.sfr.net. [2a02:842a:d52e:6101:6fd0:6c4:5d68:f0a5]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-382549111fdsm4219900f8f.58.2024.11.21.00.53.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2024 00:53:17 -0800 (PST) From: Julien Stephan Date: Thu, 21 Nov 2024 09:53:15 +0100 Subject: [PATCH v7 1/5] dt-bindings: media: add mediatek ISP3.0 sensor interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241121-add-mtk-isp-3-0-support-v7-1-b04dc9610619@baylibre.com> References: <20241121-add-mtk-isp-3-0-support-v7-0-b04dc9610619@baylibre.com> In-Reply-To: <20241121-add-mtk-isp-3-0-support-v7-0-b04dc9610619@baylibre.com> To: Laurent Pinchart , Andy Hsieh , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Julien Stephan , Louis Kuo , Phi-Bang Nguyen X-Mailer: b4 0.14.2 From: Louis Kuo This adds the bindings, for the mediatek ISP3.0 SENINF module embedded in some Mediatek SoC, such as the mt8365 Signed-off-by: Louis Kuo Signed-off-by: Phi-Bang Nguyen Signed-off-by: Laurent Pinchart Reviewed-by: Laurent Pinchart Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring (Arm) Signed-off-by: Julien Stephan --- .../bindings/media/mediatek,mt8365-seninf.yaml | 259 +++++++++++++++++= ++++ MAINTAINERS | 7 + 2 files changed, 266 insertions(+) diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8365-seninf= .yaml b/Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml new file mode 100644 index 0000000000000000000000000000000000000000..8bd78ef424acf1ec207b527b4a8= 4b6a535f37593 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml @@ -0,0 +1,259 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2023 MediaTek, BayLibre +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mt8365-seninf.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Sensor Interface 3.0 + +maintainers: + - Laurent Pinchart + - Julien Stephan + - Andy Hsieh + +description: + The ISP3.0 SENINF is the CSI-2 and parallel camera sensor interface foun= d in + multiple MediaTek SoCs. It can support up to three physical CSI-2 input = ports, + configured in DPHY (2 or 4 data lanes) or CPHY depending on the SoC. + On the output side, SENINF can be connected either to CAMSV instance or + to the internal ISP. CAMSV is used to bypass the internal ISP processing + in order to connect either an external ISP, or a sensor (RAW, YUV). + +properties: + compatible: + const: mediatek,mt8365-seninf + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + items: + - description: Seninf camsys clock + - description: Seninf top mux clock + + clock-names: + items: + - const: camsys + - const: top_mux + + phys: + minItems: 2 + maxItems: 2 + description: + phandle to the PHYs connected to CSI0/A, CSI1, CSI0B + + phy-names: + description: + list of PHYs names + minItems: 2 + maxItems: 2 + items: + enum: [ csi0, csi1, csi0b] + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI0 or CSI0A port + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + data-lanes: + minItems: 1 + maxItems: 4 + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI1 port + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + data-lanes: + minItems: 1 + maxItems: 4 + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI2 port + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + data-lanes: + minItems: 1 + maxItems: 4 + + port@3: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: CSI0B port + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + data-lanes: + minItems: 1 + maxItems: 2 + + port@4: + $ref: /schemas/graph.yaml#/properties/port + description: connection point for cam0 + + port@5: + $ref: /schemas/graph.yaml#/properties/port + description: connection point for cam1 + + port@6: + $ref: /schemas/graph.yaml#/properties/port + description: connection point for camsv0 + + port@7: + $ref: /schemas/graph.yaml#/properties/port + description: connection point for camsv1 + + port@8: + $ref: /schemas/graph.yaml#/properties/port + description: connection point for camsv2 + + port@9: + $ref: /schemas/graph.yaml#/properties/port + description: connection point for camsv3 + + required: + - port@0 + - port@1 + - port@2 + - port@3 + - port@4 + - port@5 + - port@6 + - port@7 + - port@8 + - port@9 + +required: + - compatible + - interrupts + - clocks + - clock-names + - power-domains + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + csi@15040000 { + compatible =3D "mediatek,mt8365-seninf"; + reg =3D <0 0x15040000 0 0x6000>; + interrupts =3D ; + clocks =3D <&camsys CLK_CAM_SENIF>, + <&topckgen CLK_TOP_SENIF_SEL>; + clock-names =3D "camsys", "top_mux"; + + power-domains =3D <&spm MT8365_POWER_DOMAIN_CAM>; + + phys =3D <&mipi_csi0 PHY_TYPE_DPHY>, <&mipi_csi1>; + phy-names =3D "csi0", "csi1"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + seninf_in1: endpoint { + clock-lanes =3D <2>; + data-lanes =3D <1 3 0 4>; + remote-endpoint =3D <&isp1_out>; + }; + }; + + port@1 { + reg =3D <1>; + }; + + port@2 { + reg =3D <2>; + }; + + port@3 { + reg =3D <3>; + }; + + port@4 { + reg =3D <4>; + seninf_camsv1_endpoint: endpoint { + remote-endpoint =3D <&camsv1_endpoint>; + }; + }; + + port@5 { + reg =3D <5>; + seninf_camsv2_endpoint: endpoint { + remote-endpoint =3D <&camsv2_endpoint>; + }; + }; + + port@6 { + reg =3D <6>; + }; + + port@7 { + reg =3D <7>; + }; + + port@8 { + reg =3D <8>; + }; + + port@9 { + reg =3D <9>; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 4c7f9e37c5653664a11a2cb36aba942830b5a8d1..242c54c88a4a22fc0cbe5c4fc5d= 7b0d0f84b329e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14565,6 +14565,13 @@ M: Sean Wang S: Maintained F: drivers/char/hw_random/mtk-rng.c =20 +MEDIATEK ISP3.0 DRIVER +M: Laurent Pinchart +M: Julien Stephan +M: Andy Hsieh +S: Supported +F: Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml + MEDIATEK SMI DRIVER M: Yong Wu L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) --=20 2.47.0 From nobody Sun Nov 24 05:51:41 2024 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29CE414EC55 for ; Thu, 21 Nov 2024 08:53:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732179202; cv=none; b=JTl/XVUC6SV6+k3BC+DxOgND9nVVvZlo0N+tEt3M81acs2ZgZEQbN9Jfccghr55JWO2Fe5Gdt8Eoj4NmN7r1rN6NLeXjTdjKKvQClzzVzTWAZ3qqNSUNUj8qN/zQVG1XmJx5OelQ8ZZRpQmmFggIndrHGSB6oQJrKipXFEDA7Do= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732179202; c=relaxed/simple; bh=VcRZkRl52glLElGROP/kyPKKuC4UuiBlNv7MHYLPriI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XiyVMPu1KG9P7BlOvpc7Jm1FGBivqtX1iaVGG61lb+EQqponk1iRJidSWUh3N2QJMrHq5Eul1LChs8RZn515yIzXysb36zYrsx8VdvWMoD1u9AeHValvsPm3az8FMMg23qenC3TBnq/e55fHW0pgJrdHweXLZodcROR8nHRlsKU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=0K51CpJV; arc=none smtp.client-ip=209.85.221.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="0K51CpJV" Received: by mail-wr1-f51.google.com with SMTP id ffacd0b85a97d-38232cebb0cso429517f8f.1 for ; Thu, 21 Nov 2024 00:53:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1732179198; x=1732783998; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=BDQsEsIuIG+15FFvp5RFf0/w51W8dM3c8wZ8eGx3or8=; b=0K51CpJVsRtEvGPbmIQkr6X1vSlVrQ3C2Sum0SN9UF2rzGPuUg4tl4cRlyfo0i60W7 OZsDz/i8fz6XTRGyfYgqvxV1s4Gy1MsAiMqnTiwPQezj5tOufKKMQ0Ti0y97K2ZhJDsm m32akw8vil85bYIXUptLRt5fr3lgHIQcxDEltH2GLQqkF5gV0dNtSPrEGLq8I58rdh+n wyuGQtjLbgr/lQj0KlODBDHdm4jQmoLuWuK5qaJMTyyEQgflGRroJCxz3JbNICIzV41K CpEmj9qqgs1u7BngIIxT15geBewTJe/fYgfvBqF6Zho7JisnT5ukwrTLeKO+VWeA+YgT GW/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732179198; x=1732783998; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BDQsEsIuIG+15FFvp5RFf0/w51W8dM3c8wZ8eGx3or8=; b=hio9UZXtzEaMJOxB6Rb8dWfqRCVk9FheIgLtIp3/V/X6mfij1xMq0E9oDE+R68LgEx tu1bYDHiWFbtLS+p56cfrZkGkgivX4QPJopgH+85oD0Pu5Ii6RPQYUZ3ZvnBAtddi2Jt BOMqZJowVr2dcjeHrjdg3jQwXDMDojKIeYwAOOx9I6JdijwO34hlwLmK6Zmsa3/ImWQQ Y260VME+4yUWXwS5IOJFQNkRKa3uktPdviBgpHcGiZpo6jPIjrc1D5BBxMuCuiz+zzbr BUUN6V0zg5m9W8CsVtZhih4bbqJ7NL81CoN+vgVAxXFMpHzWI/q/W+zqS5aZco1+Erm4 /nXg== X-Forwarded-Encrypted: i=1; AJvYcCUZ5Hqjcy51sEM70sZCMFVX+BqcnbaolUAMGsAH6kObykhVb38a89IZ4tGwy3GDavuYrn3GqO/euxn4l2Q=@vger.kernel.org X-Gm-Message-State: AOJu0YwnNAuJKpOTTLb+ZykisXzvyxSFrE90aahlkrmLeKc0tBNrB2MU qNXzXSF3Spr2Hn/LSL/XjslGPnOxZwoIO0gGRkLpKP6R0tp4kIdVr0Pp/15TA8I= X-Google-Smtp-Source: AGHT+IFBXGEL/v3q5aubHnM8Fav9mx+Z1bn+z8Isj/XnwmhflIinllJom4TbpB46wOLK9/cU6nIV9Q== X-Received: by 2002:a5d:59af:0:b0:382:4cc3:7def with SMTP id ffacd0b85a97d-38254adf651mr3994848f8f.7.1732179198364; Thu, 21 Nov 2024 00:53:18 -0800 (PST) Received: from [192.168.42.0] (2a02-842a-d52e-6101-6fd0-06c4-5d68-f0a5.rev.sfr.net. [2a02:842a:d52e:6101:6fd0:6c4:5d68:f0a5]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-382549111fdsm4219900f8f.58.2024.11.21.00.53.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2024 00:53:18 -0800 (PST) From: Julien Stephan Date: Thu, 21 Nov 2024 09:53:16 +0100 Subject: [PATCH v7 2/5] dt-bindings: media: add mediatek ISP3.0 camsv Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241121-add-mtk-isp-3-0-support-v7-2-b04dc9610619@baylibre.com> References: <20241121-add-mtk-isp-3-0-support-v7-0-b04dc9610619@baylibre.com> In-Reply-To: <20241121-add-mtk-isp-3-0-support-v7-0-b04dc9610619@baylibre.com> To: Laurent Pinchart , Andy Hsieh , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Julien Stephan , Phi-bang Nguyen X-Mailer: b4 0.14.2 From: Phi-bang Nguyen This adds the bindings, for the ISP3.0 camsv module embedded in some Mediatek SoC, such as the mt8365 Signed-off-by: Phi-bang Nguyen Reviewed-by: Rob Herring (Arm) Signed-off-by: Julien Stephan --- .../bindings/media/mediatek,mt8365-camsv.yaml | 109 +++++++++++++++++= ++++ MAINTAINERS | 1 + 2 files changed, 110 insertions(+) diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8365-camsv.= yaml b/Documentation/devicetree/bindings/media/mediatek,mt8365-camsv.yaml new file mode 100644 index 0000000000000000000000000000000000000000..fdd07675645917fbcd692606c83= 6efd07e50ac0c --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mt8365-camsv.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2023 MediaTek, BayLibre +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mt8365-camsv.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek CAMSV 3.0 + +maintainers: + - Laurent Pinchart + - Julien Stephan + - Andy Hsieh + +description: + The CAMSV is a video capture device that includes a DMA engine connected= to + the SENINF CSI-2 receivers. The number of CAMSVs depend on the SoC model. + +properties: + compatible: + const: mediatek,mt8365-camsv + + reg: + items: + - description: camsv base + - description: img0 base + - description: tg base + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + items: + - description: cam clock + - description: camtg clock + - description: camsv clock + + clock-names: + items: + - const: cam + - const: camtg + - const: camsv + + iommus: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Connection to the SENINF output + + required: + - port@0 + +required: + - compatible + - interrupts + - clocks + - clock-names + - power-domains + - iommus + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + camsv@15050000 { + compatible =3D "mediatek,mt8365-camsv"; + reg =3D <0 0x15050000 0 0x0040>, + <0 0x15050208 0 0x0020>, + <0 0x15050400 0 0x0100>; + interrupts =3D ; + clocks =3D <&camsys CLK_CAM>, + <&camsys CLK_CAMTG>, + <&camsys CLK_CAMSV0>; + clock-names =3D "cam", "camtg", "camsv"; + iommus =3D <&iommu M4U_PORT_CAM_IMGO>; + power-domains =3D <&spm MT8365_POWER_DOMAIN_CAM>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + port@0 { + reg =3D <0>; + camsv1_endpoint: endpoint { + remote-endpoint =3D <&seninf_camsv1_endpoint>; + }; + }; + }; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 242c54c88a4a22fc0cbe5c4fc5d7b0d0f84b329e..6147629405c8d40b00c4755a4ee= 27a746b26f782 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14570,6 +14570,7 @@ M: Laurent Pinchart M: Julien Stephan M: Andy Hsieh S: Supported +F: Documentation/devicetree/bindings/media/mediatek,mt8365-camsv.yaml F: Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml =20 MEDIATEK SMI DRIVER --=20 2.47.0 From nobody Sun Nov 24 05:51:41 2024 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A9BE1C7B64 for ; Thu, 21 Nov 2024 08:53:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732179207; cv=none; b=MDw13DUmz+eyNMIY4E1Mgiaua/g86UFAna2FWH5Uf2l5eH0kH1jVP8Cl4zwhRV2+s1VvbwQ3CgjaskhonUxqGyIB0Y6YrDts5owetGcoD1WaUa2AMZIejpqKTnrTPxibPhB3JXxZGQd1LFIjIxE9b42hbYMEBgKRwlfnRDfoiSQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732179207; c=relaxed/simple; bh=Ok7XQOepaXdtZd/kR23wFrTEICCgd84NsGp9fcgzx2Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OzD94+JN5Om/KoTSIC8opoVxaZxMHCTAkheiRutIvqHyFhwNyE7PtZ+MxymbNwPCVTwed7u8gImtthFgtgL7OiexPGCyBAAwb+8eiPdJC/Gyd3ibBM8aB94I7Ur46mW0MTx9n9ZFkFREV8teyotrBVCqjC+F0F7nN77p9meXA9k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=eBgdBq08; arc=none smtp.client-ip=209.85.221.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="eBgdBq08" Received: by mail-wr1-f51.google.com with SMTP id ffacd0b85a97d-3824038142aso411137f8f.2 for ; Thu, 21 Nov 2024 00:53:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1732179200; x=1732784000; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=XFUkoqarupU4XVceczOkOe0mXTzGDb94EOYO0zdXKXk=; b=eBgdBq08pkalguHVJfpsUWCdVRgTKg6abBGguZrkA/AAMtvJoFjctDwRvgB7xOUwsF iBzEPAuqKP02OTjMMNFJ6td9lBnsxU3oIIDfB36DflnxRILiFvmqOprLJJOssKkXzCUo dxsp+UYlXevaN2iTgt5W7BtrPMr1Tph4gHpu7hUZpU2PsD5mrB8bd4RdLPMS1Jor9Y9f VCxUSUu2CZWrw++jvaw0m/2W2+6u/6D8hM7fgnTSzU+cyM0GQJSNKI3RDsBou+JUw6Si Dd0/jhCDHYCvHg8WiKN7Ska+iEIkIbm7CJqP/PXGJ+eRFze8kLoQufB/BLXeTA2fHilz 8luA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732179200; x=1732784000; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XFUkoqarupU4XVceczOkOe0mXTzGDb94EOYO0zdXKXk=; b=G5xW/AFMAlx0fbLN6+xFkmHn54AaJIxGYR6yCIh9ANy9UvqJ5p6/HWBLhiVhLEvjIF GYiCk392klJmD8gZSJbsfm4n+1UQPGEF7kiZgWI2J9EaIvGRr2cqF9LdfQ5eMbqCMkUm 4G+m2bIyrt/Kvvqd5l7hxygjw99lJiPOaNrPSlSi6XikIdGg8iLz4Bh82ann8PBoSC/4 kSgAy7nm8B5a0cqqhcr/wLEJtbOhhiUZkNcaoxYrllZASllnWNapIlY8ccYMMFtsbTh0 o2EduHRhIX0jy5TucgkCFc2iUpXQ6V7PUIFpdEM10WXZN+wVZn4D4JbF9AV0ECKj2NoR sfDw== X-Forwarded-Encrypted: i=1; AJvYcCWeLtGHX82J/0b4nq6ksOOLPstCa4SBl99obKLosrD3zQA/BxHQoNU9LPtGkqnrQkHczxfpi9iTJPT79no=@vger.kernel.org X-Gm-Message-State: AOJu0Yy7kMblzOPI4hg8dNIK8dWsRwiBPz1dU9spQqonag7nzVTIstnv oMiL+IAKH8mwCS+jeGn5VB6tJD+GX7ZPeRqGkWkI3qsgXBZtBtInkD1gdpF/xTk= X-Google-Smtp-Source: AGHT+IGtkLAqEPSclQZVSAuCCIKbLDm2GvHfCrttMVEjzdt29SDzcAFtGoNg+V9FDqAjGRUL310MCA== X-Received: by 2002:a5d:47a9:0:b0:382:372a:5719 with SMTP id ffacd0b85a97d-38254b2744emr4193326f8f.59.1732179199362; Thu, 21 Nov 2024 00:53:19 -0800 (PST) Received: from [192.168.42.0] (2a02-842a-d52e-6101-6fd0-06c4-5d68-f0a5.rev.sfr.net. [2a02:842a:d52e:6101:6fd0:6c4:5d68:f0a5]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-382549111fdsm4219900f8f.58.2024.11.21.00.53.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2024 00:53:19 -0800 (PST) From: Julien Stephan Date: Thu, 21 Nov 2024 09:53:17 +0100 Subject: [PATCH v7 3/5] media: platform: mediatek: isp: add mediatek ISP3.0 sensor interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241121-add-mtk-isp-3-0-support-v7-3-b04dc9610619@baylibre.com> References: <20241121-add-mtk-isp-3-0-support-v7-0-b04dc9610619@baylibre.com> In-Reply-To: <20241121-add-mtk-isp-3-0-support-v7-0-b04dc9610619@baylibre.com> To: Laurent Pinchart , Andy Hsieh , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Julien Stephan , Louis Kuo , Phi-bang Nguyen , Florian Sylvestre X-Mailer: b4 0.14.2 From: Louis Kuo This will add the mediatek ISP3.0 seninf (sensor interface) driver found on several Mediatek SoCs such as the mt8365. Then seninf module has 4 physical CSI-2 inputs. Depending on the soc they may not be all connected. Signed-off-by: Louis Kuo Signed-off-by: Phi-bang Nguyen Signed-off-by: Florian Sylvestre Co-developed-by: Laurent Pinchart Signed-off-by: Laurent Pinchart Co-developed-by: Julien Stephan Signed-off-by: Julien Stephan --- MAINTAINERS | 1 + drivers/media/platform/mediatek/Kconfig | 1 + drivers/media/platform/mediatek/Makefile | 1 + drivers/media/platform/mediatek/isp/Kconfig | 17 + drivers/media/platform/mediatek/isp/Makefile | 4 + drivers/media/platform/mediatek/isp/mtk_seninf.c | 1636 ++++++++++++++++= ++++ .../media/platform/mediatek/isp/mtk_seninf_reg.h | 114 ++ 7 files changed, 1774 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 6147629405c8d40b00c4755a4ee27a746b26f782..9654a7f4e21cddb77bb799add56= 110f5f27f7a79 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14572,6 +14572,7 @@ M: Andy Hsieh S: Supported F: Documentation/devicetree/bindings/media/mediatek,mt8365-camsv.yaml F: Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml +F: drivers/media/platform/mediatek/isp/* =20 MEDIATEK SMI DRIVER M: Yong Wu diff --git a/drivers/media/platform/mediatek/Kconfig b/drivers/media/platfo= rm/mediatek/Kconfig index 84104e2cd02447790ae5c29953a2e82ca4fdd0a7..a405d57013292c515d2a2db4d43= aa1ed8cb21f7b 100644 --- a/drivers/media/platform/mediatek/Kconfig +++ b/drivers/media/platform/mediatek/Kconfig @@ -2,6 +2,7 @@ =20 comment "Mediatek media platform drivers" =20 +source "drivers/media/platform/mediatek/isp/Kconfig" source "drivers/media/platform/mediatek/jpeg/Kconfig" source "drivers/media/platform/mediatek/mdp/Kconfig" source "drivers/media/platform/mediatek/vcodec/Kconfig" diff --git a/drivers/media/platform/mediatek/Makefile b/drivers/media/platf= orm/mediatek/Makefile index 38e6ba917fe5cdd932aa6c88221c9a7aa5a7705a..2341a0e373a4e30f0caf823ab67= 098fde96fc071 100644 --- a/drivers/media/platform/mediatek/Makefile +++ b/drivers/media/platform/mediatek/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only +obj-y +=3D isp/ obj-y +=3D jpeg/ obj-y +=3D mdp/ obj-y +=3D vcodec/ diff --git a/drivers/media/platform/mediatek/isp/Kconfig b/drivers/media/pl= atform/mediatek/isp/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..2a3cef81d15aa12633ade2f3be0= bba36b9af62e1 --- /dev/null +++ b/drivers/media/platform/mediatek/isp/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-only +config MTK_SENINF30 + tristate "MediaTek ISP3.0 SENINF driver" + depends on ARCH_MEDIATEK || COMPILE_TEST + depends on OF + select MEDIA_CONTROLLER + select PHY_MTK_MIPI_CSI_0_5 + select V4L2_FWNODE + select VIDEO_V4L2_SUBDEV_API + default n + help + This driver provides a MIPI CSI-2 receiver interface to connect + an external camera module with MediaTek ISP3.0. It is able to handle + multiple cameras at the same time. + + To compile this driver as a module, choose M here: the + module will be called mtk-seninf. diff --git a/drivers/media/platform/mediatek/isp/Makefile b/drivers/media/p= latform/mediatek/isp/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..375d720f9ed75e2197bb723bdce= 9bc0472e62842 --- /dev/null +++ b/drivers/media/platform/mediatek/isp/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +mtk-seninf-objs +=3D mtk_seninf.o +obj-$(CONFIG_MTK_SENINF30) +=3D mtk-seninf.o diff --git a/drivers/media/platform/mediatek/isp/mtk_seninf.c b/drivers/med= ia/platform/mediatek/isp/mtk_seninf.c new file mode 100644 index 0000000000000000000000000000000000000000..3b040f96bb63dc90db7d17c46f9= 20d5597d936db --- /dev/null +++ b/drivers/media/platform/mediatek/isp/mtk_seninf.c @@ -0,0 +1,1636 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 MediaTek Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mtk_seninf_reg.h" + +#define SENINF_TIMESTAMP_STEP 0x67 +#define SENINF_SETTLE_DELAY 0x15 +#define SENINF_HS_TRAIL_PARAMETER 0x8 + +#define SENINF_MAX_NUM_INPUTS 4 +#define SENINF_MAX_NUM_OUTPUTS 6 +#define SENINF_MAX_NUM_MUXES 6 +#define SENINF_MAX_NUM_PADS (SENINF_MAX_NUM_INPUTS + \ + SENINF_MAX_NUM_OUTPUTS) + +#define SENINF_DEFAULT_BUS_FMT MEDIA_BUS_FMT_SGRBG10_1X10 +#define SENINF_DEFAULT_WIDTH 1920 +#define SENINF_DEFAULT_HEIGHT 1080 + +#define SENINF_PAD_10BIT 0 + +#define SENINF_TEST_MODEL 0 +#define SENINF_NORMAL_MODEL 1 +#define SENINF_ALL_ERR_IRQ_EN 0x7f +#define SENINF_IRQ_CLR_SEL 0x80000000 + +#define SENINF_MIPI_SENSOR 0x8 + +#define MTK_CSI_MAX_LANES 4 + +/* Port number in the device tree. */ +enum mtk_seninf_port { + CSI_PORT_0 =3D 0, /* 4D1C or 2D1C */ + CSI_PORT_1, /* 4D1C */ + CSI_PORT_2, /* 4D1C */ + CSI_PORT_0B, /* 2D1C */ +}; + +enum mtk_seninf_id { + SENINF_1 =3D 0, + SENINF_2 =3D 1, + SENINF_3 =3D 2, + SENINF_5 =3D 4, +}; + +static const u32 port_to_seninf_id[] =3D { + [CSI_PORT_0] =3D SENINF_1, + [CSI_PORT_1] =3D SENINF_3, + [CSI_PORT_2] =3D SENINF_5, + [CSI_PORT_0B] =3D SENINF_2, +}; + +enum mtk_seninf_phy_mode { + SENINF_PHY_MODE_NONE, + SENINF_PHY_MODE_4D1C, + SENINF_PHY_MODE_2D1C, +}; + +enum mtk_seninf_format_flag { + MTK_SENINF_FORMAT_BAYER =3D BIT(0), + MTK_SENINF_FORMAT_DPCM =3D BIT(1), + MTK_SENINF_FORMAT_JPEG =3D BIT(2), + MTK_SENINF_FORMAT_INPUT_ONLY =3D BIT(3), +}; + +/** + * struct mtk_seninf_conf - Model-specific SENINF parameters + * @model: Model description + * @nb_inputs: Number of SENINF inputs + * @nb_muxes: Number of SENINF MUX (FIFO) instances + * @nb_outputs: Number of outputs (to CAM and CAMSV instances) + */ +struct mtk_seninf_conf { + const char *model; + u8 nb_inputs; + u8 nb_muxes; + u8 nb_outputs; +}; + +/** + * struct mtk_seninf_format_info - Information about media bus formats + * @code: V4L2 media bus code + * @flags: Flags describing the format, as a combination of MTK_SENINF_FOR= MAT_* + * @bpp: Bits per pixel + */ +struct mtk_seninf_format_info { + u32 code; + u32 flags; + u8 bpp; +}; + +/** + * struct mtk_seninf_input - SENINF input block + * @pad: DT port and media entity pad number + * @seninf_id: SENINF hardware instance ID + * @base: Memory mapped I/O based address + * @seninf: Back pointer to the mtk_seninf + * @phy: PHY connected to the input + * @phy_mode: PHY operation mode (NONE when the input is not connected) + * @bus: CSI-2 bus configuration from DT + * @source_sd: Source subdev connected to the input + */ +struct mtk_seninf_input { + enum mtk_seninf_port pad; + enum mtk_seninf_id seninf_id; + void __iomem *base; + struct mtk_seninf *seninf; + + struct phy *phy; + enum mtk_seninf_phy_mode phy_mode; + + struct v4l2_mbus_config_mipi_csi2 bus; + + struct v4l2_subdev *source_sd; +}; + +/** + * struct mtk_seninf_mux - SENINF MUX channel + * @pad: DT port and media entity pad number + * @mux_id: MUX hardware instance ID + * @base: Memory mapped I/O based address + * @seninf: Back pointer to the mtk_seninf + */ +struct mtk_seninf_mux { + unsigned int pad; + unsigned int mux_id; + void __iomem *base; + struct mtk_seninf *seninf; +}; + +/** + * struct mtk_seninf - Top-level SENINF device + * @dev: The (platform) device + * @phy: PHYs at the SENINF inputs + * @num_clks: Number of clocks in the clks array + * @clks: Clocks + * @base: Memory mapped I/O base address + * @media_dev: Media controller device + * @v4l2_dev: V4L2 device + * @subdev: V4L2 subdevice + * @pads: Media entity pads + * @notifier: V4L2 async notifier for source subdevs + * @ctrl_handler: V4L2 controls handler + * @source_format: Active format on the source pad + * @inputs: Array of SENINF inputs + * @muxes: Array of MUXes + * @conf: Model-specific SENINF parameters + * @is_testmode: Whether or not the test pattern generator is enabled + */ +struct mtk_seninf { + struct device *dev; + struct phy *phy[5]; + unsigned int num_clks; + struct clk_bulk_data *clks; + void __iomem *base; + + struct media_device media_dev; + struct v4l2_device v4l2_dev; + struct v4l2_subdev subdev; + struct media_pad pads[SENINF_MAX_NUM_PADS]; + struct v4l2_async_notifier notifier; + struct v4l2_ctrl_handler ctrl_handler; + + struct mtk_seninf_input inputs[SENINF_MAX_NUM_INPUTS]; + struct mtk_seninf_mux muxes[SENINF_MAX_NUM_MUXES]; + + const struct mtk_seninf_conf *conf; + + bool is_testmode; +}; + +inline struct mtk_seninf *sd_to_mtk_seninf(struct v4l2_subdev *sd) +{ + return container_of(sd, struct mtk_seninf, subdev); +} + +static inline bool mtk_seninf_pad_is_sink(struct mtk_seninf *priv, + unsigned int pad) +{ + return pad < priv->conf->nb_inputs; +} + +static inline bool mtk_seninf_pad_is_source(struct mtk_seninf *priv, + unsigned int pad) +{ + return !mtk_seninf_pad_is_sink(priv, pad); +} + +/* -----------------------------------------------------------------------= ------ + * Formats + */ + +static const struct mtk_seninf_format_info mtk_seninf_formats[] =3D { + { + .code =3D MEDIA_BUS_FMT_SBGGR8_1X8, + .flags =3D MTK_SENINF_FORMAT_BAYER, + .bpp =3D 8, + }, { + .code =3D MEDIA_BUS_FMT_SGBRG8_1X8, + .flags =3D MTK_SENINF_FORMAT_BAYER, + .bpp =3D 8, + }, { + .code =3D MEDIA_BUS_FMT_SGRBG8_1X8, + .flags =3D MTK_SENINF_FORMAT_BAYER, + .bpp =3D 8, + }, { + .code =3D MEDIA_BUS_FMT_SRGGB8_1X8, + .flags =3D MTK_SENINF_FORMAT_BAYER, + .bpp =3D 8, + }, { + .code =3D MEDIA_BUS_FMT_SGRBG10_1X10, + .flags =3D MTK_SENINF_FORMAT_BAYER, + .bpp =3D 10, + }, { + .code =3D MEDIA_BUS_FMT_SRGGB10_1X10, + .flags =3D MTK_SENINF_FORMAT_BAYER, + .bpp =3D 10, + }, { + .code =3D MEDIA_BUS_FMT_SBGGR10_1X10, + .flags =3D MTK_SENINF_FORMAT_BAYER, + .bpp =3D 10, + }, { + .code =3D MEDIA_BUS_FMT_SGBRG10_1X10, + .flags =3D MTK_SENINF_FORMAT_BAYER, + .bpp =3D 10, + }, { + .code =3D MEDIA_BUS_FMT_SBGGR12_1X12, + .flags =3D MTK_SENINF_FORMAT_BAYER, + .bpp =3D 12, + }, { + .code =3D MEDIA_BUS_FMT_SGBRG12_1X12, + .flags =3D MTK_SENINF_FORMAT_BAYER, + .bpp =3D 12, + }, { + .code =3D MEDIA_BUS_FMT_SGRBG12_1X12, + .flags =3D MTK_SENINF_FORMAT_BAYER, + .bpp =3D 12, + }, { + .code =3D MEDIA_BUS_FMT_SRGGB12_1X12, + .flags =3D MTK_SENINF_FORMAT_BAYER, + .bpp =3D 12, + }, { + .code =3D MEDIA_BUS_FMT_SBGGR14_1X14, + .flags =3D MTK_SENINF_FORMAT_BAYER, + .bpp =3D 14, + }, { + .code =3D MEDIA_BUS_FMT_SGBRG14_1X14, + .flags =3D MTK_SENINF_FORMAT_BAYER, + .bpp =3D 14, + }, { + .code =3D MEDIA_BUS_FMT_SGRBG14_1X14, + .flags =3D MTK_SENINF_FORMAT_BAYER, + .bpp =3D 14, + }, { + .code =3D MEDIA_BUS_FMT_SRGGB14_1X14, + .flags =3D MTK_SENINF_FORMAT_BAYER, + .bpp =3D 14, + }, { + .code =3D MEDIA_BUS_FMT_SBGGR16_1X16, + .flags =3D MTK_SENINF_FORMAT_BAYER, + .bpp =3D 16, + }, { + .code =3D MEDIA_BUS_FMT_SGBRG16_1X16, + .flags =3D MTK_SENINF_FORMAT_BAYER, + .bpp =3D 16, + }, { + .code =3D MEDIA_BUS_FMT_SGRBG16_1X16, + .flags =3D MTK_SENINF_FORMAT_BAYER, + .bpp =3D 16, + }, { + .code =3D MEDIA_BUS_FMT_SRGGB16_1X16, + .flags =3D MTK_SENINF_FORMAT_BAYER, + .bpp =3D 16, + }, { + .code =3D MEDIA_BUS_FMT_UYVY8_1X16, + .bpp =3D 16, + }, { + .code =3D MEDIA_BUS_FMT_VYUY8_1X16, + .bpp =3D 16, + }, { + .code =3D MEDIA_BUS_FMT_YUYV8_1X16, + .bpp =3D 16, + }, { + .code =3D MEDIA_BUS_FMT_YVYU8_1X16, + .bpp =3D 16, + }, { + .code =3D MEDIA_BUS_FMT_JPEG_1X8, + .flags =3D MTK_SENINF_FORMAT_JPEG, + .bpp =3D 8, + }, { + .code =3D MEDIA_BUS_FMT_S5C_UYVY_JPEG_1X8, + .flags =3D MTK_SENINF_FORMAT_JPEG, + .bpp =3D 8, + }, + /* Keep the input-only formats last. */ + { + .code =3D MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8, + .flags =3D MTK_SENINF_FORMAT_DPCM | MTK_SENINF_FORMAT_INPUT_ONLY, + .bpp =3D 8, + }, { + .code =3D MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8, + .flags =3D MTK_SENINF_FORMAT_DPCM | MTK_SENINF_FORMAT_INPUT_ONLY, + .bpp =3D 8, + }, { + .code =3D MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8, + .flags =3D MTK_SENINF_FORMAT_DPCM | MTK_SENINF_FORMAT_INPUT_ONLY, + .bpp =3D 8, + }, { + .code =3D MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8, + .flags =3D MTK_SENINF_FORMAT_DPCM | MTK_SENINF_FORMAT_INPUT_ONLY, + .bpp =3D 8, + } +}; + +static const struct mtk_seninf_format_info *mtk_seninf_format_info(u32 cod= e) +{ + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(mtk_seninf_formats); ++i) { + if (mtk_seninf_formats[i].code =3D=3D code) + return &mtk_seninf_formats[i]; + } + + return NULL; +} + +static u32 mtk_seninf_read(struct mtk_seninf *priv, u32 reg) +{ + return readl(priv->base + reg); +} + +static void mtk_seninf_write(struct mtk_seninf *priv, u32 reg, u32 value) +{ + writel(value, priv->base + reg); +} + +static void __mtk_seninf_update(struct mtk_seninf *priv, u32 reg, + u32 mask, u32 value) +{ + u32 val =3D mtk_seninf_read(priv, reg); + + writel((val & ~mask) | (value & mask), priv->base + reg); +} + +#define mtk_seninf_update(priv, reg, field, val) \ + __mtk_seninf_update(priv, reg, reg##_##field, \ + FIELD_PREP(reg##_##field, val)) + +static u32 mtk_seninf_inuput_read(struct mtk_seninf_input *input, u32 reg) +{ + return readl(input->base + reg); +} + +static void mtk_seninf_input_write(struct mtk_seninf_input *input, u32 reg, + u32 value) +{ + writel(value, input->base + reg); +} + +static void __mtk_seninf_input_update(struct mtk_seninf_input *input, u32 = reg, + u32 mask, u32 value) +{ + u32 val =3D mtk_seninf_inuput_read(input, reg); + + mtk_seninf_input_write(input, reg, (val & ~mask) | (value & mask)); +} + +#define mtk_seninf_input_update(input, reg, field, val) \ + __mtk_seninf_input_update(input, reg, reg##_##field, \ + FIELD_PREP(reg##_##field, val)) + +static u32 mtk_seninf_mux_read(struct mtk_seninf_mux *mux, u32 reg) +{ + return readl(mux->base + reg); +} + +static void mtk_seninf_mux_write(struct mtk_seninf_mux *mux, u32 reg, + u32 value) +{ + writel(value, mux->base + reg); +} + +static void __mtk_seninf_mux_update(struct mtk_seninf_mux *mux, u32 reg, + u32 mask, u32 value) +{ + u32 val =3D mtk_seninf_mux_read(mux, reg); + + mtk_seninf_mux_write(mux, reg, (val & ~mask) | (value & mask)); +} + +#define mtk_seninf_mux_update(mux, reg, field, val) \ + __mtk_seninf_mux_update(mux, reg, reg##_##field, \ + FIELD_PREP(reg##_##field, val)) + +/* -----------------------------------------------------------------------= ------ + * Hardware Configuration + * + * The SENINF is the camera sensor interface. On the input side it contains + * input channels (also named SENINF), each made of a CSI-2 receiver, an + * interface for parallel sensors, and a test pattern generator. The input= s are + * routed through a N:M crossbar switch (TOP MUX) to VC/DT filters with a = FIFO + * (MUX). The MUX are routed to another N:M crossbar switch (CAM MUX), who= se + * output is then connected to other IP cores. + * + * +-------------------------------------------------------+ + * | SENINF | + * | | + * +-------+ | +----------+ TOP MUX | + * | | | | SENINF | |\ CAM MUX | + * | D-PHY | ---> | CSI-2 RX | ---> | | +------------+ |\ | + * | | | | TPG | -> | | ---> | MUX (FIFO) | ---> | | ---> = CAMSV + * +-------+ | +----------+ -> | | +------------+ -> | | | + * | |/ -> | | | + * | |/ | + * | | + * ... | ... ... ---> + * | | + * | | + * +-------------------------------------------------------+ + * + * The number of PHYs, SENINF and MUX differ between SoCs. MT8167 has a si= ngle + * MUX and thus no output CAM MUX crossbar switch. + */ + +static void mtk_seninf_csi2_setup_phy(struct mtk_seninf *priv) +{ + /* CSI0 */ + if (priv->inputs[CSI_PORT_0].phy) { + const struct mtk_seninf_input *input =3D &priv->inputs[CSI_PORT_0]; + + mtk_seninf_update(priv, SENINF_TOP_PHY_SENINF_CTL_CSI0, + DPHY_MODE, 0 /* 4D1C*/); + mtk_seninf_update(priv, SENINF_TOP_PHY_SENINF_CTL_CSI0, + CK_SEL_1, input->bus.clock_lane); + mtk_seninf_update(priv, SENINF_TOP_PHY_SENINF_CTL_CSI0, + CK_SEL_2, 2); + mtk_seninf_update(priv, SENINF_TOP_PHY_SENINF_CTL_CSI0, + PHY_SENINF_LANE_MUX_CSI0_EN, 1); + } + + /* CSI1 */ + if (priv->inputs[CSI_PORT_1].phy) { + const struct mtk_seninf_input *input =3D &priv->inputs[CSI_PORT_1]; + + mtk_seninf_update(priv, SENINF_TOP_PHY_SENINF_CTL_CSI1, + DPHY_MODE, 0 /* 4D1C */); + mtk_seninf_update(priv, SENINF_TOP_PHY_SENINF_CTL_CSI1, + CK_SEL_1, input->bus.clock_lane); + mtk_seninf_update(priv, SENINF_TOP_PHY_SENINF_CTL_CSI1, + PHY_SENINF_LANE_MUX_CSI1_EN, 1); + } +} + +static void mtk_seninf_input_setup_csi2_rx(struct mtk_seninf_input *input) +{ + unsigned int lanes[MTK_CSI_MAX_LANES] =3D { }; + unsigned int i; + + /* + * Configure data lane muxing. In 2D1C mode, lanes 0 to 2 correspond to + * CSIx[AB]_L{0,1,2}, and in 4D1C lanes 0 to 5 correspond to + * CSIxA_L{0,1,2}, CSIxB_L{0,1,2}. + * + * The clock lane must be skipped when calculating the index of the + * physical data lane. For instance, in 4D1C mode, the sensor clock + * lane is typically connected to lane 2 (CSIxA_L2), and the sensor + * data lanes 0-3 to lanes 1 (CSIxA_L1), 3 (CSIxB_L0), 0 (CSIxA_L0) and + * 4 (CSIxB_L1). The when skipping the clock lane, the data lane + * indices become 1, 2, 0 and 3. + */ + for (i =3D 0; i < input->bus.num_data_lanes; ++i) { + lanes[i] =3D input->bus.data_lanes[i]; + if (lanes[i] > input->bus.clock_lane) + lanes[i]--; + } + + mtk_seninf_input_update(input, MIPI_RX_CON24_CSI0, + CSI0_BIST_LN0_MUX, lanes[0]); + mtk_seninf_input_update(input, MIPI_RX_CON24_CSI0, + CSI0_BIST_LN1_MUX, lanes[1]); + mtk_seninf_input_update(input, MIPI_RX_CON24_CSI0, + CSI0_BIST_LN2_MUX, lanes[2]); + mtk_seninf_input_update(input, MIPI_RX_CON24_CSI0, + CSI0_BIST_LN3_MUX, lanes[3]); +} + +static s64 mtk_seninf_get_clk_divider(struct mtk_seninf *priv, + int pad_num, + u8 bpp, unsigned int num_data_lanes) +{ + struct media_entity *entity =3D &priv->subdev.entity; + struct media_pad *pad; + struct v4l2_subdev *sd; + s64 link_frequency, pixel_clock; + + + if (!(entity->pads[pad_num].flags & MEDIA_PAD_FL_SINK)) + return -ENODEV; + + pad =3D media_pad_remote_pad_first(&entity->pads[pad_num]); + if (!pad) + return -ENOENT; + + if (!is_media_entity_v4l2_subdev(pad->entity)) + return -ENOENT; + + sd =3D media_entity_to_v4l2_subdev(pad->entity); + link_frequency =3D v4l2_get_link_freq(sd->ctrl_handler, bpp, + num_data_lanes * 2); + pixel_clock =3D div_u64(link_frequency * 2 * num_data_lanes, bpp); + /* + * According to datasheet: Sensor master clock =3D ISP_clock/(CLKCNT +1) + * we also have the following constraint: + * pixel_clock >=3D Sensor master clock + */ + return div_u64(clk_get_rate(priv->clks[0].clk), pixel_clock) - 1; +} + +static int mtk_seninf_input_setup_csi2(struct mtk_seninf *priv, + struct mtk_seninf_input *input, + struct v4l2_subdev_state *state) +{ + const struct mtk_seninf_format_info *fmtinfo; + const struct v4l2_mbus_framefmt *format; + unsigned int num_data_lanes =3D input->bus.num_data_lanes; + unsigned int val =3D 0; + s64 clock_count; + + format =3D v4l2_subdev_state_get_format(state, input->pad, 0); + fmtinfo =3D mtk_seninf_format_info(format->code); + + /* Configure timestamp */ + mtk_seninf_input_write(input, SENINF_TG1_TM_STP, SENINF_TIMESTAMP_STEP); + + /* HQ */ + /* + * Configure phase counter. Zero means: + * - Sensor master clock: ISP_CLK + * - Sensor clock polarity: Rising edge + * - Sensor reset deasserted + * - Sensor powered up + * - Pixel clock inversion disabled + * - Sensor master clock polarity disabled + * - Phase counter disabled + */ + mtk_seninf_input_write(input, SENINF_TG1_PH_CNT, 0x0); + + clock_count =3D mtk_seninf_get_clk_divider(priv, input->pad, + fmtinfo->bpp, + num_data_lanes); + if (clock_count < 0) + return clock_count; + + clock_count =3D FIELD_PREP(SENINF_TG1_SEN_CK_CLKCNT, clock_count) | 0x1; + mtk_seninf_input_write(input, SENINF_TG1_SEN_CK, clock_count); + + /* First Enable Sensor interface and select pad (0x1a04_0200) */ + mtk_seninf_input_update(input, SENINF_CTRL, SENINF_EN, 1); + mtk_seninf_input_update(input, SENINF_CTRL, PAD2CAM_DATA_SEL, + SENINF_PAD_10BIT); + mtk_seninf_input_update(input, SENINF_CTRL, SENINF_SRC_SEL, 0); + mtk_seninf_input_update(input, SENINF_CTRL_EXT, SENINF_CSI2_IP_EN, 1); + mtk_seninf_input_update(input, SENINF_CTRL_EXT, SENINF_NCSI2_IP_EN, 0); + + /* DPCM Enable */ + if (fmtinfo->flags & MTK_SENINF_FORMAT_DPCM) + val =3D SENINF_CSI2_DPCM_DI_2A_DPCM_EN; + else + val =3D SENINF_CSI2_DPCM_DI_30_DPCM_EN; + mtk_seninf_input_write(input, SENINF_CSI2_DPCM, val); + + /* Settle delay */ + mtk_seninf_input_update(input, SENINF_CSI2_LNRD_TIMING, + DATA_SETTLE_PARAMETER, SENINF_SETTLE_DELAY); + + /* CSI2 control */ + val =3D mtk_seninf_inuput_read(input, SENINF_CSI2_CTL) + | (FIELD_PREP(SENINF_CSI2_CTL_ED_SEL, + DATA_HEADER_ORDER_DI_WCL_WCH) + | SENINF_CSI2_CTL_CLOCK_LANE_EN | (BIT(num_data_lanes) - 1)); + mtk_seninf_input_write(input, SENINF_CSI2_CTL, val); + + mtk_seninf_input_update(input, SENINF_CSI2_RESYNC_MERGE_CTL, + BYPASS_LANE_RESYNC, 0); + mtk_seninf_input_update(input, SENINF_CSI2_RESYNC_MERGE_CTL, + CDPHY_SEL, 0); + mtk_seninf_input_update(input, SENINF_CSI2_RESYNC_MERGE_CTL, + CPHY_LANE_RESYNC_CNT, 3); + mtk_seninf_input_update(input, SENINF_CSI2_MODE, CSR_CSI2_MODE, 0); + mtk_seninf_input_update(input, SENINF_CSI2_MODE, CSR_CSI2_HEADER_LEN, + 0); + mtk_seninf_input_update(input, SENINF_CSI2_DPHY_SYNC, SYNC_SEQ_MASK_0, + 0xff00); + mtk_seninf_input_update(input, SENINF_CSI2_DPHY_SYNC, SYNC_SEQ_PAT_0, + 0x001d); + + mtk_seninf_input_update(input, SENINF_CSI2_CTL, CLOCK_HS_OPTION, 0); + mtk_seninf_input_update(input, SENINF_CSI2_CTL, HSRX_DET_EN, 0); + mtk_seninf_input_update(input, SENINF_CSI2_CTL, HS_TRAIL_EN, 1); + mtk_seninf_input_update(input, SENINF_CSI2_HS_TRAIL, HS_TRAIL_PARAMETER, + SENINF_HS_TRAIL_PARAMETER); + + /* Set debug port to output packet number */ + mtk_seninf_input_update(input, SENINF_CSI2_DGB_SEL, DEBUG_EN, 1); + mtk_seninf_input_update(input, SENINF_CSI2_DGB_SEL, DEBUG_SEL, 0x1a); + + /* HQ */ + mtk_seninf_input_write(input, SENINF_CSI2_SPARE0, 0xfffffffe); + + /* Reset the CSI2 to commit changes */ + mtk_seninf_input_update(input, SENINF_CTRL, CSI2_SW_RST, 1); + udelay(1); + mtk_seninf_input_update(input, SENINF_CTRL, CSI2_SW_RST, 0); + + return 0; +} + +static void mtk_seninf_mux_setup(struct mtk_seninf_mux *mux, + struct mtk_seninf_input *input, + struct v4l2_subdev_state *state) +{ + const struct mtk_seninf_format_info *fmtinfo; + const struct v4l2_mbus_framefmt *format; + unsigned int pix_sel_ext; + unsigned int pix_sel; + unsigned int hs_pol =3D 0; + unsigned int vs_pol =3D 0; + unsigned int val; + u32 rst_mask; + + format =3D v4l2_subdev_state_get_format(state, input->pad, 0); + fmtinfo =3D mtk_seninf_format_info(format->code); + + /* Enable mux */ + mtk_seninf_mux_update(mux, SENINF_MUX_CTRL, SENINF_MUX_EN, 1); + mtk_seninf_mux_update(mux, SENINF_MUX_CTRL, SENINF_SRC_SEL, + SENINF_MIPI_SENSOR); + mtk_seninf_mux_update(mux, SENINF_MUX_CTRL_EXT, SENINF_SRC_SEL_EXT, + SENINF_NORMAL_MODEL); + + pix_sel_ext =3D 0; + pix_sel =3D 1; + mtk_seninf_mux_update(mux, SENINF_MUX_CTRL_EXT, SENINF_PIX_SEL_EXT, + pix_sel_ext); + mtk_seninf_mux_update(mux, SENINF_MUX_CTRL, SENINF_PIX_SEL, pix_sel); + + if (fmtinfo->flags & MTK_SENINF_FORMAT_JPEG) { + mtk_seninf_mux_update(mux, SENINF_MUX_CTRL, FIFO_FULL_WR_EN, 0); + mtk_seninf_mux_update(mux, SENINF_MUX_CTRL, FIFO_FLUSH_EN, + FIFO_FLUSH_EN_JPEG_2_PIXEL_MODE); + mtk_seninf_mux_update(mux, SENINF_MUX_CTRL, FIFO_PUSH_EN, + FIFO_PUSH_EN_JPEG_2_PIXEL_MODE); + } else { + mtk_seninf_mux_update(mux, SENINF_MUX_CTRL, FIFO_FULL_WR_EN, 2); + mtk_seninf_mux_update(mux, SENINF_MUX_CTRL, FIFO_FLUSH_EN, + FIFO_FLUSH_EN_NORMAL_MODE); + mtk_seninf_mux_update(mux, SENINF_MUX_CTRL, FIFO_PUSH_EN, + FIFO_PUSH_EN_NORMAL_MODE); + } + + mtk_seninf_mux_update(mux, SENINF_MUX_CTRL, SENINF_HSYNC_POL, hs_pol); + mtk_seninf_mux_update(mux, SENINF_MUX_CTRL, SENINF_VSYNC_POL, vs_pol); + + val =3D mtk_seninf_mux_read(mux, SENINF_MUX_CTRL); + rst_mask =3D SENINF_MUX_CTRL_SENINF_IRQ_SW_RST | + SENINF_MUX_CTRL_SENINF_MUX_SW_RST; + + mtk_seninf_mux_write(mux, SENINF_MUX_CTRL, val | rst_mask); + mtk_seninf_mux_write(mux, SENINF_MUX_CTRL, val & ~rst_mask); + + /* HQ */ + val =3D SENINF_FIFO_FULL_SEL; + + /* SPARE field meaning is unknown */ + val |=3D 0xc0000; + mtk_seninf_mux_write(mux, SENINF_MUX_SPARE, val); +} + +static void mtk_seninf_top_mux_setup(struct mtk_seninf *priv, + enum mtk_seninf_id seninf_id, + struct mtk_seninf_mux *mux) +{ + unsigned int val; + + /* + * Use the top mux (from SENINF input to MUX) to configure routing, and + * hardcode a 1:1 mapping from the MUX instances to the SENINF outputs. + */ + val =3D mtk_seninf_read(priv, SENINF_TOP_MUX_CTRL) + & ~(0xf << (mux->mux_id * 4)); + val |=3D (seninf_id & 0xf) << (mux->mux_id * 4); + mtk_seninf_write(priv, SENINF_TOP_MUX_CTRL, val); + + /* + * We currently support only seninf version 3.0 + * where camsv0 and camsv1 are hardwired respectively to + * SENINF_CAM2 and SENINF_CAM3 i.e : + * - SENINF_TOP_CAM_MUX_CTRL[11:8] =3D 0 + * - SENINF_TOP_CAM_MUX_CTRL[15:12] =3D 1 + * so we hardcode it here + */ + mtk_seninf_update(priv, SENINF_TOP_CAM_MUX_CTRL, + SENINF_CAM2_MUX_SRC_SEL, 0); + mtk_seninf_update(priv, SENINF_TOP_CAM_MUX_CTRL, + SENINF_CAM3_MUX_SRC_SEL, 1); +} + +static void seninf_enable_test_pattern(struct mtk_seninf *priv, + struct v4l2_subdev_state *state) +{ + struct mtk_seninf_input *input =3D &priv->inputs[CSI_PORT_0]; + struct mtk_seninf_mux *mux =3D &priv->muxes[0]; + const struct mtk_seninf_format_info *fmtinfo; + const struct v4l2_mbus_framefmt *format; + unsigned int val; + unsigned int pix_sel_ext; + unsigned int pix_sel; + unsigned int hs_pol =3D 0; + unsigned int vs_pol =3D 0; + unsigned int seninf =3D 0; + unsigned int tm_size =3D 0; + unsigned int mux_id =3D mux->mux_id; + + format =3D v4l2_subdev_state_get_format(state, priv->conf->nb_inputs, 0); + fmtinfo =3D mtk_seninf_format_info(format->code); + + mtk_seninf_update(priv, SENINF_TOP_CTRL, MUX_LP_MODE, 0); + + mtk_seninf_update(priv, SENINF_TOP_CTRL, SENINF_PCLK_EN, 1); + mtk_seninf_update(priv, SENINF_TOP_CTRL, SENINF2_PCLK_EN, 1); + + mtk_seninf_input_update(input, SENINF_CTRL, SENINF_EN, 1); + mtk_seninf_input_update(input, SENINF_CTRL, SENINF_SRC_SEL, 1); + mtk_seninf_input_update(input, SENINF_CTRL_EXT, SENINF_TESTMDL_IP_EN, + 1); + + mtk_seninf_input_update(input, SENINF_TG1_TM_CTL, TM_EN, 1); + mtk_seninf_input_update(input, SENINF_TG1_TM_CTL, TM_PAT, 0xc); + mtk_seninf_input_update(input, SENINF_TG1_TM_CTL, TM_VSYNC, 4); + mtk_seninf_input_update(input, SENINF_TG1_TM_CTL, TM_DUMMYPXL, 0x28); + + if (fmtinfo->flags & MTK_SENINF_FORMAT_BAYER) + mtk_seninf_input_update(input, SENINF_TG1_TM_CTL, TM_FMT, 0x0); + else + mtk_seninf_input_update(input, SENINF_TG1_TM_CTL, TM_FMT, 0x1); + + tm_size =3D FIELD_PREP(SENINF_TG1_TM_SIZE_TM_LINE, format->height + 8); + switch (format->code) { + case MEDIA_BUS_FMT_UYVY8_1X16: + case MEDIA_BUS_FMT_VYUY8_1X16: + case MEDIA_BUS_FMT_YUYV8_1X16: + case MEDIA_BUS_FMT_YVYU8_1X16: + tm_size |=3D FIELD_PREP(SENINF_TG1_TM_SIZE_TM_PXL, + format->width * 2); + break; + default: + tm_size |=3D FIELD_PREP(SENINF_TG1_TM_SIZE_TM_PXL, format->width); + break; + } + mtk_seninf_input_write(input, SENINF_TG1_TM_SIZE, tm_size); + + mtk_seninf_input_write(input, SENINF_TG1_TM_CLK, + TEST_MODEL_CLK_DIVIDED_CNT); + mtk_seninf_input_write(input, SENINF_TG1_TM_STP, TIME_STAMP_DIVIDER); + + /* Set top mux */ + val =3D (mtk_seninf_read(priv, SENINF_TOP_MUX_CTRL) + & (~(0xf << (mux_id * 4)))) | + ((seninf & 0xf) << (mux_id * 4)); + mtk_seninf_write(priv, SENINF_TOP_MUX_CTRL, val); + + mtk_seninf_mux_update(mux, SENINF_MUX_CTRL, SENINF_MUX_EN, 1); + mtk_seninf_mux_update(mux, SENINF_MUX_CTRL_EXT, SENINF_SRC_SEL_EXT, + SENINF_TEST_MODEL); + mtk_seninf_mux_update(mux, SENINF_MUX_CTRL, SENINF_SRC_SEL, 1); + + pix_sel_ext =3D 0; + pix_sel =3D 1; + + mtk_seninf_mux_update(mux, SENINF_MUX_CTRL_EXT, + SENINF_PIX_SEL_EXT, pix_sel_ext); + + mtk_seninf_mux_update(mux, SENINF_MUX_CTRL, SENINF_PIX_SEL, pix_sel); + + mtk_seninf_mux_update(mux, SENINF_MUX_CTRL, FIFO_PUSH_EN, 0x1f); + mtk_seninf_mux_update(mux, SENINF_MUX_CTRL, FIFO_FLUSH_EN, 0x1b); + mtk_seninf_mux_update(mux, SENINF_MUX_CTRL, FIFO_FULL_WR_EN, 2); + + mtk_seninf_mux_update(mux, SENINF_MUX_CTRL, SENINF_HSYNC_POL, hs_pol); + mtk_seninf_mux_update(mux, SENINF_MUX_CTRL, SENINF_VSYNC_POL, vs_pol); + mtk_seninf_mux_update(mux, SENINF_MUX_CTRL, SENINF_HSYNC_MASK, 1); + + mtk_seninf_mux_write(mux, SENINF_MUX_INTEN, + SENINF_IRQ_CLR_SEL | SENINF_ALL_ERR_IRQ_EN); + + mtk_seninf_mux_write(mux, SENINF_MUX_CTRL, + mtk_seninf_mux_read(mux, SENINF_MUX_CTRL) | + SENINF_MUX_CTRL_SENINF_IRQ_SW_RST | + SENINF_MUX_CTRL_SENINF_MUX_SW_RST); + udelay(1); + mtk_seninf_mux_write(mux, SENINF_MUX_CTRL, + mtk_seninf_mux_read(mux, SENINF_MUX_CTRL) & + ~(SENINF_MUX_CTRL_SENINF_IRQ_SW_RST | + SENINF_MUX_CTRL_SENINF_MUX_SW_RST)); + + //check this + mtk_seninf_write(priv, SENINF_TOP_CAM_MUX_CTRL, 0x76540010); + /* + * We currently support only seninf version 3.0 + * where camsv0 and camsv1 are hardwired respectively to + * test pattern is valid only for seninf_1 (id 0) i.e : + * - SENINF_TOP_CAM_MUX_CTRL[11:8] =3D 0 + * - SENINF_TOP_CAM_MUX_CTRL[15:12] =3D 0 + * so we hardcode it here + */ + mtk_seninf_update(priv, SENINF_TOP_CAM_MUX_CTRL, + SENINF_CAM2_MUX_SRC_SEL, 0); + mtk_seninf_update(priv, SENINF_TOP_CAM_MUX_CTRL, + SENINF_CAM3_MUX_SRC_SEL, 0); +} + +static int mtk_seninf_start(struct mtk_seninf *priv, + struct v4l2_subdev_state *state, + struct mtk_seninf_input *input, + struct mtk_seninf_mux *mux) +{ + int ret; + + phy_power_on(input->phy); + + mtk_seninf_input_setup_csi2_rx(input); + ret =3D mtk_seninf_input_setup_csi2(priv, input, state); + if (ret) + return ret; + + mtk_seninf_mux_setup(mux, input, state); + mtk_seninf_top_mux_setup(priv, input->seninf_id, mux); + return 0; +} + +static void mtk_seninf_stop(struct mtk_seninf *priv, + struct mtk_seninf_input *input) +{ + unsigned int val; + + /* Disable CSI2(2.5G) first */ + val =3D mtk_seninf_inuput_read(input, SENINF_CSI2_CTL); + val &=3D ~(SENINF_CSI2_CTL_CLOCK_LANE_EN | + SENINF_CSI2_CTL_DATA_LANE3_EN | + SENINF_CSI2_CTL_DATA_LANE2_EN | + SENINF_CSI2_CTL_DATA_LANE1_EN | + SENINF_CSI2_CTL_DATA_LANE0_EN); + mtk_seninf_input_write(input, SENINF_CSI2_CTL, val); + + if (!priv->is_testmode) + phy_power_off(input->phy); +} + +/* -----------------------------------------------------------------------= ------ + * V4L2 Controls + */ + +static int seninf_set_ctrl(struct v4l2_ctrl *ctrl) +{ + struct mtk_seninf *priv =3D container_of(ctrl->handler, + struct mtk_seninf, ctrl_handler); + + switch (ctrl->id) { + case V4L2_CID_TEST_PATTERN: + priv->is_testmode =3D !!ctrl->val; + break; + } + + return 0; +} + +static const struct v4l2_ctrl_ops seninf_ctrl_ops =3D { + .s_ctrl =3D seninf_set_ctrl, +}; + +static const char *const seninf_test_pattern_menu[] =3D { + "No test pattern", + "Static horizontal color bars", +}; + +static int seninf_initialize_controls(struct mtk_seninf *priv) +{ + struct v4l2_ctrl_handler *handler; + int ret; + + handler =3D &priv->ctrl_handler; + ret =3D v4l2_ctrl_handler_init(handler, 2); + if (ret) + return ret; + + v4l2_ctrl_new_std_menu_items(handler, &seninf_ctrl_ops, + V4L2_CID_TEST_PATTERN, + ARRAY_SIZE(seninf_test_pattern_menu) - 1, + 0, 0, seninf_test_pattern_menu); + + priv->is_testmode =3D false; + + if (handler->error) { + ret =3D handler->error; + dev_err(priv->dev, + "Failed to init controls(%d)\n", ret); + v4l2_ctrl_handler_free(handler); + return ret; + } + + priv->subdev.ctrl_handler =3D handler; + + return 0; +} + +/* -----------------------------------------------------------------------= ------ + * V4L2 Subdev Operations + */ +static int seninf_enable_streams(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, u32 pad, + u64 streams_mask) +{ + struct mtk_seninf *priv =3D sd_to_mtk_seninf(sd); + struct mtk_seninf_input *input; + struct mtk_seninf_mux *mux; + struct v4l2_subdev *source; + u32 sink_pad; + int ret; + + /* Stream control can only operate on source pads. */ + if (pad < priv->conf->nb_inputs || + pad >=3D priv->conf->nb_inputs + priv->conf->nb_outputs) + return -EINVAL; + + /* + * Locate the SENINF input and MUX for the source pad. + */ + + ret =3D v4l2_subdev_routing_find_opposite_end(&state->routing, pad, + 0, &sink_pad, NULL); + if (ret) { + dev_dbg(priv->dev, "No sink pad routed to source pad %u\n", + pad); + return ret; + } + + input =3D &priv->inputs[sink_pad]; + mux =3D &priv->muxes[pad - priv->conf->nb_inputs]; + + ret =3D pm_runtime_get_sync(priv->dev); + if (ret < 0) { + dev_err(priv->dev, "Failed to pm_runtime_get_sync: %d\n", ret); + pm_runtime_put_noidle(priv->dev); + return ret; + } + + /* If test mode is enabled, just enable the test pattern generator. */ + if (priv->is_testmode) { + seninf_enable_test_pattern(priv, state); + return 0; + } + + /* Start the SENINF first and then the source. */ + ret =3D mtk_seninf_start(priv, state, input, mux); + if (ret) { + dev_err(priv->dev, "failed to start seninf: %d\n", ret); + return ret; + } + + source =3D input->source_sd; + ret =3D v4l2_subdev_call(source, video, s_stream, 1); + if (ret) { + dev_err(priv->dev, "failed to start source %s: %d\n", + source->entity.name, ret); + mtk_seninf_stop(priv, input); + pm_runtime_put(priv->dev); + } + + return ret; +} + +static int seninf_disable_streams(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, u32 pad, + u64 streams_mask) +{ + struct mtk_seninf *priv =3D sd_to_mtk_seninf(sd); + struct mtk_seninf_input *input; + struct mtk_seninf_mux *mux; + struct v4l2_subdev *source; + u32 sink_pad; + int ret; + + /* Stream control can only operate on source pads. */ + if (pad < priv->conf->nb_inputs || + pad >=3D priv->conf->nb_inputs + priv->conf->nb_outputs) + return -EINVAL; + + /* + * Locate the SENINF input and MUX for the source pad. + * + */ + + ret =3D v4l2_subdev_routing_find_opposite_end(&state->routing, pad, + 0, &sink_pad, NULL); + if (ret) { + dev_dbg(priv->dev, "No sink pad routed to source pad %u\n", + pad); + return ret; + } + + input =3D &priv->inputs[sink_pad]; + mux =3D &priv->muxes[pad - priv->conf->nb_inputs]; + + if (!priv->is_testmode) { + source =3D input->source_sd; + ret =3D v4l2_subdev_call(source, video, s_stream, 0); + if (ret) + dev_err(priv->dev, + "failed to stop source %s: %d\n", + source->entity.name, ret); + } + + mtk_seninf_stop(priv, input); + pm_runtime_put(priv->dev); + return ret; +} + +static const struct v4l2_mbus_framefmt mtk_seninf_default_fmt =3D { + .code =3D SENINF_DEFAULT_BUS_FMT, + .width =3D SENINF_DEFAULT_WIDTH, + .height =3D SENINF_DEFAULT_HEIGHT, + .field =3D V4L2_FIELD_NONE, + .colorspace =3D V4L2_COLORSPACE_SRGB, + .xfer_func =3D V4L2_XFER_FUNC_DEFAULT, + .ycbcr_enc =3D V4L2_YCBCR_ENC_DEFAULT, + .quantization =3D V4L2_QUANTIZATION_DEFAULT, +}; + +static int __seninf_set_routing(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + struct v4l2_subdev_krouting *routing) +{ + int ret; + + ret =3D v4l2_subdev_routing_validate(sd, routing, + V4L2_SUBDEV_ROUTING_ONLY_1_TO_1); + if (ret) + return ret; + + return v4l2_subdev_set_routing_with_fmt(sd, state, routing, + &mtk_seninf_default_fmt); +} + +static int seninf_init_state(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state) +{ + struct mtk_seninf *priv =3D sd_to_mtk_seninf(sd); + struct v4l2_subdev_route routes[SENINF_MAX_NUM_OUTPUTS] =3D { }; + struct v4l2_subdev_krouting routing =3D { + .routes =3D routes, + .num_routes =3D priv->conf->nb_outputs, + }; + unsigned int i; + + /* + * Initialize one route for supported source pads. + * It is a single route from the first sink pad to the source pad, + * while on SENINF 5.0 the routing table will map sink pads to source + * pads connected to CAMSV 1:1 (skipping the first two source pads + * connected to the CAM instances). + */ + for (i =3D 0; i < routing.num_routes; i++) { + struct v4l2_subdev_route *route =3D &routes[i]; + + route->sink_pad =3D i; + route->sink_stream =3D 0; + route->source_pad =3D priv->conf->nb_inputs + i; + route->source_stream =3D 0; + route->flags =3D V4L2_SUBDEV_ROUTE_FL_ACTIVE; + } + + return __seninf_set_routing(sd, state, &routing); +} + +static int seninf_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + struct v4l2_subdev_mbus_code_enum *code) +{ + const struct mtk_seninf_format_info *fmtinfo; + struct mtk_seninf *priv =3D sd_to_mtk_seninf(sd); + + if (code->index >=3D ARRAY_SIZE(mtk_seninf_formats)) + return -EINVAL; + + fmtinfo =3D &mtk_seninf_formats[code->index]; + if (fmtinfo->flags & MTK_SENINF_FORMAT_INPUT_ONLY && + mtk_seninf_pad_is_source(priv, code->pad)) + return -EINVAL; + + code->code =3D fmtinfo->code; + + return 0; +} + +static int seninf_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + struct v4l2_subdev_format *fmt) +{ + struct mtk_seninf *priv =3D sd_to_mtk_seninf(sd); + const struct mtk_seninf_format_info *fmtinfo; + struct v4l2_mbus_framefmt *format; + + /* + * TODO (?): We should disallow setting formats on the source pad + * completely, as the SENINF can't perform any processing. This would + * however break usage of the test pattern generator, as there would be + * no way to configure formats at all when no active input is selected. + */ + + /* + * Default to the first format if the requested media bus code isn't + * supported. + */ + fmtinfo =3D mtk_seninf_format_info(fmt->format.code); + if (!fmtinfo) { + fmtinfo =3D &mtk_seninf_formats[0]; + fmt->format.code =3D fmtinfo->code; + } + + /* Interlaced formats are not supported yet. */ + fmt->format.field =3D V4L2_FIELD_NONE; + + /* Store the format. */ + format =3D v4l2_subdev_state_get_format(state, fmt->pad, fmt->stream); + if (!format) + return -EINVAL; + + *format =3D fmt->format; + + if (mtk_seninf_pad_is_source(priv, fmt->pad)) + return 0; + + /* Propagate the format to the corresponding source pad. */ + format =3D v4l2_subdev_state_get_opposite_stream_format(state, fmt->pad, + fmt->stream); + if (!format) + return -EINVAL; + + *format =3D fmt->format; + + return 0; +} + +static int seninf_set_routing(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + enum v4l2_subdev_format_whence which, + struct v4l2_subdev_krouting *routing) +{ + return __seninf_set_routing(sd, state, routing); +} + +static const struct v4l2_subdev_core_ops seninf_subdev_core_ops =3D { + .subscribe_event =3D v4l2_ctrl_subdev_subscribe_event, + .unsubscribe_event =3D v4l2_event_subdev_unsubscribe, +}; + +static const struct v4l2_subdev_pad_ops seninf_subdev_pad_ops =3D { + .enum_mbus_code =3D seninf_enum_mbus_code, + .get_fmt =3D v4l2_subdev_get_fmt, + .set_fmt =3D seninf_set_fmt, + .link_validate =3D v4l2_subdev_link_validate_default, + .set_routing =3D seninf_set_routing, + .enable_streams =3D seninf_enable_streams, + .disable_streams =3D seninf_disable_streams, +}; + +static const struct v4l2_subdev_ops seninf_subdev_ops =3D { + .core =3D &seninf_subdev_core_ops, + .pad =3D &seninf_subdev_pad_ops, +}; + +static const struct v4l2_subdev_internal_ops seninf_subdev_internal_ops = =3D { + .init_state =3D seninf_init_state, +}; + +/* -----------------------------------------------------------------------= ------ + * Media Entity Operations + */ + +static const struct media_entity_operations seninf_media_ops =3D { + .get_fwnode_pad =3D v4l2_subdev_get_fwnode_pad_1_to_1, + .link_validate =3D v4l2_subdev_link_validate, + .has_pad_interdep =3D v4l2_subdev_has_pad_interdep, +}; + +/* -----------------------------------------------------------------------= ------ + * Async Subdev Notifier + */ + +struct mtk_seninf_async_subdev { + struct v4l2_async_connection asc; + struct mtk_seninf_input *input; + unsigned int port; +}; + +static int mtk_seninf_fwnode_parse(struct device *dev, + unsigned int id) + +{ + static const char * const phy_names[] =3D { + "csi0", "csi1", "csi2", "csi0b" }; + struct mtk_seninf *priv =3D dev_get_drvdata(dev); + struct fwnode_handle *ep, *fwnode; + struct mtk_seninf_input *input; + struct mtk_seninf_async_subdev *asd; + struct v4l2_fwnode_endpoint vep =3D { .bus_type =3D V4L2_MBUS_CSI2_DPHY }; + unsigned int port; + int ret; + + ep =3D fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), id, 0, 0); + if (!ep) + return 0; + + fwnode =3D fwnode_graph_get_remote_endpoint(ep); + ret =3D v4l2_fwnode_endpoint_parse(ep, &vep); + if (ret) { + dev_err(dev, "Failed to parse %p fw\n", to_of_node(fwnode)); + ret =3D -EINVAL; + goto out; + } + + asd =3D v4l2_async_nf_add_fwnode(&priv->notifier, fwnode, + struct mtk_seninf_async_subdev); + if (IS_ERR(asd)) { + ret =3D PTR_ERR(asd); + goto out; + } + + port =3D vep.base.port; + asd->port =3D port; + + if (mtk_seninf_pad_is_source(priv, port)) { + ret =3D 0; + goto out; + } + + input =3D &priv->inputs[port]; + + input->pad =3D port; + input->seninf_id =3D port_to_seninf_id[port]; + input->base =3D priv->base + 0x1000 * input->seninf_id; + input->seninf =3D priv; + + input->bus =3D vep.bus.mipi_csi2; + + input->phy =3D devm_phy_get(dev, phy_names[port]); + if (IS_ERR(input->phy)) { + dev_err(dev, "failed to get phy: %ld\n", PTR_ERR(input->phy)); + ret =3D PTR_ERR(input->phy); + goto out; + } + input->phy_mode =3D SENINF_PHY_MODE_4D1C; + + asd->input =3D input; + + ret =3D 0; +out: + fwnode_handle_put(ep); + fwnode_handle_put(fwnode); + return ret; +} + +static int mtk_seninf_notifier_bound(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *sd, + struct v4l2_async_connection *asc) +{ + struct mtk_seninf *priv =3D container_of(notifier, struct mtk_seninf, + notifier); + struct mtk_seninf_async_subdev *asd =3D + container_of(asc, struct mtk_seninf_async_subdev, asc); + struct device_link *link; + int ret; + + dev_dbg(priv->dev, "%s bound to SENINF port %u\n", sd->entity.name, + asd->port); + + if (mtk_seninf_pad_is_sink(priv, asd->port)) { + struct mtk_seninf_input *input =3D asd->input; + + input->source_sd =3D sd; + + link =3D device_link_add(priv->dev, sd->dev, + DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); + if (!link) { + dev_err(priv->dev, + "Failed to create device link from source %s\n", + sd->name); + return -EINVAL; + } + + ret =3D v4l2_create_fwnode_links_to_pad(sd, + &priv->pads[input->pad], + MEDIA_LNK_FL_IMMUTABLE | + MEDIA_LNK_FL_ENABLED); + } else { + link =3D device_link_add(sd->dev, priv->dev, + DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); + if (!link) { + dev_err(priv->dev, + "Failed to create device link to output %s\n", + sd->name); + return -EINVAL; + } + + ret =3D v4l2_create_fwnode_links_to_pad(&priv->subdev, + &sd->entity.pads[0], + MEDIA_LNK_FL_IMMUTABLE | + MEDIA_LNK_FL_ENABLED); + } + if (ret) { + dev_err(priv->dev, "Failed to create links between SENINF port %u and %s= (%d)\n", + asd->port, sd->entity.name, ret); + return ret; + } + + return 0; +} + +static int mtk_seninf_notifier_complete(struct v4l2_async_notifier *notifi= er) +{ + struct mtk_seninf *priv =3D container_of(notifier, struct mtk_seninf, + notifier); + int ret; + + ret =3D v4l2_device_register_subdev_nodes(&priv->v4l2_dev); + if (ret) { + dev_err(priv->dev, "Failed to register subdev nodes: %d\n", + ret); + return ret; + } + + return 0; +} + +static const struct v4l2_async_notifier_operations mtk_seninf_async_ops = =3D { + .bound =3D mtk_seninf_notifier_bound, + .complete =3D mtk_seninf_notifier_complete, +}; + +static int mtk_seninf_media_init(struct mtk_seninf *priv) +{ + struct media_device *media_dev =3D &priv->media_dev; + const struct mtk_seninf_conf *conf =3D priv->conf; + unsigned int num_pads =3D conf->nb_outputs + conf->nb_inputs; + struct media_pad *pads =3D priv->pads; + struct device *dev =3D priv->dev; + unsigned int i; + int ret; + + media_dev->dev =3D dev; + strscpy(media_dev->model, conf->model, sizeof(media_dev->model)); + media_dev->hw_revision =3D 0; + media_device_init(media_dev); + + for (i =3D 0; i < conf->nb_inputs; i++) + pads[i].flags =3D MEDIA_PAD_FL_SINK; + for (i =3D conf->nb_inputs; i < num_pads; i++) + pads[i].flags =3D MEDIA_PAD_FL_SOURCE; + + ret =3D media_entity_pads_init(&priv->subdev.entity, num_pads, pads); + if (ret) { + media_device_cleanup(media_dev); + return ret; + } + + return 0; +} + +static int mtk_seninf_v4l2_async_register(struct mtk_seninf *priv) +{ + const struct mtk_seninf_conf *conf =3D priv->conf; + struct device *dev =3D priv->dev; + unsigned int i; + int ret; + + v4l2_async_nf_init(&priv->notifier, &priv->v4l2_dev); + + for (i =3D 0; i < conf->nb_inputs + conf->nb_outputs; ++i) { + ret =3D mtk_seninf_fwnode_parse(dev, i); + + if (ret) { + dev_err(dev, + "Failed to parse endpoint at port %d: %d\n", + i, ret); + goto err_clean_notififer; + } + } + + priv->notifier.ops =3D &mtk_seninf_async_ops; + ret =3D v4l2_async_nf_register(&priv->notifier); + if (ret) { + dev_err(dev, "Failed to register async notifier: %d\n", ret); + goto err_clean_notififer; + } + return 0; + +err_clean_notififer: + v4l2_async_nf_cleanup(&priv->notifier); + + return ret; +} + +static int mtk_seninf_v4l2_register(struct mtk_seninf *priv) +{ + struct v4l2_subdev *sd =3D &priv->subdev; + struct device *dev =3D priv->dev; + int ret; + + /* Initialize media device & pads. */ + ret =3D mtk_seninf_media_init(priv); + if (ret) + return ret; + + /* Initialize & register v4l2 device. */ + priv->v4l2_dev.mdev =3D &priv->media_dev; + + ret =3D v4l2_device_register(dev, &priv->v4l2_dev); + if (ret) { + dev_err_probe(dev, ret, "Failed to register V4L2 device\n"); + goto err_clean_media; + } + + /* Initialize & register subdev. */ + v4l2_subdev_init(sd, &seninf_subdev_ops); + sd->internal_ops =3D &seninf_subdev_internal_ops; + sd->dev =3D dev; + sd->entity.function =3D MEDIA_ENT_F_VID_IF_BRIDGE; + sd->entity.ops =3D &seninf_media_ops; + sd->flags |=3D V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS | + V4L2_SUBDEV_FL_STREAMS; + strscpy(sd->name, dev_name(dev), sizeof(sd->name)); + ret =3D seninf_initialize_controls(priv); + if (ret) { + dev_err_probe(dev, ret, "Failed to initialize controls\n"); + goto err_unreg_v4l2; + } + v4l2_set_subdevdata(sd, priv); + + ret =3D v4l2_subdev_init_finalize(sd); + if (ret) + goto err_free_handler; + + ret =3D v4l2_device_register_subdev(&priv->v4l2_dev, sd); + if (ret) { + dev_err_probe(dev, ret, "Failed to register subdev\n"); + goto err_cleanup_subdev; + } + + /* Set up async device */ + ret =3D mtk_seninf_v4l2_async_register(priv); + if (ret) { + dev_err_probe(dev, ret, + "Failed to register v4l2 async notifier\n"); + goto err_unreg_subdev; + } + + /* Register media device */ + ret =3D media_device_register(&priv->media_dev); + if (ret) { + dev_err_probe(dev, ret, "Failed to register media device\n"); + goto err_unreg_notifier; + } + + return 0; + +err_unreg_notifier: + v4l2_async_nf_unregister(&priv->notifier); +err_unreg_subdev: + v4l2_device_unregister_subdev(sd); +err_cleanup_subdev: + v4l2_subdev_cleanup(sd); +err_free_handler: + v4l2_ctrl_handler_free(&priv->ctrl_handler); +err_unreg_v4l2: + v4l2_device_unregister(&priv->v4l2_dev); +err_clean_media: + media_entity_cleanup(&sd->entity); + media_device_cleanup(&priv->media_dev); + + return ret; +} + +static int seninf_pm_suspend(struct device *dev) +{ + struct mtk_seninf *priv =3D dev_get_drvdata(dev); + + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + + return 0; +} + +static int seninf_pm_resume(struct device *dev) +{ + struct mtk_seninf *priv =3D dev_get_drvdata(dev); + int ret; + + ret =3D clk_bulk_prepare_enable(priv->num_clks, priv->clks); + if (ret) { + dev_err(dev, "failed to enable clock: %d\n", ret); + return ret; + } + + mtk_seninf_csi2_setup_phy(priv); + + return 0; +} + +static const struct dev_pm_ops runtime_pm_ops =3D { + SET_RUNTIME_PM_OPS(seninf_pm_suspend, seninf_pm_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; + +static int seninf_probe(struct platform_device *pdev) +{ + static const char * const clk_names[] =3D { "camsys", "top_mux" }; + struct device *dev =3D &pdev->dev; + struct mtk_seninf *priv; + unsigned int i; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->conf =3D device_get_match_data(dev); + + dev_set_drvdata(dev, priv); + priv->dev =3D dev; + + priv->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->num_clks =3D ARRAY_SIZE(clk_names); + priv->clks =3D devm_kcalloc(dev, priv->num_clks, + sizeof(*priv->clks), GFP_KERNEL); + if (!priv->clks) + return -ENOMEM; + + for (i =3D 0; i < priv->num_clks; ++i) + priv->clks[i].id =3D clk_names[i]; + + ret =3D devm_clk_bulk_get(dev, priv->num_clks, priv->clks); + if (ret) + return dev_err_probe(dev, ret, "Failed to get seninf clock\n"); + + for (i =3D 0; i < priv->conf->nb_muxes; ++i) { + struct mtk_seninf_mux *mux =3D &priv->muxes[i]; + + mux->pad =3D priv->conf->nb_inputs + i; + mux->mux_id =3D i; + mux->base =3D priv->base + 0x1000 * i; + mux->seninf =3D priv; + } + + devm_pm_runtime_enable(dev); + + ret =3D mtk_seninf_v4l2_register(priv); + return ret; +} + +static void seninf_remove(struct platform_device *pdev) +{ + struct mtk_seninf *priv =3D dev_get_drvdata(&pdev->dev); + + media_device_unregister(&priv->media_dev); + media_device_cleanup(&priv->media_dev); + v4l2_async_nf_unregister(&priv->notifier); + v4l2_async_nf_cleanup(&priv->notifier); + v4l2_device_unregister_subdev(&priv->subdev); + v4l2_subdev_cleanup(&priv->subdev); + v4l2_ctrl_handler_free(&priv->ctrl_handler); + media_entity_cleanup(&priv->subdev.entity); + v4l2_device_unregister(&priv->v4l2_dev); +} + +static const struct mtk_seninf_conf seninf_8365_conf =3D { + .model =3D "mtk-camsys-3.0", + .nb_inputs =3D 4, + .nb_muxes =3D 6, + .nb_outputs =3D 4, +}; + +static const struct of_device_id mtk_seninf_of_match[] =3D { + { .compatible =3D "mediatek,mt8365-seninf", .data =3D &seninf_8365_conf }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, mtk_seninf_of_match); + +static struct platform_driver seninf_pdrv =3D { + .driver =3D { + .name =3D "mtk-seninf", + .pm =3D &runtime_pm_ops, + .of_match_table =3D mtk_seninf_of_match, + }, + .probe =3D seninf_probe, + .remove =3D seninf_remove, +}; + +module_platform_driver(seninf_pdrv); + +MODULE_DESCRIPTION("MTK sensor interface driver"); +MODULE_AUTHOR("Louis Kuo "); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/platform/mediatek/isp/mtk_seninf_reg.h b/drivers= /media/platform/mediatek/isp/mtk_seninf_reg.h new file mode 100644 index 0000000000000000000000000000000000000000..1f13755ab2f0239b0ab7ed20052= 3da5a7b773d1b --- /dev/null +++ b/drivers/media/platform/mediatek/isp/mtk_seninf_reg.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022 MediaTek Inc. + */ + +#ifndef __SENINF_REG_H__ +#define __SENINF_REG_H__ + +#include + +#define SENINF_TOP_CTRL 0x0000 +#define SENINF_TOP_CTRL_MUX_LP_MODE BIT(31) +#define SENINF_TOP_CTRL_SENINF_PCLK_EN BIT(10) +#define SENINF_TOP_CTRL_SENINF2_PCLK_EN BIT(11) +#define SENINF_TOP_MUX_CTRL 0x0008 +#define SENINF_TOP_CAM_MUX_CTRL 0x0010 +#define SENINF_TOP_CAM_MUX_CTRL_SENINF_CAM2_MUX_SRC_SEL GENMASK(11, 8) +#define SENINF_TOP_CAM_MUX_CTRL_SENINF_CAM3_MUX_SRC_SEL GENMASK(15, 12) +#define SENINF_TOP_PHY_SENINF_CTL_CSI0 0x001c +#define SENINF_TOP_PHY_SENINF_CTL_CSI0_DPHY_MODE BIT(0) +#define SENINF_TOP_PHY_SENINF_CTL_CSI0_CK_SEL_1 GENMASK(10, 8) +#define SENINF_TOP_PHY_SENINF_CTL_CSI0_CK_SEL_2 GENMASK(13, 12) +#define SENINF_TOP_PHY_SENINF_CTL_CSI0_PHY_SENINF_LANE_MUX_CSI0_EN BIT(31) +#define SENINF_TOP_PHY_SENINF_CTL_CSI1 0x0020 +#define SENINF_TOP_PHY_SENINF_CTL_CSI1_DPHY_MODE BIT(0) +#define SENINF_TOP_PHY_SENINF_CTL_CSI1_CK_SEL_1 GENMASK(10, 8) +#define SENINF_TOP_PHY_SENINF_CTL_CSI1_PHY_SENINF_LANE_MUX_CSI1_EN BIT(31) +#define SENINF_CTRL 0x0200 +#define SENINF_CTRL_SENINF_EN BIT(0) +#define SENINF_CTRL_CSI2_SW_RST BIT(7) +#define SENINF_CTRL_SENINF_SRC_SEL GENMASK(14, 12) +#define SENINF_CTRL_PAD2CAM_DATA_SEL GENMASK(30, 28) +#define SENINF_CTRL_EXT 0x0204 +#define SENINF_CTRL_EXT_SENINF_TESTMDL_IP_EN BIT(1) +#define SENINF_CTRL_EXT_SENINF_NCSI2_IP_EN BIT(5) +#define SENINF_CTRL_EXT_SENINF_CSI2_IP_EN BIT(6) +#define SENINF_TG1_PH_CNT 0x0600 +#define SENINF_TG1_SEN_CK 0x0604 +#define SENINF_TG1_SEN_CK_CLKCNT GENMASK(21, 16) +#define SENINF_TG1_TM_CTL 0x0608 +#define SENINF_TG1_TM_CTL_TM_EN BIT(0) +#define SENINF_TG1_TM_CTL_TM_FMT BIT(2) +#define SENINF_TG1_TM_CTL_TM_PAT GENMASK(7, 4) +#define SENINF_TG1_TM_CTL_TM_VSYNC GENMASK(15, 8) +#define SENINF_TG1_TM_CTL_TM_DUMMYPXL GENMASK(23, 16) +#define SENINF_TG1_TM_SIZE 0x060c +#define SENINF_TG1_TM_SIZE_TM_LINE GENMASK(29, 16) +#define SENINF_TG1_TM_SIZE_TM_PXL GENMASK(12, 0) +#define SENINF_TG1_TM_CLK 0x0610 +#define TEST_MODEL_CLK_DIVIDED_CNT 8 +#define SENINF_TG1_TM_STP 0x0614 +#define TIME_STAMP_DIVIDER 1 +#define MIPI_RX_CON24_CSI0 0x0824 +#define MIPI_RX_CON24_CSI0_CSI0_BIST_LN0_MUX GENMASK(25, 24) +#define MIPI_RX_CON24_CSI0_CSI0_BIST_LN1_MUX GENMASK(27, 26) +#define MIPI_RX_CON24_CSI0_CSI0_BIST_LN2_MUX GENMASK(29, 28) +#define MIPI_RX_CON24_CSI0_CSI0_BIST_LN3_MUX GENMASK(31, 30) +#define SENINF_CSI2_CTL 0x0a00 +#define SENINF_CSI2_CTL_DATA_LANE0_EN BIT(0) +#define SENINF_CSI2_CTL_DATA_LANE1_EN BIT(1) +#define SENINF_CSI2_CTL_DATA_LANE2_EN BIT(2) +#define SENINF_CSI2_CTL_DATA_LANE3_EN BIT(3) +#define SENINF_CSI2_CTL_CLOCK_LANE_EN BIT(4) +#define SENINF_CSI2_CTL_HSRX_DET_EN BIT(7) +#define SENINF_CSI2_CTL_ED_SEL BIT(16) +#define DATA_HEADER_ORDER_DI_WCL_WCH 1 +#define SENINF_CSI2_CTL_HS_TRAIL_EN BIT(25) +#define SENINF_CSI2_CTL_CLOCK_HS_OPTION BIT(27) +#define SENINF_CSI2_LNRD_TIMING 0x0a08 +#define SENINF_CSI2_LNRD_TIMING_DATA_SETTLE_PARAMETER GENMASK(15, 8) +#define SENINF_CSI2_DPCM 0x0a0c +#define SENINF_CSI2_DPCM_DI_30_DPCM_EN BIT(7) +#define SENINF_CSI2_DPCM_DI_2A_DPCM_EN BIT(15) +#define SENINF_CSI2_DGB_SEL 0x0a18 +#define SENINF_CSI2_DGB_SEL_DEBUG_SEL GENMASK(7, 0) +#define SENINF_CSI2_DGB_SEL_DEBUG_EN BIT(31) +#define SENINF_CSI2_SPARE0 0x0a20 +#define SENINF_CSI2_LNRC_FSM 0x0a28 +#define SENINF_CSI2_HS_TRAIL 0x0a40 +#define SENINF_CSI2_HS_TRAIL_HS_TRAIL_PARAMETER GENMASK(7, 0) +#define SENINF_CSI2_RESYNC_MERGE_CTL 0x0a74 +#define SENINF_CSI2_RESYNC_MERGE_CTL_CPHY_LANE_RESYNC_CNT GENMASK(2, 0) +#define SENINF_CSI2_RESYNC_MERGE_CTL_BYPASS_LANE_RESYNC BIT(10) +#define SENINF_CSI2_RESYNC_MERGE_CTL_CDPHY_SEL BIT(11) +#define SENINF_CSI2_MODE 0x0ae8 +#define SENINF_CSI2_MODE_CSR_CSI2_MODE GENMASK(7, 0) +#define SENINF_CSI2_MODE_CSR_CSI2_HEADER_LEN GENMASK(10, 8) +#define SENINF_CSI2_DPHY_SYNC 0x0b20 +#define SENINF_CSI2_DPHY_SYNC_SYNC_SEQ_MASK_0 GENMASK(15, 0) +#define SENINF_CSI2_DPHY_SYNC_SYNC_SEQ_PAT_0 GENMASK(31, 16) +#define SENINF_MUX_CTRL 0x0d00 +#define SENINF_MUX_CTRL_SENINF_MUX_SW_RST BIT(0) +#define SENINF_MUX_CTRL_SENINF_IRQ_SW_RST BIT(1) +#define SENINF_MUX_CTRL_SENINF_HSYNC_MASK BIT(7) +#define SENINF_MUX_CTRL_SENINF_PIX_SEL BIT(8) +#define SENINF_MUX_CTRL_SENINF_VSYNC_POL BIT(9) +#define SENINF_MUX_CTRL_SENINF_HSYNC_POL BIT(10) +#define SENINF_MUX_CTRL_SENINF_SRC_SEL GENMASK(15, 12) +#define SENINF_MUX_CTRL_FIFO_PUSH_EN GENMASK(21, 16) +#define FIFO_PUSH_EN_NORMAL_MODE 0x1f +#define FIFO_PUSH_EN_JPEG_2_PIXEL_MODE 0x1e +#define SENINF_MUX_CTRL_FIFO_FLUSH_EN GENMASK(28, 22) +#define FIFO_FLUSH_EN_NORMAL_MODE 0x1b +#define FIFO_FLUSH_EN_JPEG_2_PIXEL_MODE 0x18 +#define SENINF_MUX_CTRL_FIFO_FULL_WR_EN GENMASK(29, 28) +#define SENINF_MUX_CTRL_SENINF_MUX_EN BIT(31) +#define SENINF_MUX_INTEN 0x0d04 +#define SENINF_MUX_SPARE 0x0d2c +#define SENINF_FIFO_FULL_SEL BIT(13) +#define SENINF_MUX_CTRL_EXT 0x0d3c +#define SENINF_MUX_CTRL_EXT_SENINF_SRC_SEL_EXT GENMASK(1, 0) +#define SENINF_MUX_CTRL_EXT_SENINF_PIX_SEL_EXT BIT(4) + +#endif /* __SENINF_REG_H__ */ --=20 2.47.0 From nobody Sun Nov 24 05:51:41 2024 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EECE1CB30B for ; Thu, 21 Nov 2024 08:53:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732179208; cv=none; b=cL/T9kNVDLAW9btBLDVqqMb0V/cmVk7Dt1819ftI17LPGaWaB2Xz81QqNAfUX2h4vFNZyOIz85BkbJufUZPADACPcGFQ35pDUwdyDMX3CCOMZ5RQ6RjKCT1bvfOMZoZHU+GOz0UIUQO1XjrXPKDkxNQgz+6EOS4C85LXX+sHdQw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732179208; c=relaxed/simple; bh=6n+S86RoAdZIZuJDPBq9B3e25CXEVJL86rH0qyqrJnI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cAxGQsH+xL6yVGl7Zk1pgEzqaJVq9VezLpvFmrnHzYIVCjBojm7/9BmjfDYCMdnjYczH0tImF/GlKhstODJ0uL5ba3IEjLoyGJpXaHMAu3g2pRuwpo+OUgfs/izBq9/hNKYvgfs3HVfLenmkwak+mRV/QXS0F9LFYWv6wXdflGw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=QiPgBBRQ; arc=none smtp.client-ip=209.85.221.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="QiPgBBRQ" Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-382325b0508so448326f8f.3 for ; Thu, 21 Nov 2024 00:53:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1732179201; x=1732784001; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=0OSbfoYQsoE2dZGYChQCk9jjihU6c6NuuyWsfj1aseQ=; b=QiPgBBRQOBFtiYATENPRxgwAoKmtSw/+FlZpuTdWkvXxvOLSr3J6hGQNaz25HWgFpS Ygj7rmynul8gziWPiKOVFPP1Q6g4LNKEthzmJpGpsCDNyau1zlLHA2A1gHRiSh1tDtaH NBiXXlVf8duOejSDx+FXQHm6nWZ+cjtXMpd0aIL3cgz7uUlN9MS9Q5Qom/HOrjtVF9EE gnWjSlfzJ2NXI3XVa3C7iSbURYaG1sEePq8IX0D/Ynt/6lmQOkykHee8q6DnChpBaV0X UzIRj5gxw2Bo1lDMAm3gPnWflXVoJDCdRY6krZHv/CTVMBFHVb3bPJMV1ZoxWgoFKwFp DP8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732179201; x=1732784001; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0OSbfoYQsoE2dZGYChQCk9jjihU6c6NuuyWsfj1aseQ=; b=MvBayIa5VY3mXyr4uYApNGBgB+Xr+iCNOFNb15O8tt97IB//Qkbc7Ydbb4W38TAg7f mQlTQNubOvuqAETeXTQ9PZCYVcl5qebTKVxL3APF4QsRt9zNNaN48M+2XtLZnd3yBX3X P5XjWvlmeLCkrdoq5/HmWlJFK2T1XhTTBxfMbNNV2C3GR36KZ1YJAADjq3Nivn/pzKOb wrQjJ9gSk5EtU8diDn9NsyQRaNYoL0mItojBYS/oQbyNX0hTxnZGreYGq+En5VxU0ilz d36ZN3AZTw6NK6hsYp6ITAzICGhBaTSBBU9OvEdjJvVDa4lsVjSQD1Zo31dNi9oXzNJF IrrA== X-Forwarded-Encrypted: i=1; AJvYcCX05xRxw8A5HEDgbpc7yifzM9OiOtBo/J394TqswCLJ3xhP/BSJ8rM0LfI6nhJFQUliSOeCDwbY/RkyS5A=@vger.kernel.org X-Gm-Message-State: AOJu0YwB7KgOi5W9jac6FNSuRVTllsLoSwGE0irj2L9WoNh2DP81KaOL YrqecPPobu87ODIi4YqFvyhjEgTy1/SSCZJUzdA4NEbN+cYhRibdpuC4gO7HhAs= X-Google-Smtp-Source: AGHT+IEcAv3GRZwseuzL0YCWZg0w8k962U2tdmxbozyTY4fRwzpVpwqF+C9HcEjnZKWef7e7goJWmg== X-Received: by 2002:a05:6000:1787:b0:382:588d:90ae with SMTP id ffacd0b85a97d-382588d9382mr2659960f8f.15.1732179200377; Thu, 21 Nov 2024 00:53:20 -0800 (PST) Received: from [192.168.42.0] (2a02-842a-d52e-6101-6fd0-06c4-5d68-f0a5.rev.sfr.net. [2a02:842a:d52e:6101:6fd0:6c4:5d68:f0a5]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-382549111fdsm4219900f8f.58.2024.11.21.00.53.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2024 00:53:20 -0800 (PST) From: Julien Stephan Date: Thu, 21 Nov 2024 09:53:18 +0100 Subject: [PATCH v7 4/5] media: platform: mediatek: isp: add mediatek ISP3.0 camsv Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241121-add-mtk-isp-3-0-support-v7-4-b04dc9610619@baylibre.com> References: <20241121-add-mtk-isp-3-0-support-v7-0-b04dc9610619@baylibre.com> In-Reply-To: <20241121-add-mtk-isp-3-0-support-v7-0-b04dc9610619@baylibre.com> To: Laurent Pinchart , Andy Hsieh , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Julien Stephan , Phi-bang Nguyen , Florian Sylvestre , Paul Elder X-Mailer: b4 0.14.2 From: Phi-bang Nguyen This driver provides a path to bypass the SoC ISP so that image data coming from the SENINF can go directly into memory without any image processing. This allows the use of an external ISP. Signed-off-by: Phi-bang Nguyen Signed-off-by: Florian Sylvestre [Paul Elder fix irq locking] Signed-off-by: Paul Elder Co-developed-by: Laurent Pinchart Signed-off-by: Laurent Pinchart Co-developed-by: Julien Stephan Signed-off-by: Julien Stephan --- drivers/media/platform/mediatek/isp/Kconfig | 18 + drivers/media/platform/mediatek/isp/Makefile | 5 + drivers/media/platform/mediatek/isp/mtk_camsv.c | 275 ++++++++ drivers/media/platform/mediatek/isp/mtk_camsv.h | 170 +++++ .../media/platform/mediatek/isp/mtk_camsv30_hw.c | 539 ++++++++++++++++ .../media/platform/mediatek/isp/mtk_camsv_video.c | 701 +++++++++++++++++= ++++ 6 files changed, 1708 insertions(+) diff --git a/drivers/media/platform/mediatek/isp/Kconfig b/drivers/media/pl= atform/mediatek/isp/Kconfig index 2a3cef81d15aa12633ade2f3be0bba36b9af62e1..2b89efc7ba9aa6b85f850bb8ec9= 38cde581f31a2 100644 --- a/drivers/media/platform/mediatek/isp/Kconfig +++ b/drivers/media/platform/mediatek/isp/Kconfig @@ -1,4 +1,22 @@ # SPDX-License-Identifier: GPL-2.0-only +config MTK_CAMSV30 + tristate "MediaTek ISP3.0 CAMSV driver" + depends on ARCH_MEDIATEK || COMPILE_TEST + depends on OF + depends on PM + select MEDIA_CONTROLLER + select MTK_SENINF30 + select VIDEO_V4L2_SUBDEV_API + select VIDEOBUF2_DMA_CONTIG + select VIDEOBUF2_VMALLOC + default n + help + This driver provides a path to bypass the SoC ISP so that + image data come from the SENINF can go directly into memory + without any image processing. + To compile this driver as a module, choose M here: the + module will be called mtk-camsv30. + config MTK_SENINF30 tristate "MediaTek ISP3.0 SENINF driver" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/media/platform/mediatek/isp/Makefile b/drivers/media/p= latform/mediatek/isp/Makefile index 375d720f9ed75e2197bb723bdce9bc0472e62842..e7205759fe9bc27bd5146c490b9= 3db72deb3767f 100644 --- a/drivers/media/platform/mediatek/isp/Makefile +++ b/drivers/media/platform/mediatek/isp/Makefile @@ -1,4 +1,9 @@ # SPDX-License-Identifier: GPL-2.0 =20 +mtk-camsv30-objs +=3D mtk_camsv.o +mtk-camsv30-objs +=3D mtk_camsv30_hw.o +mtk-camsv30-objs +=3D mtk_camsv_video.o +obj-$(CONFIG_MTK_CAMSV30) +=3D mtk-camsv30.o + mtk-seninf-objs +=3D mtk_seninf.o obj-$(CONFIG_MTK_SENINF30) +=3D mtk-seninf.o diff --git a/drivers/media/platform/mediatek/isp/mtk_camsv.c b/drivers/medi= a/platform/mediatek/isp/mtk_camsv.c new file mode 100644 index 0000000000000000000000000000000000000000..a02a1c226ee6164db08d18d6927= d35ac86eaa8cc --- /dev/null +++ b/drivers/media/platform/mediatek/isp/mtk_camsv.c @@ -0,0 +1,275 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 BayLibre + * Copyright (c) 2022 MediaTek Inc. + */ + +#include +#include + +#include "mtk_camsv.h" + +static inline struct mtk_cam_dev *to_mtk_cam_dev(struct v4l2_subdev *sd) +{ + return container_of(sd, struct mtk_cam_dev, subdev); +} + +static const u32 mtk_cam_mbus_formats[] =3D { + MEDIA_BUS_FMT_SBGGR8_1X8, + MEDIA_BUS_FMT_SGBRG8_1X8, + MEDIA_BUS_FMT_SGRBG8_1X8, + MEDIA_BUS_FMT_SRGGB8_1X8, + MEDIA_BUS_FMT_SBGGR10_1X10, + MEDIA_BUS_FMT_SGBRG10_1X10, + MEDIA_BUS_FMT_SGRBG10_1X10, + MEDIA_BUS_FMT_SRGGB10_1X10, + MEDIA_BUS_FMT_SBGGR12_1X12, + MEDIA_BUS_FMT_SGBRG12_1X12, + MEDIA_BUS_FMT_SGRBG12_1X12, + MEDIA_BUS_FMT_SRGGB12_1X12, + MEDIA_BUS_FMT_UYVY8_1X16, + MEDIA_BUS_FMT_VYUY8_1X16, + MEDIA_BUS_FMT_YUYV8_1X16, + MEDIA_BUS_FMT_YVYU8_1X16, +}; + +/* -----------------------------------------------------------------------= ------ + * V4L2 Subdev Operations + */ + +static int mtk_cam_init_state(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state) +{ + static const struct v4l2_mbus_framefmt def_format =3D { + .code =3D MEDIA_BUS_FMT_SGRBG10_1X10, + .width =3D IMG_MAX_WIDTH, + .height =3D IMG_MAX_HEIGHT, + .field =3D V4L2_FIELD_NONE, + .colorspace =3D V4L2_COLORSPACE_SRGB, + .xfer_func =3D V4L2_XFER_FUNC_DEFAULT, + .ycbcr_enc =3D V4L2_YCBCR_ENC_DEFAULT, + .quantization =3D V4L2_QUANTIZATION_DEFAULT, + }; + struct v4l2_mbus_framefmt *format; + unsigned int i; + + for (i =3D 0; i < sd->entity.num_pads; i++) { + format =3D v4l2_subdev_state_get_format(sd_state, i); + *format =3D def_format; + } + + return 0; +} + +static int mtk_cam_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index >=3D ARRAY_SIZE(mtk_cam_mbus_formats)) + return -EINVAL; + + code->code =3D mtk_cam_mbus_formats[code->index]; + + return 0; +} + +static int mtk_cam_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + struct v4l2_mbus_framefmt *format; + unsigned int i; + + /* + * We only support pass-through mode, the format on source pads can't + * be modified. + */ + if (fmt->pad !=3D MTK_CAM_CIO_PAD_SENINF) + return -EINVAL; + + for (i =3D 0; i < ARRAY_SIZE(mtk_cam_mbus_formats); ++i) { + if (mtk_cam_mbus_formats[i] =3D=3D fmt->format.code) + break; + } + + if (i =3D=3D ARRAY_SIZE(mtk_cam_mbus_formats)) + fmt->format.code =3D mtk_cam_mbus_formats[0]; + + format =3D v4l2_subdev_state_get_format(sd_state, fmt->pad); + format->width =3D clamp_t(u32, fmt->format.width, + IMG_MIN_WIDTH, IMG_MAX_WIDTH); + format->height =3D clamp_t(u32, fmt->format.height, + IMG_MIN_HEIGHT, IMG_MAX_HEIGHT); + format->code =3D fmt->format.code; + + fmt->format =3D *format; + + /* Propagate the format to the source pad. */ + format =3D v4l2_subdev_state_get_format(sd_state, MTK_CAM_CIO_PAD_VIDEO); + format->width =3D fmt->format.width; + format->height =3D fmt->format.height; + format->code =3D fmt->format.code; + + return 0; +} + +static int mtk_cam_subdev_registered(struct v4l2_subdev *sd) +{ + struct mtk_cam_dev *cam =3D to_mtk_cam_dev(sd); + + /* Create the video device and link. */ + return mtk_cam_video_register(cam); +} + +static int camsv_enable_streams(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, u32 pad, + u64 streams_mask) +{ + struct mtk_cam_dev *cam =3D to_mtk_cam_dev(sd); + struct v4l2_subdev *seninf; + int ret; + + if (!cam->seninf) { + cam->seninf =3D media_pad_remote_pad_first(&cam->subdev_pads[MTK_CAM_CIO= _PAD_SENINF]); + if (!cam->seninf) { + dev_err(cam->dev, "No SENINF connected\n"); + return -ENOLINK; + } + } + + seninf =3D media_entity_to_v4l2_subdev(cam->seninf->entity); + + /* Seninf must stream on first */ + ret =3D v4l2_subdev_enable_streams(seninf, cam->seninf->index, BIT(0)); + if (ret) { + dev_err(cam->dev, "failed to stream on %s:%d\n", + seninf->entity.name, ret); + return ret; + } + + return 0; +} + +static int camsv_disable_streams(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, u32 pad, + u64 streams_mask) +{ + struct mtk_cam_dev *cam =3D to_mtk_cam_dev(sd); + struct v4l2_subdev *seninf; + int ret; + + if (cam->seninf) { + seninf =3D media_entity_to_v4l2_subdev(cam->seninf->entity); + ret =3D v4l2_subdev_disable_streams(seninf, cam->seninf->index, + BIT(0)); + if (ret) { + dev_err(cam->dev, "failed to stream off %s:%d\n", + sd->entity.name, ret); + return ret; + } + } + + return 0; +} + +static const struct v4l2_subdev_pad_ops mtk_cam_subdev_pad_ops =3D { + .enum_mbus_code =3D mtk_cam_enum_mbus_code, + .set_fmt =3D mtk_cam_set_fmt, + .get_fmt =3D v4l2_subdev_get_fmt, + .link_validate =3D v4l2_subdev_link_validate_default, + .enable_streams =3D camsv_enable_streams, + .disable_streams =3D camsv_disable_streams, +}; + +static const struct v4l2_subdev_ops mtk_cam_subdev_ops =3D { + .pad =3D &mtk_cam_subdev_pad_ops, +}; + +static const struct v4l2_subdev_internal_ops mtk_cam_internal_ops =3D { + .init_state =3D mtk_cam_init_state, + .registered =3D mtk_cam_subdev_registered, +}; + +/* -----------------------------------------------------------------------= ------ + * Media Entity Operations + */ + +static const struct media_entity_operations mtk_cam_media_entity_ops =3D { + .link_validate =3D v4l2_subdev_link_validate, + .get_fwnode_pad =3D v4l2_subdev_get_fwnode_pad_1_to_1, +}; + +/* -----------------------------------------------------------------------= ------ + * Init & Cleanup + */ + +static int mtk_cam_v4l2_register(struct mtk_cam_dev *cam) +{ + struct device *dev =3D cam->dev; + int ret; + + cam->subdev_pads[MTK_CAM_CIO_PAD_SENINF].flags =3D MEDIA_PAD_FL_SINK; + cam->subdev_pads[MTK_CAM_CIO_PAD_VIDEO].flags =3D MEDIA_PAD_FL_SOURCE; + + /* Initialize subdev pads */ + ret =3D media_entity_pads_init(&cam->subdev.entity, + ARRAY_SIZE(cam->subdev_pads), + cam->subdev_pads); + if (ret) { + dev_err(dev, "failed to initialize media pads:%d\n", ret); + return ret; + } + + /* Initialize subdev */ + v4l2_subdev_init(&cam->subdev, &mtk_cam_subdev_ops); + + cam->subdev.dev =3D dev; + cam->subdev.entity.function =3D MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; + cam->subdev.entity.ops =3D &mtk_cam_media_entity_ops; + cam->subdev.internal_ops =3D &mtk_cam_internal_ops; + cam->subdev.flags =3D V4L2_SUBDEV_FL_HAS_DEVNODE; + strscpy(cam->subdev.name, dev_name(dev), sizeof(cam->subdev.name)); + v4l2_set_subdevdata(&cam->subdev, cam); + + v4l2_subdev_init_finalize(&cam->subdev); + + ret =3D v4l2_async_register_subdev(&cam->subdev); + if (ret) { + dev_err(dev, "failed to initialize subdev:%d\n", ret); + media_entity_cleanup(&cam->subdev.entity); + return ret; + } + + return 0; +} + +static void mtk_cam_v4l2_unregister(struct mtk_cam_dev *cam) +{ + mtk_cam_video_unregister(&cam->vdev); + + media_entity_cleanup(&cam->subdev.entity); + v4l2_async_unregister_subdev(&cam->subdev); + v4l2_subdev_cleanup(&cam->subdev); +} + +int mtk_cam_dev_init(struct mtk_cam_dev *cam_dev) +{ + int ret; + + mutex_init(&cam_dev->op_lock); + + /* v4l2 sub-device registration */ + ret =3D mtk_cam_v4l2_register(cam_dev); + if (ret) { + mutex_destroy(&cam_dev->op_lock); + return ret; + } + + return 0; +} + +void mtk_cam_dev_cleanup(struct mtk_cam_dev *cam) +{ + mtk_cam_v4l2_unregister(cam); + mutex_destroy(&cam->op_lock); +} diff --git a/drivers/media/platform/mediatek/isp/mtk_camsv.h b/drivers/medi= a/platform/mediatek/isp/mtk_camsv.h new file mode 100644 index 0000000000000000000000000000000000000000..de928662c75778ffeae708a7bda= c27943af75d94 --- /dev/null +++ b/drivers/media/platform/mediatek/isp/mtk_camsv.h @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 BayLibre + * Copyright (c) 2022 MediaTek Inc. + */ + +#ifndef __MTK_CAMSV_H__ +#define __MTK_CAMSV_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IMG_MAX_WIDTH 5376U +#define IMG_MAX_HEIGHT 4032U +#define IMG_MIN_WIDTH 80U +#define IMG_MIN_HEIGHT 60U + +#define MTK_CAM_CIO_PAD_SENINF 0U +#define MTK_CAM_CIO_PAD_VIDEO 1U +#define MTK_CAM_CIO_NUM_PADS 2U + +struct mtk_cam_format_info { + u32 code; + u32 fourcc; + u8 bpp; +}; + +struct mtk_cam_dev_buffer { + struct vb2_v4l2_buffer v4l2_buf; + struct list_head list; + dma_addr_t daddr; + void *vaddr; +}; + +struct mtk_cam_sparams { + u32 w_factor; + u32 module_en_pak; + u32 fmt_sel; + u32 pak; + u32 imgo_stride; +}; + +/** + * struct mtk_cam_vdev_desc - MTK camera device descriptor + * @num_fmts: the number of supported node formats + * @fmts: supported format + * @frmsizes: supported V4L2 frame size number + */ +struct mtk_cam_vdev_desc { + u8 num_fmts; + const u32 *fmts; + const struct v4l2_frmsizeenum *frmsizes; +}; + +/** + * struct mtk_cam_video_device - MediaTek video device structure + * @desc: The node description of video device + * @vdev_pad: The media pad graph object of video device + * @vdev: The video device instance + * @vbq: A videobuf queue of video device + * @vdev_lock: Serializes vb2 queue and video device operations + * @format: The V4L2 format of video device + * @fmtinfo: Information about the current format + */ +struct mtk_cam_video_device { + const struct mtk_cam_vdev_desc *desc; + + struct media_pad vdev_pad; + struct video_device vdev; + struct vb2_queue vbq; + + /* Serializes vb2 queue and video device operations */ + struct mutex vdev_lock; + + struct v4l2_pix_format_mplane format; + const struct mtk_cam_format_info *fmtinfo; +}; + +/** + * struct mtk_cam_dev - MediaTek camera device structure. + * @dev: Pointer to device. + * @regs: Base address of CAMSV. + * @regs_img0: Base address of CAMSV IMG0. + * @regs_tg: Base address of CAMSV TG. + * @num_clks: Number of clocks. + * @clks: The clocks. + * @irq: Irq fired when buffer is ready. + * @conf: soc specific driver data. + * @pipeline: Media pipeline information. + * @subdev: The V4L2 sub-device instance. + * @subdev_pads: Media pads of this sub-device. + * @vdev: The video device node. + * @seninf: Pointer to the seninf pad. + * @stream_count: Number of streaming video nodes. + * @sequence: Buffer sequence number. + * @op_lock: Serializes driver's VB2 callback operations. + * @buf_list_lock: Protects the buffer list. + * @buf_list: List head for the buffer list. + * @hw_functions: Hardware specific functions. + */ +struct mtk_cam_dev { + struct device *dev; + void __iomem *regs; + void __iomem *regs_img0; + void __iomem *regs_tg; + + unsigned int num_clks; + struct clk_bulk_data *clks; + unsigned int irq; + const struct mtk_cam_conf *conf; + + struct media_pipeline pipeline; + struct v4l2_subdev subdev; + struct media_pad subdev_pads[MTK_CAM_CIO_NUM_PADS]; + struct mtk_cam_video_device vdev; + struct media_pad *seninf; + unsigned int stream_count; + unsigned int sequence; + + struct mutex op_lock; + spinlock_t buf_list_lock; + + struct list_head buf_list; + + const struct mtk_cam_hw_functions *hw_functions; + +}; + +/** + * struct mtk_cam_conf - MediaTek camera configuration structure + * @tg_sen_mode: TG sensor mode + * @module_en: module enable + * @imgo_con: dma control register + * @imgo_con2: dma control register 2 + */ +struct mtk_cam_conf { + u32 tg_sen_mode; + u32 module_en; + u32 imgo_con; + u32 imgo_con2; +}; + +struct mtk_cam_hw_functions { + void (*mtk_cam_setup)(struct mtk_cam_dev *cam_dev, u32 width, + u32 height, u32 bpl, u32 mbus_fmt); + void (*mtk_cam_update_buffers_add)(struct mtk_cam_dev *cam_dev, + struct mtk_cam_dev_buffer *buf); + void (*mtk_cam_cmos_vf_hw_enable)(struct mtk_cam_dev *cam_dev); + void (*mtk_cam_cmos_vf_hw_disable)(struct mtk_cam_dev *cam_dev); + void (*mtk_cam_fbc_init)(struct mtk_cam_dev *cam_dev, + unsigned int num_buffers); + void (*mtk_cam_fbc_inc)(struct mtk_cam_dev *cam_dev); +}; + +int mtk_cam_dev_init(struct mtk_cam_dev *cam_dev); +void mtk_cam_dev_cleanup(struct mtk_cam_dev *cam_dev); +int mtk_cam_video_register(struct mtk_cam_dev *cam_dev); +void mtk_cam_video_unregister(struct mtk_cam_video_device *vdev); + +#endif /* __MTK_CAMSV_H__ */ diff --git a/drivers/media/platform/mediatek/isp/mtk_camsv30_hw.c b/drivers= /media/platform/mediatek/isp/mtk_camsv30_hw.c new file mode 100644 index 0000000000000000000000000000000000000000..56c3686770901da9d355f36ee86= a9aa7f71aeb1f --- /dev/null +++ b/drivers/media/platform/mediatek/isp/mtk_camsv30_hw.c @@ -0,0 +1,539 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 BayLibre + * Copyright (c) 2022 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mtk_camsv.h" + +/* CAMSV */ +#define CAMSV_MODULE_EN 0x0000 +#define CAMSV_MODULE_EN_IMGO_EN BIT(4) +#define CAMSV_FMT_SEL 0x0004 +#define CAMSV_INT_EN 0x0008 +#define CAMSV_INT_STATUS 0x000c +#define CAMSV_SW_CTL 0x0010 +#define CAMSV_IMGO_FBC 0x001C +#define CAMSV_CLK_EN 0x0020 +#define CAMSV_PAK 0x003c + +/* CAMSV_TG */ +#define CAMSV_TG_SEN_MODE 0x0010 +#define CAMSV_TG_VF_CON 0x0014 +#define CAMSV_TG_SEN_GRAB_PXL 0x0018 +#define CAMSV_TG_SEN_GRAB_LIN 0x001c +#define CAMSV_TG_PATH_CFG 0x0020 + +/* CAMSV_IMG0 */ +#define CAMSV_IMGO_SV_BASE_ADDR 0x0000 +#define CAMSV_IMGO_SV_XSIZE 0x0008 +#define CAMSV_IMGO_SV_YSIZE 0x000c +#define CAMSV_IMGO_SV_STRIDE 0x0010 +#define CAMSV_IMGO_SV_CON 0x0014 +#define CAMSV_IMGO_SV_CON2 0x0018 + +#define CAMSV_TG_SEN_MODE_CMOS_EN BIT(0) +#define CAMSV_TG_VF_CON_VFDATA_EN BIT(0) + +/* CAMSV_CLK_EN bits */ +#define CAMSV_TG_DP_CLK_EN BIT(0) +#define CAMSV_PAK_DP_CLK_EN BIT(2) +#define CAMSV_DMA_DP_CLK_EN BIT(15) + +/* CAMSV_SW_CTL bits */ +#define CAMSV_IMGO_RST_TRIG BIT(0) +#define CAMSV_IMGO_RST_ST BIT(1) +#define CAMSV_SW_RST BIT(2) + +/* IRQ BITS */ +#define CAMSV_IRQ_TG_ERR BIT(4) +#define CAMSV_IRQ_TG_GBERR BIT(5) +#define CAMSV_IRQ_PASS1_DON BIT(10) +#define CAMSV_IRQ_IMGO_ERR BIT(16) + +/* FBC bits */ +#define CAMSV_IMGO_FBC_RCNT_INC BIT(11) +#define CAMSV_IMGO_FBC_EN BIT(14) +#define CAMSV_IMGO_FBC_LOCK_EN BIT(15) +#define CAMSV_IMGO_FBC_FB_NUM GENMASK(19, 16) + +#define INT_ST_MASK_CAMSV (CAMSV_IRQ_PASS1_DON) + +#define INT_ST_MASK_CAMSV_ERR \ + (CAMSV_IRQ_TG_ERR | CAMSV_IRQ_TG_GBERR | CAMSV_IRQ_IMGO_ERR) + +#define MTK_CAMSV30_AUTOSUSPEND_DELAY_MS 100 + +static const struct mtk_cam_conf camsv30_conf =3D { + .tg_sen_mode =3D 0x00010002U, /* TIME_STP_EN =3D 1. DBL_DATA_BUS =3D 1 */ + .module_en =3D 0x40000001U, /* enable double buffer and TG */ + .imgo_con =3D 0x80000080U, /* DMA FIFO depth and burst */ + .imgo_con2 =3D 0x00020002U, /* DMA priority */ +}; + +static void fmt_to_sparams(u32 mbus_fmt, struct mtk_cam_sparams *sparams) +{ + switch (mbus_fmt) { + case MEDIA_BUS_FMT_SBGGR12_1X12: + case MEDIA_BUS_FMT_SGBRG12_1X12: + case MEDIA_BUS_FMT_SGRBG12_1X12: + case MEDIA_BUS_FMT_SRGGB12_1X12: + sparams->w_factor =3D 1; + sparams->module_en_pak =3D 0x4; + sparams->fmt_sel =3D 0x2; + sparams->pak =3D 0x5; + sparams->imgo_stride =3D 0X000b0000; + break; + case MEDIA_BUS_FMT_SBGGR10_1X10: + case MEDIA_BUS_FMT_SGBRG10_1X10: + case MEDIA_BUS_FMT_SGRBG10_1X10: + case MEDIA_BUS_FMT_SRGGB10_1X10: + sparams->w_factor =3D 1; + sparams->module_en_pak =3D 0x4; + sparams->fmt_sel =3D 0x1; + sparams->pak =3D 0x6; + sparams->imgo_stride =3D 0X000b0000; + break; + case MEDIA_BUS_FMT_SBGGR8_1X8: + case MEDIA_BUS_FMT_SGBRG8_1X8: + case MEDIA_BUS_FMT_SGRBG8_1X8: + case MEDIA_BUS_FMT_SRGGB8_1X8: + sparams->w_factor =3D 1; + sparams->module_en_pak =3D 0x4; + sparams->fmt_sel =3D 0x0; + sparams->pak =3D 0x7; + sparams->imgo_stride =3D 0X000b0000; + break; + case MEDIA_BUS_FMT_UYVY8_1X16: + case MEDIA_BUS_FMT_VYUY8_1X16: + case MEDIA_BUS_FMT_YUYV8_1X16: + case MEDIA_BUS_FMT_YVYU8_1X16: + sparams->w_factor =3D 2; + sparams->module_en_pak =3D 0x8; + sparams->fmt_sel =3D 0x1000003; + sparams->pak =3D 0x0; + sparams->imgo_stride =3D 0x00090000; + break; + default: + break; + } +} + +static u32 mtk_camsv30_read(struct mtk_cam_dev *priv, u32 reg) +{ + return readl(priv->regs + reg); +} + +static void mtk_camsv30_write(struct mtk_cam_dev *priv, u32 reg, u32 value) +{ + writel(value, priv->regs + reg); +} + +static void mtk_camsv30_img0_write(struct mtk_cam_dev *priv, u32 reg, u32 = value) +{ + writel(value, priv->regs_img0 + reg); +} + +static u32 mtk_camsv30_tg_read(struct mtk_cam_dev *priv, u32 reg) +{ + return readl(priv->regs_tg + reg); +} + +static void mtk_camsv30_tg_write(struct mtk_cam_dev *priv, u32 reg, u32 va= lue) +{ + writel(value, priv->regs_tg + reg); +} + +static void mtk_camsv30_update_buffers_add(struct mtk_cam_dev *cam_dev, + struct mtk_cam_dev_buffer *buf) +{ + mtk_camsv30_img0_write(cam_dev, CAMSV_IMGO_SV_BASE_ADDR, buf->daddr); +} + +static void mtk_camsv30_cmos_vf_hw_enable(struct mtk_cam_dev *cam_dev) +{ + unsigned int fbc_val; + u32 clk_en =3D CAMSV_TG_DP_CLK_EN | CAMSV_DMA_DP_CLK_EN | + CAMSV_PAK_DP_CLK_EN; + + fbc_val =3D mtk_camsv30_read(cam_dev, CAMSV_IMGO_FBC); + fbc_val |=3D CAMSV_IMGO_FBC_EN; + mtk_camsv30_write(cam_dev, CAMSV_IMGO_FBC, fbc_val); + + mtk_camsv30_write(cam_dev, CAMSV_CLK_EN, clk_en); + mtk_camsv30_tg_write(cam_dev, CAMSV_TG_SEN_MODE, + mtk_camsv30_tg_read(cam_dev, CAMSV_TG_SEN_MODE) | + CAMSV_TG_SEN_MODE_CMOS_EN); + mtk_camsv30_tg_write(cam_dev, CAMSV_TG_VF_CON, + mtk_camsv30_tg_read(cam_dev, CAMSV_TG_VF_CON) | + CAMSV_TG_VF_CON_VFDATA_EN); +} + +static void mtk_camsv30_cmos_vf_hw_disable(struct mtk_cam_dev *cam_dev) +{ + unsigned int fbc_val; + + mtk_camsv30_tg_write(cam_dev, CAMSV_TG_SEN_MODE, + mtk_camsv30_tg_read(cam_dev, CAMSV_TG_SEN_MODE) & + ~CAMSV_TG_SEN_MODE_CMOS_EN); + mtk_camsv30_tg_write(cam_dev, CAMSV_TG_VF_CON, + mtk_camsv30_tg_read(cam_dev, CAMSV_TG_VF_CON) & + ~CAMSV_TG_VF_CON_VFDATA_EN); + fbc_val =3D mtk_camsv30_read(cam_dev, CAMSV_IMGO_FBC); + fbc_val &=3D ~CAMSV_IMGO_FBC_EN; + mtk_camsv30_write(cam_dev, CAMSV_IMGO_FBC, fbc_val); +} + +static void mtk_camsv30_fbc_init(struct mtk_cam_dev *cam_dev, + unsigned int num_buffers) +{ + unsigned int fbc_val; + + if (pm_runtime_resume_and_get(cam_dev->dev) < 0) { + dev_err(cam_dev->dev, "failed to get pm_runtime\n"); + return; + } + + fbc_val =3D mtk_camsv30_read(cam_dev, CAMSV_IMGO_FBC); + fbc_val &=3D ~CAMSV_IMGO_FBC_FB_NUM; + fbc_val |=3D CAMSV_IMGO_FBC_EN; + fbc_val |=3D FIELD_PREP(CAMSV_IMGO_FBC_FB_NUM, num_buffers); + mtk_camsv30_write(cam_dev, CAMSV_IMGO_FBC, fbc_val); + + pm_runtime_put_autosuspend(cam_dev->dev); +} + +static void mtk_camsv30_fbc_inc(struct mtk_cam_dev *cam_dev) +{ + unsigned int fbc_val; + + if (pm_runtime_resume_and_get(cam_dev->dev) < 0) { + dev_err(cam_dev->dev, "failed to get pm_runtime\n"); + return; + } + + fbc_val =3D mtk_camsv30_read(cam_dev, CAMSV_IMGO_FBC); + fbc_val |=3D CAMSV_IMGO_FBC_RCNT_INC; + mtk_camsv30_write(cam_dev, CAMSV_IMGO_FBC, fbc_val); + fbc_val &=3D ~CAMSV_IMGO_FBC_RCNT_INC; + mtk_camsv30_write(cam_dev, CAMSV_IMGO_FBC, fbc_val); + + pm_runtime_put_autosuspend(cam_dev->dev); +} + +static void mtk_camsv30_setup(struct mtk_cam_dev *cam_dev, u32 w, u32 h, + u32 bpl, u32 mbus_fmt) +{ + const struct mtk_cam_conf *conf =3D cam_dev->conf; + u32 tmp; + struct mtk_cam_sparams sparams; + + fmt_to_sparams(mbus_fmt, &sparams); + + if (pm_runtime_resume_and_get(cam_dev->dev) < 0) { + dev_err(cam_dev->dev, "failed to get pm_runtime\n"); + return; + } + + mtk_camsv30_tg_write(cam_dev, CAMSV_TG_SEN_MODE, conf->tg_sen_mode); + + mtk_camsv30_tg_write(cam_dev, CAMSV_TG_SEN_GRAB_PXL, + (w * sparams.w_factor) << 16U); + + mtk_camsv30_tg_write(cam_dev, CAMSV_TG_SEN_GRAB_LIN, h << 16U); + + /* YUV_U2S_DIS: disable YUV sensor unsigned to signed */ + mtk_camsv30_tg_write(cam_dev, CAMSV_TG_PATH_CFG, 0x1000U); + + /* Reset cam */ + mtk_camsv30_write(cam_dev, CAMSV_SW_CTL, CAMSV_SW_RST); + mtk_camsv30_write(cam_dev, CAMSV_SW_CTL, 0x0U); + mtk_camsv30_write(cam_dev, CAMSV_SW_CTL, CAMSV_IMGO_RST_TRIG); + + readl_poll_timeout_atomic(cam_dev->regs + CAMSV_SW_CTL, tmp, + (tmp =3D=3D (CAMSV_IMGO_RST_TRIG | + CAMSV_IMGO_RST_ST)), 10, 200); + + mtk_camsv30_write(cam_dev, CAMSV_SW_CTL, 0x0U); + + mtk_camsv30_write(cam_dev, CAMSV_INT_EN, INT_ST_MASK_CAMSV); + + mtk_camsv30_write(cam_dev, CAMSV_MODULE_EN, + conf->module_en | sparams.module_en_pak); + mtk_camsv30_write(cam_dev, CAMSV_FMT_SEL, sparams.fmt_sel); + mtk_camsv30_write(cam_dev, CAMSV_PAK, sparams.pak); + + mtk_camsv30_img0_write(cam_dev, CAMSV_IMGO_SV_XSIZE, bpl - 1U); + mtk_camsv30_img0_write(cam_dev, CAMSV_IMGO_SV_YSIZE, h - 1U); + + mtk_camsv30_img0_write(cam_dev, CAMSV_IMGO_SV_STRIDE, + sparams.imgo_stride | bpl); + + mtk_camsv30_img0_write(cam_dev, CAMSV_IMGO_SV_CON, conf->imgo_con); + mtk_camsv30_img0_write(cam_dev, CAMSV_IMGO_SV_CON2, conf->imgo_con2); + + /* CMOS_EN first */ + mtk_camsv30_tg_write(cam_dev, CAMSV_TG_SEN_MODE, + mtk_camsv30_tg_read(cam_dev, CAMSV_TG_SEN_MODE) | + CAMSV_TG_SEN_MODE_CMOS_EN); + + /* finally, CAMSV_MODULE_EN : IMGO_EN */ + mtk_camsv30_write(cam_dev, CAMSV_MODULE_EN, + mtk_camsv30_read(cam_dev, CAMSV_MODULE_EN) | + CAMSV_MODULE_EN_IMGO_EN); + + pm_runtime_put_autosuspend(cam_dev->dev); +} + +static irqreturn_t isp_irq_camsv30(int irq, void *data) +{ + struct mtk_cam_dev *cam_dev =3D (struct mtk_cam_dev *)data; + struct mtk_cam_dev_buffer *buf; + unsigned int irq_status; + + spin_lock(&cam_dev->buf_list_lock); + + irq_status =3D mtk_camsv30_read(cam_dev, CAMSV_INT_STATUS); + + if (irq_status & INT_ST_MASK_CAMSV_ERR) + dev_err(cam_dev->dev, "irq error 0x%lx\n", + irq_status & INT_ST_MASK_CAMSV_ERR); + + /* De-queue frame */ + if (irq_status & CAMSV_IRQ_PASS1_DON) { + cam_dev->sequence++; + + buf =3D list_first_entry_or_null(&cam_dev->buf_list, + struct mtk_cam_dev_buffer, + list); + if (buf) { + buf->v4l2_buf.sequence =3D cam_dev->sequence; + buf->v4l2_buf.vb2_buf.timestamp =3D + ktime_get_ns(); + vb2_buffer_done(&buf->v4l2_buf.vb2_buf, + VB2_BUF_STATE_DONE); + list_del(&buf->list); + } + + buf =3D list_first_entry_or_null(&cam_dev->buf_list, + struct mtk_cam_dev_buffer, + list); + if (buf) + mtk_camsv30_update_buffers_add(cam_dev, buf); + } + + spin_unlock(&cam_dev->buf_list_lock); + + return IRQ_HANDLED; +} + +static int mtk_camsv30_runtime_suspend(struct device *dev) +{ + struct mtk_cam_dev *cam_dev =3D dev_get_drvdata(dev); + struct vb2_queue *vbq =3D &cam_dev->vdev.vbq; + + if (vb2_is_streaming(vbq)) { + mutex_lock(&cam_dev->op_lock); + v4l2_subdev_disable_streams(&cam_dev->subdev, + cam_dev->subdev_pads[MTK_CAM_CIO_PAD_VIDEO].index, + BIT(0)); + mutex_unlock(&cam_dev->op_lock); + } + + clk_bulk_disable_unprepare(cam_dev->num_clks, cam_dev->clks); + + return 0; +} + +static int mtk_camsv30_runtime_resume(struct device *dev) +{ + struct mtk_cam_dev *cam_dev =3D dev_get_drvdata(dev); + struct mtk_cam_video_device *vdev =3D &cam_dev->vdev; + const struct v4l2_pix_format_mplane *fmt =3D &vdev->format; + struct vb2_queue *vbq =3D &vdev->vbq; + struct mtk_cam_dev_buffer *buf, *buf_prev; + int ret; + unsigned long flags =3D 0; + + ret =3D clk_bulk_prepare_enable(cam_dev->num_clks, cam_dev->clks); + if (ret) { + dev_err(dev, "failed to enable clock:%d\n", ret); + return ret; + } + + if (vb2_is_streaming(vbq)) { + mtk_camsv30_setup(cam_dev, fmt->width, fmt->height, + fmt->plane_fmt[0].bytesperline, + vdev->fmtinfo->code); + + spin_lock_irqsave(&cam_dev->buf_list_lock, flags); + buf =3D list_first_entry_or_null(&cam_dev->buf_list, + struct mtk_cam_dev_buffer, + list); + if (buf) + mtk_camsv30_update_buffers_add(cam_dev, buf); + + spin_unlock_irqrestore(&cam_dev->buf_list_lock, flags); + mtk_camsv30_cmos_vf_hw_enable(cam_dev); + + + /* Stream on the sub-device */ + mutex_lock(&cam_dev->op_lock); + ret =3D v4l2_subdev_enable_streams(&cam_dev->subdev, + cam_dev->subdev_pads[MTK_CAM_CIO_PAD_VIDEO].index, + BIT(0)); + + if (ret) { + cam_dev->stream_count--; + if (cam_dev->stream_count =3D=3D 0) + media_pipeline_stop(vdev->vdev.entity.pads); + } + mutex_unlock(&cam_dev->op_lock); + + if (ret) + goto fail_no_stream; + } + + return 0; + +fail_no_stream: + spin_lock_irqsave(&cam_dev->buf_list_lock, flags); + list_for_each_entry_safe(buf, buf_prev, &cam_dev->buf_list, list) { + buf->daddr =3D 0ULL; + list_del(&buf->list); + vb2_buffer_done(&buf->v4l2_buf.vb2_buf, VB2_BUF_STATE_ERROR); + } + spin_unlock_irqrestore(&cam_dev->buf_list_lock, flags); + return ret; +} + +static const struct mtk_cam_hw_functions mtk_camsv30_hw_functions =3D { + .mtk_cam_setup =3D mtk_camsv30_setup, + .mtk_cam_update_buffers_add =3D mtk_camsv30_update_buffers_add, + .mtk_cam_cmos_vf_hw_enable =3D mtk_camsv30_cmos_vf_hw_enable, + .mtk_cam_cmos_vf_hw_disable =3D mtk_camsv30_cmos_vf_hw_disable, + .mtk_cam_fbc_init =3D mtk_camsv30_fbc_init, + .mtk_cam_fbc_inc =3D mtk_camsv30_fbc_inc, +}; + +static int mtk_camsv30_probe(struct platform_device *pdev) +{ + static const char * const clk_names[] =3D { "cam", "camtg", "camsv"}; + + struct mtk_cam_dev *cam_dev; + struct device *dev =3D &pdev->dev; + unsigned int i; + int ret; + + if (!iommu_present(&platform_bus_type)) + return -EPROBE_DEFER; + + cam_dev =3D devm_kzalloc(dev, sizeof(*cam_dev), GFP_KERNEL); + if (!cam_dev) + return -ENOMEM; + + cam_dev->conf =3D device_get_match_data(dev); + if (!cam_dev->conf) + return -ENODEV; + + cam_dev->dev =3D dev; + dev_set_drvdata(dev, cam_dev); + + cam_dev->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(cam_dev->regs)) + return dev_err_probe(dev, PTR_ERR(cam_dev->regs), + "failed to map register base\n"); + + cam_dev->regs_img0 =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(cam_dev->regs_img0)) + return dev_err_probe(dev, PTR_ERR(cam_dev->regs_img0), + "failed to map img0 register base\n"); + + cam_dev->regs_tg =3D devm_platform_ioremap_resource(pdev, 2); + if (IS_ERR(cam_dev->regs_tg)) + return dev_err_probe(dev, PTR_ERR(cam_dev->regs_tg), + "failed to map TG register base\n"); + + cam_dev->num_clks =3D ARRAY_SIZE(clk_names); + cam_dev->clks =3D devm_kcalloc(dev, cam_dev->num_clks, + sizeof(*cam_dev->clks), GFP_KERNEL); + if (!cam_dev->clks) + return -ENOMEM; + + for (i =3D 0; i < cam_dev->num_clks; ++i) + cam_dev->clks[i].id =3D clk_names[i]; + + ret =3D devm_clk_bulk_get(dev, cam_dev->num_clks, cam_dev->clks); + if (ret) + return dev_err_probe(dev, ret, "failed to get clocks: %i\n", + ret); + + cam_dev->irq =3D platform_get_irq(pdev, 0); + ret =3D devm_request_irq(dev, cam_dev->irq, isp_irq_camsv30, 0, + dev_name(dev), cam_dev); + if (ret !=3D 0) + return dev_err_probe(dev, -ENODEV, "failed to request irq=3D%d\n", + cam_dev->irq); + + cam_dev->hw_functions =3D &mtk_camsv30_hw_functions; + + spin_lock_init(&cam_dev->buf_list_lock); + + /* initialise runtime power management */ + pm_runtime_set_autosuspend_delay(dev, MTK_CAMSV30_AUTOSUSPEND_DELAY_MS); + pm_runtime_use_autosuspend(dev); + pm_runtime_set_suspended(dev); + devm_pm_runtime_enable(dev); + + /* Initialize the v4l2 common part */ + return mtk_cam_dev_init(cam_dev); +} + +static void mtk_camsv30_remove(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct mtk_cam_dev *cam_dev =3D dev_get_drvdata(dev); + + mtk_cam_dev_cleanup(cam_dev); + pm_runtime_put_autosuspend(dev); +} + +static const struct dev_pm_ops mtk_camsv30_pm_ops =3D { + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) + SET_RUNTIME_PM_OPS(mtk_camsv30_runtime_suspend, + mtk_camsv30_runtime_resume, NULL) +}; + +static const struct of_device_id mtk_camsv30_of_ids[] =3D { + { .compatible =3D "mediatek,mt8365-camsv", .data =3D &camsv30_conf }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, mtk_camsv30_of_ids); + +static struct platform_driver mtk_camsv30_driver =3D { + .probe =3D mtk_camsv30_probe, + .remove =3D mtk_camsv30_remove, + .driver =3D { + .name =3D "mtk-camsv-isp30", + .of_match_table =3D mtk_camsv30_of_ids, + .pm =3D &mtk_camsv30_pm_ops, + } +}; + +module_platform_driver(mtk_camsv30_driver); + +MODULE_DESCRIPTION("MediaTek CAMSV ISP3.0 driver"); +MODULE_AUTHOR("Florian Sylvestre "); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/platform/mediatek/isp/mtk_camsv_video.c b/driver= s/media/platform/mediatek/isp/mtk_camsv_video.c new file mode 100644 index 0000000000000000000000000000000000000000..4a5f3431a14563d5ed133270a99= 07773e8626f9c --- /dev/null +++ b/drivers/media/platform/mediatek/isp/mtk_camsv_video.c @@ -0,0 +1,701 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * mtk_camsv_video.c - V4L2 video node support + * + * Copyright (c) 2020 BayLibre + * Copyright (c) 2022 MediaTek Inc. + */ + +#include +#include +#include +#include +#include + +#include "mtk_camsv.h" + +static inline struct mtk_cam_video_device * +file_to_mtk_cam_video_device(struct file *__file) +{ + return container_of(video_devdata(__file), + struct mtk_cam_video_device, vdev); +} + +static inline struct mtk_cam_video_device * +vb2_queue_to_mtk_cam_video_device(struct vb2_queue *vq) +{ + return container_of(vq, struct mtk_cam_video_device, vbq); +} + +static inline struct mtk_cam_dev_buffer * +to_mtk_cam_dev_buffer(struct vb2_buffer *buf) +{ + return container_of(buf, struct mtk_cam_dev_buffer, v4l2_buf.vb2_buf); +} + +/* -----------------------------------------------------------------------= ------ + * Format Information + */ + +static const struct mtk_cam_format_info mtk_cam_format_info[] =3D { + { + .fourcc =3D V4L2_PIX_FMT_SBGGR8, + .code =3D MEDIA_BUS_FMT_SBGGR8_1X8, + .bpp =3D 8, + }, { + .fourcc =3D V4L2_PIX_FMT_SGBRG8, + .code =3D MEDIA_BUS_FMT_SGBRG8_1X8, + .bpp =3D 8, + }, { + .fourcc =3D V4L2_PIX_FMT_SGRBG8, + .code =3D MEDIA_BUS_FMT_SGRBG8_1X8, + .bpp =3D 8, + }, { + .fourcc =3D V4L2_PIX_FMT_SRGGB8, + .code =3D MEDIA_BUS_FMT_SRGGB8_1X8, + .bpp =3D 8, + }, { + .fourcc =3D V4L2_PIX_FMT_YUYV, + .code =3D MEDIA_BUS_FMT_YUYV8_1X16, + .bpp =3D 16, + }, { + .fourcc =3D V4L2_PIX_FMT_YVYU, + .code =3D MEDIA_BUS_FMT_YVYU8_1X16, + .bpp =3D 16, + }, { + .fourcc =3D V4L2_PIX_FMT_UYVY, + .code =3D MEDIA_BUS_FMT_UYVY8_1X16, + .bpp =3D 16, + }, { + .fourcc =3D V4L2_PIX_FMT_VYUY, + .code =3D MEDIA_BUS_FMT_VYUY8_1X16, + .bpp =3D 16, + }, +}; + +static const struct mtk_cam_format_info * +mtk_cam_format_info_by_fourcc(u32 fourcc) +{ + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(mtk_cam_format_info); ++i) { + const struct mtk_cam_format_info *info =3D + &mtk_cam_format_info[i]; + + if (info->fourcc =3D=3D fourcc) + return info; + } + + return NULL; +} + +static const struct mtk_cam_format_info * +mtk_cam_format_info_by_code(u32 code) +{ + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(mtk_cam_format_info); ++i) { + const struct mtk_cam_format_info *info =3D + &mtk_cam_format_info[i]; + + if (info->code =3D=3D code) + return info; + } + + return NULL; +} + +static bool mtk_cam_dev_find_fmt(const struct mtk_cam_vdev_desc *desc, + u32 format) +{ + unsigned int i; + + for (i =3D 0; i < desc->num_fmts; i++) { + if (desc->fmts[i] =3D=3D format) + return true; + } + + return false; +} + +static void calc_bpl_size_pix_mp(const struct mtk_cam_format_info *fmtinfo, + struct v4l2_pix_format_mplane *pix_mp) +{ + unsigned int bpl; + unsigned int i; + + bpl =3D ALIGN(DIV_ROUND_UP(pix_mp->width * fmtinfo->bpp, 8), 2); + + for (i =3D 0; i < pix_mp->num_planes; ++i) { + pix_mp->plane_fmt[i].bytesperline =3D bpl; + pix_mp->plane_fmt[i].sizeimage =3D bpl * pix_mp->height; + } +} + +static void mtk_cam_dev_load_default_fmt(struct mtk_cam_dev *cam) +{ + struct mtk_cam_video_device *vdev =3D &cam->vdev; + struct v4l2_pix_format_mplane *fmt =3D &vdev->format; + + fmt->num_planes =3D 1; + fmt->pixelformat =3D vdev->desc->fmts[0]; + fmt->width =3D IMG_MAX_WIDTH; + fmt->height =3D IMG_MAX_HEIGHT; + + fmt->colorspace =3D V4L2_COLORSPACE_SRGB; + fmt->field =3D V4L2_FIELD_NONE; + fmt->ycbcr_enc =3D V4L2_YCBCR_ENC_DEFAULT; + fmt->quantization =3D V4L2_QUANTIZATION_DEFAULT; + fmt->xfer_func =3D V4L2_XFER_FUNC_DEFAULT; + + vdev->fmtinfo =3D mtk_cam_format_info_by_fourcc(fmt->pixelformat); + + calc_bpl_size_pix_mp(vdev->fmtinfo, fmt); +} + +/* -----------------------------------------------------------------------= ------ + * VB2 Queue Operations + */ + +static int mtk_cam_vb2_queue_setup(struct vb2_queue *vq, + unsigned int *num_buffers, + unsigned int *num_planes, + unsigned int sizes[], + struct device *alloc_devs[]) +{ + struct mtk_cam_video_device *vdev =3D + vb2_queue_to_mtk_cam_video_device(vq); + struct mtk_cam_dev *cam =3D vb2_get_drv_priv(vq); + const struct v4l2_pix_format_mplane *fmt =3D &vdev->format; + unsigned int size, default_num_planes, i; + + size =3D fmt->plane_fmt[0].sizeimage; + + default_num_planes =3D 1; + + if (*num_planes =3D=3D 0) { + *num_planes =3D default_num_planes; + for (i =3D 0; i < *num_planes; ++i) + sizes[i] =3D size; + } else if (*num_planes !=3D default_num_planes || sizes[0] < size) { + return -EINVAL; + } + + (*cam->hw_functions->mtk_cam_fbc_init)(cam, *num_buffers); + + return 0; +} + +static int mtk_cam_vb2_buf_prepare(struct vb2_buffer *vb) +{ + struct mtk_cam_video_device *vdev =3D + vb2_queue_to_mtk_cam_video_device(vb->vb2_queue); + struct mtk_cam_dev *cam =3D vb2_get_drv_priv(vb->vb2_queue); + struct mtk_cam_dev_buffer *buf =3D to_mtk_cam_dev_buffer(vb); + const struct v4l2_pix_format_mplane *fmt =3D &vdev->format; + u32 size; + int i; + + for (i =3D 0; i < vb->num_planes; i++) { + size =3D fmt->plane_fmt[i].sizeimage; + if (vb2_plane_size(vb, i) < size) { + dev_err(cam->dev, "plane size is too small:%lu<%u\n", + vb2_plane_size(vb, i), size); + return -EINVAL; + } + } + + buf->v4l2_buf.field =3D V4L2_FIELD_NONE; + + for (i =3D 0; i < vb->num_planes; i++) { + size =3D fmt->plane_fmt[i].sizeimage; + vb2_set_plane_payload(vb, i, size); + } + + if (!buf->daddr) + buf->daddr =3D vb2_dma_contig_plane_dma_addr(vb, 0); + + return 0; +} + +static void mtk_cam_vb2_buf_queue(struct vb2_buffer *vb) +{ + struct mtk_cam_dev *cam =3D vb2_get_drv_priv(vb->vb2_queue); + struct mtk_cam_dev_buffer *buf =3D to_mtk_cam_dev_buffer(vb); + unsigned long flags; + + /* Add the buffer into the tracking list */ + spin_lock_irqsave(&cam->buf_list_lock, flags); + if (list_empty(&cam->buf_list)) + (*cam->hw_functions->mtk_cam_update_buffers_add)(cam, buf); + + list_add_tail(&buf->list, &cam->buf_list); + (*cam->hw_functions->mtk_cam_fbc_inc)(cam); + spin_unlock_irqrestore(&cam->buf_list_lock, flags); +} + +static void mtk_cam_vb2_return_all_buffers(struct mtk_cam_dev *cam, + enum vb2_buffer_state state) +{ + struct mtk_cam_dev_buffer *buf, *buf_prev; + unsigned long flags; + + spin_lock_irqsave(&cam->buf_list_lock, flags); + list_for_each_entry_safe(buf, buf_prev, &cam->buf_list, list) { + buf->daddr =3D 0ULL; + list_del(&buf->list); + vb2_buffer_done(&buf->v4l2_buf.vb2_buf, state); + } + spin_unlock_irqrestore(&cam->buf_list_lock, flags); +} + +static void mtk_cam_cmos_vf_enable(struct mtk_cam_dev *cam_dev, + bool enable, bool pak_en) +{ + if (enable) + cam_dev->hw_functions->mtk_cam_cmos_vf_hw_enable(cam_dev); + else + cam_dev->hw_functions->mtk_cam_cmos_vf_hw_disable(cam_dev); +} + +static int mtk_cam_verify_format(struct mtk_cam_dev *cam) +{ + struct mtk_cam_video_device *vdev =3D &cam->vdev; + struct v4l2_subdev_format fmt =3D { + .which =3D V4L2_SUBDEV_FORMAT_ACTIVE, + .pad =3D MTK_CAM_CIO_PAD_VIDEO, + }; + int ret; + + ret =3D v4l2_subdev_call(&cam->subdev, pad, get_fmt, NULL, &fmt); + if (ret < 0) + return ret =3D=3D -ENOIOCTLCMD ? -EINVAL : ret; + + if (vdev->fmtinfo->code !=3D fmt.format.code || + vdev->format.height !=3D fmt.format.height || + vdev->format.width !=3D fmt.format.width) + return -EINVAL; + + return 0; +} + +static int mtk_cam_vb2_start_streaming(struct vb2_queue *vq, + unsigned int count) +{ + struct mtk_cam_dev *cam =3D vb2_get_drv_priv(vq); + struct mtk_cam_dev_buffer *buf; + struct mtk_cam_video_device *vdev =3D + vb2_queue_to_mtk_cam_video_device(vq); + struct device *dev =3D cam->dev; + const struct v4l2_pix_format_mplane *fmt =3D &vdev->format; + int ret; + unsigned long flags; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) { + dev_err(dev, "failed to get pm_runtime\n"); + return ret; + } + + (*cam->hw_functions->mtk_cam_setup)(cam, fmt->width, fmt->height, + fmt->plane_fmt[0].bytesperline, vdev->fmtinfo->code); + + /* Enable CMOS and VF */ + mtk_cam_cmos_vf_enable(cam, true, true); + + mutex_lock(&cam->op_lock); + + ret =3D mtk_cam_verify_format(cam); + if (ret < 0) + goto fail_unlock; + + /* Start streaming of the whole pipeline now*/ + if (!cam->pipeline.start_count) { + ret =3D media_pipeline_start(vdev->vdev.entity.pads, + &cam->pipeline); + if (ret) { + dev_err(dev, "failed to start pipeline:%d\n", ret); + goto fail_unlock; + } + } + + /* Media links are fixed after media_pipeline_start */ + cam->stream_count++; + + cam->sequence =3D (unsigned int)-1; + + /* Stream on the sub-device */ + ret =3D v4l2_subdev_enable_streams(&cam->subdev, + cam->subdev_pads[MTK_CAM_CIO_PAD_VIDEO].index, + BIT(0)); + if (ret) + goto fail_no_stream; + + mutex_unlock(&cam->op_lock); + + /* Adding the buffer into the tracking list */ + spin_lock_irqsave(&cam->buf_list_lock, flags); + buf =3D list_first_entry_or_null(&cam->buf_list, + struct mtk_cam_dev_buffer, + list); + if (buf) + (*cam->hw_functions->mtk_cam_update_buffers_add)(cam, buf); + spin_unlock_irqrestore(&cam->buf_list_lock, flags); + + return 0; + +fail_no_stream: + cam->stream_count--; + if (cam->stream_count =3D=3D 0) + media_pipeline_stop(vdev->vdev.entity.pads); +fail_unlock: + mutex_unlock(&cam->op_lock); + mtk_cam_vb2_return_all_buffers(cam, VB2_BUF_STATE_QUEUED); + + return ret; +} + +static void mtk_cam_vb2_stop_streaming(struct vb2_queue *vq) +{ + struct mtk_cam_dev *cam =3D vb2_get_drv_priv(vq); + struct mtk_cam_video_device *vdev =3D + vb2_queue_to_mtk_cam_video_device(vq); + + /* Disable CMOS and VF */ + mtk_cam_cmos_vf_enable(cam, false, false); + + mutex_lock(&cam->op_lock); + + v4l2_subdev_disable_streams(&cam->subdev, + cam->subdev_pads[MTK_CAM_CIO_PAD_VIDEO].index, + BIT(0)); + + mtk_cam_vb2_return_all_buffers(cam, VB2_BUF_STATE_ERROR); + cam->stream_count--; + if (cam->stream_count) { + mutex_unlock(&cam->op_lock); + return; + } + + mutex_unlock(&cam->op_lock); + + media_pipeline_stop(vdev->vdev.entity.pads); +} + +static const struct vb2_ops mtk_cam_vb2_ops =3D { + .queue_setup =3D mtk_cam_vb2_queue_setup, + .buf_prepare =3D mtk_cam_vb2_buf_prepare, + .buf_queue =3D mtk_cam_vb2_buf_queue, + .start_streaming =3D mtk_cam_vb2_start_streaming, + .stop_streaming =3D mtk_cam_vb2_stop_streaming, + .wait_prepare =3D vb2_ops_wait_prepare, + .wait_finish =3D vb2_ops_wait_finish, +}; + +/* -----------------------------------------------------------------------= ------ + * V4L2 Video IOCTLs + */ + +static int mtk_cam_vidioc_querycap(struct file *file, void *fh, + struct v4l2_capability *cap) +{ + struct mtk_cam_dev *cam =3D video_drvdata(file); + + strscpy(cap->driver, dev_driver_string(cam->dev), sizeof(cap->driver)); + strscpy(cap->card, dev_driver_string(cam->dev), sizeof(cap->card)); + + return 0; +} + +static int mtk_cam_vidioc_enum_fmt(struct file *file, void *fh, + struct v4l2_fmtdesc *f) +{ + struct mtk_cam_video_device *vdev =3D file_to_mtk_cam_video_device(file); + const struct mtk_cam_format_info *fmtinfo; + unsigned int i; + + /* If mbus_code is not set enumerate all supported formats. */ + if (!f->mbus_code) { + if (f->index >=3D vdev->desc->num_fmts) + return -EINVAL; + + /* f->description is filled in v4l_fill_fmtdesc function */ + f->pixelformat =3D vdev->desc->fmts[f->index]; + f->flags =3D 0; + + return 0; + } + + /* + * Otherwise only enumerate supported pixel formats corresponding to + * that bus code. + */ + if (f->index) + return -EINVAL; + + fmtinfo =3D mtk_cam_format_info_by_code(f->mbus_code); + if (!fmtinfo) + return -EINVAL; + + for (i =3D 0; i < vdev->desc->num_fmts; ++i) { + if (vdev->desc->fmts[i] =3D=3D fmtinfo->fourcc) { + f->pixelformat =3D fmtinfo->fourcc; + f->flags =3D 0; + return 0; + } + } + + return -EINVAL; +} + +static int mtk_cam_vidioc_g_fmt(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct mtk_cam_video_device *vdev =3D file_to_mtk_cam_video_device(file); + + f->fmt.pix_mp =3D vdev->format; + + return 0; +} + +static int mtk_cam_vidioc_try_fmt(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct mtk_cam_video_device *vdev =3D file_to_mtk_cam_video_device(file); + struct v4l2_pix_format_mplane *pix_mp =3D &f->fmt.pix_mp; + const struct mtk_cam_format_info *fmtinfo; + + /* Validate pixelformat */ + if (!mtk_cam_dev_find_fmt(vdev->desc, pix_mp->pixelformat)) + pix_mp->pixelformat =3D vdev->desc->fmts[0]; + + pix_mp->width =3D clamp_val(pix_mp->width, IMG_MIN_WIDTH, IMG_MAX_WIDTH); + pix_mp->height =3D clamp_val(pix_mp->height, IMG_MIN_HEIGHT, + IMG_MAX_HEIGHT); + + pix_mp->num_planes =3D 1; + + fmtinfo =3D mtk_cam_format_info_by_fourcc(pix_mp->pixelformat); + calc_bpl_size_pix_mp(fmtinfo, pix_mp); + + /* Constant format fields */ + pix_mp->colorspace =3D V4L2_COLORSPACE_SRGB; + pix_mp->field =3D V4L2_FIELD_NONE; + pix_mp->ycbcr_enc =3D V4L2_YCBCR_ENC_DEFAULT; + pix_mp->quantization =3D V4L2_QUANTIZATION_DEFAULT; + pix_mp->xfer_func =3D V4L2_XFER_FUNC_DEFAULT; + + return 0; +} + +static int mtk_cam_vidioc_s_fmt(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct mtk_cam_video_device *vdev =3D file_to_mtk_cam_video_device(file); + int ret; + + if (vb2_is_busy(vdev->vdev.queue)) + return -EBUSY; + + ret =3D mtk_cam_vidioc_try_fmt(file, fh, f); + if (ret) + return ret; + + /* Configure to video device */ + vdev->format =3D f->fmt.pix_mp; + vdev->fmtinfo =3D + mtk_cam_format_info_by_fourcc(f->fmt.pix_mp.pixelformat); + + return 0; +} + +static int mtk_cam_vidioc_enum_framesizes(struct file *file, void *priv, + struct v4l2_frmsizeenum *sizes) +{ + struct mtk_cam_video_device *vdev =3D file_to_mtk_cam_video_device(file); + + if (sizes->index) + return -EINVAL; + + if (!mtk_cam_dev_find_fmt(vdev->desc, sizes->pixel_format)) + return -EINVAL; + + sizes->type =3D vdev->desc->frmsizes->type; + memcpy(&sizes->stepwise, &vdev->desc->frmsizes->stepwise, + sizeof(sizes->stepwise)); + + return 0; +} + +static const struct v4l2_ioctl_ops mtk_cam_v4l2_vcap_ioctl_ops =3D { + .vidioc_querycap =3D mtk_cam_vidioc_querycap, + .vidioc_enum_framesizes =3D mtk_cam_vidioc_enum_framesizes, + .vidioc_enum_fmt_vid_cap =3D mtk_cam_vidioc_enum_fmt, + .vidioc_g_fmt_vid_cap_mplane =3D mtk_cam_vidioc_g_fmt, + .vidioc_s_fmt_vid_cap_mplane =3D mtk_cam_vidioc_s_fmt, + .vidioc_try_fmt_vid_cap_mplane =3D mtk_cam_vidioc_try_fmt, + .vidioc_reqbufs =3D vb2_ioctl_reqbufs, + .vidioc_create_bufs =3D vb2_ioctl_create_bufs, + .vidioc_prepare_buf =3D vb2_ioctl_prepare_buf, + .vidioc_querybuf =3D vb2_ioctl_querybuf, + .vidioc_qbuf =3D vb2_ioctl_qbuf, + .vidioc_dqbuf =3D vb2_ioctl_dqbuf, + .vidioc_streamon =3D vb2_ioctl_streamon, + .vidioc_streamoff =3D vb2_ioctl_streamoff, + .vidioc_expbuf =3D vb2_ioctl_expbuf, + .vidioc_subscribe_event =3D v4l2_ctrl_subscribe_event, + .vidioc_unsubscribe_event =3D v4l2_event_unsubscribe, +}; + +static const struct v4l2_file_operations mtk_cam_v4l2_fops =3D { + .unlocked_ioctl =3D video_ioctl2, + .open =3D v4l2_fh_open, + .release =3D vb2_fop_release, + .poll =3D vb2_fop_poll, + .mmap =3D vb2_fop_mmap, +#ifdef CONFIG_COMPAT + .compat_ioctl32 =3D v4l2_compat_ioctl32, +#endif +}; + +/* -----------------------------------------------------------------------= ------ + * Init & Cleanup + */ + +static const u32 stream_out_fmts[] =3D { + /* The 1st entry is the default image format */ + V4L2_PIX_FMT_SBGGR8, + V4L2_PIX_FMT_SGBRG8, + V4L2_PIX_FMT_SGRBG8, + V4L2_PIX_FMT_SRGGB8, + V4L2_PIX_FMT_UYVY, + V4L2_PIX_FMT_VYUY, + V4L2_PIX_FMT_YUYV, + V4L2_PIX_FMT_YVYU, +}; + +static const struct mtk_cam_vdev_desc video_stream =3D { + .fmts =3D stream_out_fmts, + .num_fmts =3D ARRAY_SIZE(stream_out_fmts), + .frmsizes =3D + &(struct v4l2_frmsizeenum){ + .index =3D 0, + .type =3D V4L2_FRMSIZE_TYPE_CONTINUOUS, + .stepwise =3D { + .max_width =3D IMG_MAX_WIDTH, + .min_width =3D IMG_MIN_WIDTH, + .max_height =3D IMG_MAX_HEIGHT, + .min_height =3D IMG_MIN_HEIGHT, + .step_height =3D 1, + .step_width =3D 1, + }, + }, +}; + +int mtk_cam_video_register(struct mtk_cam_dev *cam) +{ + struct device *dev =3D cam->dev; + struct mtk_cam_video_device *cam_vdev =3D &cam->vdev; + struct video_device *vdev =3D &cam_vdev->vdev; + struct vb2_queue *vbq =3D &cam_vdev->vbq; + int ret; + + vb2_dma_contig_set_max_seg_size(cam->dev, DMA_BIT_MASK(32)); + + cam_vdev->desc =3D &video_stream; + + /* Initialize mtk_cam_video_device */ + mtk_cam_dev_load_default_fmt(cam); + + cam_vdev->vdev_pad.flags =3D MEDIA_PAD_FL_SOURCE; + + /* Initialize media entities */ + ret =3D media_entity_pads_init(&vdev->entity, 1, &cam_vdev->vdev_pad); + if (ret) { + dev_err(dev, "failed to initialize media pad:%d\n", ret); + return ret; + } + cam_vdev->vdev_pad.flags =3D MEDIA_PAD_FL_SINK; + + vbq->type =3D V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; + vbq->io_modes =3D VB2_MMAP | VB2_DMABUF; + vbq->dev =3D dev; + vbq->ops =3D &mtk_cam_vb2_ops; + vbq->mem_ops =3D &vb2_dma_contig_memops; + vbq->buf_struct_size =3D sizeof(struct mtk_cam_dev_buffer); + /* + * TODO: The hardware supports SOF interrupts, switch to a SOF + * timestamp source would give better accuracy, but first requires + * extending the V4L2 API to support it. + */ + vbq->timestamp_flags =3D V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC + | V4L2_BUF_FLAG_TSTAMP_SRC_EOF; + + /* No minimum buffers limitation */ + vbq->min_queued_buffers =3D 0; + vbq->drv_priv =3D cam; + + vbq->lock =3D &cam_vdev->vdev_lock; + ret =3D vb2_queue_init(vbq); + if (ret) { + dev_err(dev, "failed to init. vb2 queue:%d\n", ret); + goto fail_media_clean; + } + + /* Initialize vdev */ + snprintf(vdev->name, sizeof(vdev->name), "%s video stream", + dev_name(dev)); + + /* Set cap/type/ioctl_ops of the video device */ + vdev->device_caps =3D V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_STREAMING + | V4L2_CAP_IO_MC; + vdev->ioctl_ops =3D &mtk_cam_v4l2_vcap_ioctl_ops; + vdev->fops =3D &mtk_cam_v4l2_fops; + vdev->release =3D video_device_release_empty; + vdev->lock =3D &cam_vdev->vdev_lock; + vdev->v4l2_dev =3D cam->subdev.v4l2_dev; + vdev->queue =3D &cam_vdev->vbq; + vdev->vfl_dir =3D VFL_DIR_RX; + vdev->entity.function =3D MEDIA_ENT_F_IO_V4L; + video_set_drvdata(vdev, cam); + + /* Initialize miscellaneous variables */ + mutex_init(&cam_vdev->vdev_lock); + INIT_LIST_HEAD(&cam->buf_list); + + ret =3D video_register_device(vdev, VFL_TYPE_VIDEO, -1); + if (ret) { + dev_err(dev, "failed to register vde:%d\n", ret); + goto fail_vb2_rel; + } + + /* Create link between the video pad and the subdev pad. */ + ret =3D media_create_pad_link(&cam->subdev.entity, + MTK_CAM_CIO_PAD_VIDEO, + &vdev->entity, 0, + MEDIA_LNK_FL_IMMUTABLE + | MEDIA_LNK_FL_ENABLED); + if (ret) + goto fail_vdev_ureg; + + return 0; + +fail_vdev_ureg: + video_unregister_device(vdev); +fail_vb2_rel: + mutex_destroy(&cam_vdev->vdev_lock); + vb2_queue_release(vbq); +fail_media_clean: + media_entity_cleanup(&vdev->entity); + + return ret; +} + +void mtk_cam_video_unregister(struct mtk_cam_video_device *vdev) +{ + video_unregister_device(&vdev->vdev); + vb2_queue_release(&vdev->vbq); + media_entity_cleanup(&vdev->vdev.entity); + mutex_destroy(&vdev->vdev_lock); + vb2_dma_contig_clear_max_seg_size(&vdev->vdev.dev); +} --=20 2.47.0 From nobody Sun Nov 24 05:51:41 2024 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE2F71CACEB for ; Thu, 21 Nov 2024 08:53:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732179205; cv=none; b=Nsf1fm1Kwm787lLV86+OKPigKqeD0oPDlUYr+viuKFq7dWMgcSdB2de/Rx/q+Yz9JDeodxr173OZ/wiVEb7w+CNH2JQVkZ5a8XVMQV4Td/3GxnyNM8o84G2WyyCfAtG5BKWTx/tKZN+p0hgOc8weSnd3jYH2iIOLcZo9DprfE0Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732179205; c=relaxed/simple; bh=vO0NUTf39JA9CFefBGrsZh8fB/IWZjp1lI/XOU0bfnk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AvToG3DgHxI4hVK5BZjRU3nw9T16dtXg4fgWmNiKsbf6iJWNTbUsoJiIf5J3pHiKGfWus2wHrD9n0jtG4lqwnbb8+HDgUDseebXXqiKRYiS1hkjXNzjS1pZIEW1Vhu5tV0RGiKQXm4A7RMv4bj7hSE+hVyH4EAfqMBaLSZnEQh4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=twSSky7P; arc=none smtp.client-ip=209.85.221.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="twSSky7P" Received: by mail-wr1-f45.google.com with SMTP id ffacd0b85a97d-37ed3bd6114so374576f8f.2 for ; Thu, 21 Nov 2024 00:53:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1732179201; x=1732784001; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=sA8zIvCeVehOTON6gWSJevS8rNPym+2I4qMSEQq/Vfs=; b=twSSky7P+R5J1YPy9le5oMqF7TWKJ9mw9tmmc+3BiF2+PeuHbOSihsXL3KhIC6tcEt YE1WGhebPEfQMJdY+hYtAo7X3zcNkOR38QFzT8k6d2VfcT/8EXG/qUpieVmQj8iPxplQ wyMD6j4IaTT4sdzMNpoDhUmzoQevgNVB+mcMiVjGmoZ91UCh8FPofGJktbNIovdgDauA XukG3Xz9w7680erWwYr/xUQ8HtlydhAu6I0xjx7fx2L72hu5cyDiRi3mkLKdkvKOa+sr mzjQJx+dOS1dRFb6xYw9c4cKaXP5mD+CP3vNj28rTr7cPBEdQVBvgCbUAj9gdc3V9WkT SGrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732179201; x=1732784001; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sA8zIvCeVehOTON6gWSJevS8rNPym+2I4qMSEQq/Vfs=; b=FoR93Z2FqHzxoaMAL9YZ51BaRC+YUT+bM32Ptg590F8lo1NmW23O9XJA7yrbYzh5cg g0YZXU4hwZtxcG5kUy+2eqraNW+Nc0kCN688f6tkYhcGELdBeFLHJYTQTNYs5UPuvR09 jNjeI9swjNLJ07RHwiXH7D3wQag+gcm4ldPTd6as1HJxhjvmCgsLroHQVd7H5qoPXNr6 +9l1dH5DbU83MGhX9Ber9sTjqlglKlQao3UdtD9uG+JOonUQJBv3Ksh0xXrJqxEDsd/q d59/O7QKcMuscoEj4KJVHcb/6iI5p9XQTv4IPjiBWYCsfflDjHfO2LG6jkfhc1JOryNi +5OQ== X-Forwarded-Encrypted: i=1; AJvYcCVCmuPXqz7u3ltvGuFfA8TJ37XgW/rL2m0iAC1BhoQt8uK+3MaAtOwtreLv4YkMHT8Qg4QX1e/0bxAJxT8=@vger.kernel.org X-Gm-Message-State: AOJu0YwWkk7zvZ11auPzkBPlvxGCNckE595A483ybYCkVCCtW+wjQ2xz IZmxsDOwA0dqRotrST0z0vulrYqx/dhKOtEHrwW2SonyC8g33jqqCteorEwIXCQ= X-Gm-Gg: ASbGncs27AenKSET4GFvKNoQbKoIFvJcO+IZb1TwFH2g9+K/p3KAcbPVNeapYAf10mo h/sJ556z4ljOop49bn3TD1dqPAYnwXqMmh3DsCMPkdUZZ6ys4qsJMhbwj/3ssJ1ou/a1DfVlI4f LAtakUML3PXrOGlvCmgrdKt5FHWS8R2sON5epgTIAH3oGCt/u2rxdHDX842S2GKoiYSptqOurOo q0PQsMVT++vxYLXyIhH5YVAGoA5yr6wnIJDuqx9UnDrmdiyLXwL2bkfD4lHGUF4S412HjHYBxWU fWH3RmCgb/lPoOQ9VNMIy6u4TkyDoxCt5pOzlpqmTV8= X-Google-Smtp-Source: AGHT+IEb1ziv6SCjdyDQL96zzjg5G/z4Gi8F8wOiJmIAV34djYMshwdbu/LEIi6CkwPFG6A8w8/SPQ== X-Received: by 2002:a5d:584a:0:b0:382:5492:4670 with SMTP id ffacd0b85a97d-38254b163c4mr4639144f8f.40.1732179201134; Thu, 21 Nov 2024 00:53:21 -0800 (PST) Received: from [192.168.42.0] (2a02-842a-d52e-6101-6fd0-06c4-5d68-f0a5.rev.sfr.net. [2a02:842a:d52e:6101:6fd0:6c4:5d68:f0a5]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-382549111fdsm4219900f8f.58.2024.11.21.00.53.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2024 00:53:20 -0800 (PST) From: Julien Stephan Date: Thu, 21 Nov 2024 09:53:19 +0100 Subject: [PATCH v7 5/5] arm64: dts: mediatek: mt8365: Add support for camera Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241121-add-mtk-isp-3-0-support-v7-5-b04dc9610619@baylibre.com> References: <20241121-add-mtk-isp-3-0-support-v7-0-b04dc9610619@baylibre.com> In-Reply-To: <20241121-add-mtk-isp-3-0-support-v7-0-b04dc9610619@baylibre.com> To: Laurent Pinchart , Andy Hsieh , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Julien Stephan X-Mailer: b4 0.14.2 Add base support for cameras for mt8365 platforms. This requires nodes for the sensor interface, camsv, and CSI receivers. Reviewed-by: Laurent Pinchart Signed-off-by: Julien Stephan --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 125 +++++++++++++++++++++++++++= ++++ 1 file changed, 125 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts= /mediatek/mt8365.dtsi index 9c91fe8ea0f969770a611f90b593683f93ff3e22..f3aae8d76cbece5779fe0b23139= d594c0ea52579 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include =20 / { compatible =3D "mediatek,mt8365"; @@ -704,6 +705,23 @@ ethernet: ethernet@112a0000 { status =3D "disabled"; }; =20 + mipi_csi0: mipi-csi0@11c10000 { + compatible =3D "mediatek,mt8365-csi-rx"; + reg =3D <0 0x11c10000 0 0x2000>; + status =3D "disabled"; + num-lanes =3D <4>; + #phy-cells =3D <1>; + }; + + mipi_csi1: mipi-csi1@11c12000 { + compatible =3D "mediatek,mt8365-csi-rx"; + reg =3D <0 0x11c12000 0 0x2000>; + phy-type =3D ; + status =3D "disabled"; + num-lanes =3D <4>; + #phy-cells =3D <0>; + }; + u3phy: t-phy@11cc0000 { compatible =3D "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; #address-cells =3D <1>; @@ -774,6 +792,113 @@ larb2: larb@15001000 { mediatek,larb-id =3D <2>; }; =20 + seninf: seninf@15040000 { + compatible =3D "mediatek,mt8365-seninf"; + reg =3D <0 0x15040000 0 0x6000>; + interrupts =3D ; + clocks =3D <&camsys CLK_CAM_SENIF>, + <&topckgen CLK_TOP_SENIF_SEL>; + clock-names =3D "camsys", "top_mux"; + + power-domains =3D <&spm MT8365_POWER_DOMAIN_CAM>; + + phys =3D <&mipi_csi0 PHY_TYPE_DPHY>, <&mipi_csi1>; + phy-names =3D "csi0", "csi1"; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + }; + + port@2 { + reg =3D <2>; + }; + + port@3 { + reg =3D <3>; + }; + + port@4 { + reg =3D <4>; + seninf_camsv1_endpoint: endpoint { + remote-endpoint =3D + <&camsv1_endpoint>; + }; + }; + + port@5 { + reg =3D <5>; + seninf_camsv2_endpoint: endpoint { + remote-endpoint =3D + <&camsv2_endpoint>; + }; + }; + }; + }; + + camsv1: camsv@15050000 { + compatible =3D "mediatek,mt8365-camsv"; + reg =3D <0 0x15050000 0 0x0040>, + <0 0x15050208 0 0x0020>, + <0 0x15050400 0 0x0100>; + interrupts =3D ; + clocks =3D <&camsys CLK_CAM>, + <&camsys CLK_CAMTG>, + <&camsys CLK_CAMSV0>; + clock-names =3D "cam", "camtg", "camsv"; + iommus =3D <&iommu M4U_PORT_CAM_IMGO>; + mediatek,larb =3D <&larb2>; + power-domains =3D <&spm MT8365_POWER_DOMAIN_CAM>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + port@0 { + reg =3D <0>; + camsv1_endpoint: endpoint { + remote-endpoint =3D <&seninf_camsv1_endpoint>; + }; + }; + }; + }; + + camsv2: camsv@15050800 { + compatible =3D "mediatek,mt8365-camsv"; + reg =3D <0 0x15050800 0 0x0040>, + <0 0x15050228 0 0x0020>, + <0 0x15050c00 0 0x0100>; + interrupts =3D ; + clocks =3D <&camsys CLK_CAM>, + <&camsys CLK_CAMTG>, + <&camsys CLK_CAMSV1>; + clock-names =3D "cam", "camtg", "camsv"; + iommus =3D <&iommu M4U_PORT_CAM_IMGO>; + mediatek,larb =3D <&larb2>; + power-domains =3D <&spm MT8365_POWER_DOMAIN_CAM>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + port@0 { + reg =3D <0>; + camsv2_endpoint: endpoint { + remote-endpoint =3D <&seninf_camsv2_endpoint>; + }; + }; + }; + }; + vdecsys: syscon@16000000 { compatible =3D "mediatek,mt8365-vdecsys", "syscon"; reg =3D <0 0x16000000 0 0x1000>; --=20 2.47.0