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([145.224.90.249]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa20e046932sm774520766b.170.2024.11.20.06.38.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Nov 2024 06:38:03 -0800 (PST) From: James Clark To: linux-perf-users@vger.kernel.org Cc: James Clark , John Garry , Will Deacon , Mike Leach , Leo Yan , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] perf vendor events arm64: Update N2/V2 events from source Date: Wed, 20 Nov 2024 14:37:31 +0000 Message-Id: <20241120143739.243728-1-james.clark@linaro.org> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update using the new data [1] for these changes: * Scale some metrics like dtlb_walk_ratio to percent so they display better with Perf's 2 dp precision * Description typos, grammar and clarifications * Unnecessary metric formula brackets seem to have been removed in the source but this is not a functional change * New sve_all_percentage metric The following command was used to generate this commit: $ telemetry-solution/tools/perf_json_generator/generate.py \ tools/perf/ --telemetry-files \ telemetry-solution/data/pmu/cpu/neoverse/neoverse-v2.json:neoverse-n2-v2 [1]: https://gitlab.arm.com/telemetry-solution/telemetry-solution/-/blob/ma= in/data/pmu/cpu/neoverse/neoverse-v2.json Signed-off-by: James Clark Reviewed-by: Ian Rogers --- .../arm64/arm/neoverse-n2-v2/exception.json | 2 +- .../arm64/arm/neoverse-n2-v2/general.json | 2 +- .../arm64/arm/neoverse-n2-v2/l1d_cache.json | 6 +- .../arm64/arm/neoverse-n2-v2/l2_cache.json | 14 +-- .../arm64/arm/neoverse-n2-v2/l3_cache.json | 4 +- .../arm64/arm/neoverse-n2-v2/ll_cache.json | 4 +- .../arch/arm64/arm/neoverse-n2-v2/memory.json | 2 +- .../arm64/arm/neoverse-n2-v2/metrics.json | 93 ++++++++++--------- .../arm64/arm/neoverse-n2-v2/retired.json | 4 +- .../arm/neoverse-n2-v2/spec_operation.json | 14 +-- .../arch/arm64/arm/neoverse-n2-v2/stall.json | 8 +- .../arch/arm64/arm/neoverse-n2-v2/tlb.json | 4 +- 12 files changed, 82 insertions(+), 75 deletions(-) diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/exception.= json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/exception.json index 4404b8e91690..7126fbf292e0 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/exception.json +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/exception.json @@ -5,7 +5,7 @@ }, { "ArchStdEvent": "EXC_RETURN", - "PublicDescription": "Counts any architecturally executed exceptio= n return instructions. Eg: AArch64: ERET" + "PublicDescription": "Counts any architecturally executed exceptio= n return instructions. For example: AArch64: ERET" }, { "ArchStdEvent": "EXC_UNDEF", diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/general.js= on b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/general.json index 428810f855b8..c5dcdcf43c58 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/general.json +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/general.json @@ -5,6 +5,6 @@ }, { "ArchStdEvent": "CNT_CYCLES", - "PublicDescription": "Counts constant frequency cycles" + "PublicDescription": "Increments at a constant frequency equal to = the rate of increment of the System Counter, CNTPCT_EL0." } ] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l1d_cache.= json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l1d_cache.json index da7c129f2569..799d106d5173 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l1d_cache.json +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l1d_cache.json @@ -1,11 +1,11 @@ [ { "ArchStdEvent": "L1D_CACHE_REFILL", - "PublicDescription": "Counts level 1 data cache refills caused by = speculatively executed load or store operations that missed in the level 1 = data cache. This event only counts one event per cache line. This event doe= s not count cache line allocations from preload instructions or from hardwa= re cache prefetching." + "PublicDescription": "Counts level 1 data cache refills caused by = speculatively executed load or store operations that missed in the level 1 = data cache. This event only counts one event per cache line." }, { "ArchStdEvent": "L1D_CACHE", - "PublicDescription": "Counts level 1 data cache accesses from any = load/store operations. Atomic operations that resolve in the CPUs caches (n= ear atomic operations) count as both a write access and read access. Each a= ccess to a cache line is counted including the multiple accesses caused by = single instructions such as LDM or STM. Each access to other level 1 data o= r unified memory structures, for example refill buffers, write buffers, and= write-back buffers, are also counted." + "PublicDescription": "Counts level 1 data cache accesses from any = load/store operations. Atomic operations that resolve in the CPUs caches (n= ear atomic operations) counts as both a write access and read access. Each = access to a cache line is counted including the multiple accesses caused by= single instructions such as LDM or STM. Each access to other level 1 data = or unified memory structures, for example refill buffers, write buffers, an= d write-back buffers, are also counted." }, { "ArchStdEvent": "L1D_CACHE_WB", @@ -17,7 +17,7 @@ }, { "ArchStdEvent": "L1D_CACHE_RD", - "PublicDescription": "Counts level 1 data cache accesses from any = load operation. Atomic load operations that resolve in the CPUs caches coun= t as both a write access and read access." + "PublicDescription": "Counts level 1 data cache accesses from any = load operation. Atomic load operations that resolve in the CPUs caches coun= ts as both a write access and read access." }, { "ArchStdEvent": "L1D_CACHE_WR", diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l2_cache.j= son b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l2_cache.json index 0e31d0daf88b..ed8291ab9737 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l2_cache.json +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l2_cache.json @@ -1,11 +1,11 @@ [ { "ArchStdEvent": "L2D_CACHE", - "PublicDescription": "Counts level 2 cache accesses. level 2 cache= is a unified cache for data and instruction accesses. Accesses are for mis= ses in the first level caches or translation resolutions due to accesses. T= his event also counts write back of dirty data from level 1 data cache to t= he L2 cache." + "PublicDescription": "Counts accesses to the level 2 cache due to = data accesses. Level 2 cache is a unified cache for data and instruction ac= cesses. Accesses are for misses in the first level data cache or translatio= n resolutions due to accesses. This event also counts write back of dirty d= ata from level 1 data cache to the L2 cache." }, { "ArchStdEvent": "L2D_CACHE_REFILL", - "PublicDescription": "Counts cache line refills into the level 2 c= ache. level 2 cache is a unified cache for data and instruction accesses. A= ccesses are for misses in the level 1 caches or translation resolutions due= to accesses." + "PublicDescription": "Counts cache line refills into the level 2 c= ache. Level 2 cache is a unified cache for data and instruction accesses. A= ccesses are for misses in the level 1 data cache or translation resolutions= due to accesses." }, { "ArchStdEvent": "L2D_CACHE_WB", @@ -13,23 +13,23 @@ }, { "ArchStdEvent": "L2D_CACHE_ALLOCATE", - "PublicDescription": "TBD" + "PublicDescription": "Counts level 2 cache line allocates that do = not fetch data from outside the level 2 data or unified cache." }, { "ArchStdEvent": "L2D_CACHE_RD", - "PublicDescription": "Counts level 2 cache accesses due to memory = read operations. level 2 cache is a unified cache for data and instruction = accesses, accesses are for misses in the level 1 caches or translation reso= lutions due to accesses." + "PublicDescription": "Counts level 2 data cache accesses due to me= mory read operations. Level 2 cache is a unified cache for data and instruc= tion accesses, accesses are for misses in the level 1 data cache or transla= tion resolutions due to accesses." }, { "ArchStdEvent": "L2D_CACHE_WR", - "PublicDescription": "Counts level 2 cache accesses due to memory = write operations. level 2 cache is a unified cache for data and instruction= accesses, accesses are for misses in the level 1 caches or translation res= olutions due to accesses." + "PublicDescription": "Counts level 2 cache accesses due to memory = write operations. Level 2 cache is a unified cache for data and instruction= accesses, accesses are for misses in the level 1 data cache or translation= resolutions due to accesses." }, { "ArchStdEvent": "L2D_CACHE_REFILL_RD", - "PublicDescription": "Counts refills for memory accesses due to me= mory read operation counted by L2D_CACHE_RD. level 2 cache is a unified cac= he for data and instruction accesses, accesses are for misses in the level = 1 caches or translation resolutions due to accesses." + "PublicDescription": "Counts refills for memory accesses due to me= mory read operation counted by L2D_CACHE_RD. Level 2 cache is a unified cac= he for data and instruction accesses, accesses are for misses in the level = 1 data cache or translation resolutions due to accesses." }, { "ArchStdEvent": "L2D_CACHE_REFILL_WR", - "PublicDescription": "Counts refills for memory accesses due to me= mory write operation counted by L2D_CACHE_WR. level 2 cache is a unified ca= che for data and instruction accesses, accesses are for misses in the level= 1 caches or translation resolutions due to accesses." + "PublicDescription": "Counts refills for memory accesses due to me= mory write operation counted by L2D_CACHE_WR. Level 2 cache is a unified ca= che for data and instruction accesses, accesses are for misses in the level= 1 data cache or translation resolutions due to accesses." }, { "ArchStdEvent": "L2D_CACHE_WB_VICTIM", diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l3_cache.j= son b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l3_cache.json index 45bfba532df7..4a2e72fc5ada 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l3_cache.json +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/l3_cache.json @@ -9,11 +9,11 @@ }, { "ArchStdEvent": "L3D_CACHE", - "PublicDescription": "Counts level 3 cache accesses. level 3 cache= is a unified cache for data and instruction accesses. Accesses are for mis= ses in the lower level caches or translation resolutions due to accesses." + "PublicDescription": "Counts level 3 cache accesses. Level 3 cache= is a unified cache for data and instruction accesses. Accesses are for mis= ses in the lower level caches or translation resolutions due to accesses." }, { "ArchStdEvent": "L3D_CACHE_RD", - "PublicDescription": "TBD" + "PublicDescription": "Counts level 3 cache accesses caused by any = memory read operation. Level 3 cache is a unified cache for data and instru= ction accesses. Accesses are for misses in the lower level caches or transl= ation resolutions due to accesses." }, { "ArchStdEvent": "L3D_CACHE_LMISS_RD", diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ll_cache.j= son b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ll_cache.json index bb712d57d58a..fd5a2e0099b8 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ll_cache.json +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ll_cache.json @@ -1,10 +1,10 @@ [ { "ArchStdEvent": "LL_CACHE_RD", - "PublicDescription": "Counts read transactions that were returned = from outside the core cluster. This event counts when the system register C= PUECTLR.EXTLLC bit is set. This event counts read transactions returned fro= m outside the core if those transactions are either hit in the system level= cache or missed in the SLC and are returned from any other external source= s." + "PublicDescription": "Counts read transactions that were returned = from outside the core cluster. This event counts for external last level ca= che when the system register CPUECTLR.EXTLLC bit is set, otherwise it coun= ts for the L3 cache. This event counts read transactions returned from outs= ide the core if those transactions are either hit in the system level cache= or missed in the SLC and are returned from any other external sources." }, { "ArchStdEvent": "LL_CACHE_MISS_RD", - "PublicDescription": "Counts read transactions that were returned = from outside the core cluster but missed in the system level cache. This ev= ent counts when the system register CPUECTLR.EXTLLC bit is set. This event = counts read transactions returned from outside the core if those transactio= ns are missed in the System level Cache. The data source of the transaction= is indicated by a field in the CHI transaction returning to the CPU. This = event does not count reads caused by cache maintenance operations." + "PublicDescription": "Counts read transactions that were returned = from outside the core cluster but missed in the system level cache. This ev= ent counts for external last level cache when the system register CPUECTLR.= EXTLLC bit is set, otherwise it counts for L3 cache. This event counts read= transactions returned from outside the core if those transactions are miss= ed in the System level Cache. The data source of the transaction is indicat= ed by a field in the CHI transaction returning to the CPU. This event does = not count reads caused by cache maintenance operations." } ] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/memory.jso= n b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/memory.json index 106a97f8b2e7..bb3491012a8f 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/memory.json +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/memory.json @@ -33,7 +33,7 @@ }, { "ArchStdEvent": "MEM_ACCESS_CHECKED", - "PublicDescription": "Counts the number of memory read and write a= ccesses in a cycle that are tag checked by the Memory Tagging Extension (MT= E)." + "PublicDescription": "Counts the number of memory read and write a= ccesses counted by MEM_ACCESS that are tag checked by the Memory Tagging Ex= tension (MTE). This event is implemented as the sum of MEM_ACCESS_CHECKED_R= D and MEM_ACCESS_CHECKED_WR" }, { "ArchStdEvent": "MEM_ACCESS_CHECKED_RD", diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/metrics.js= on b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/metrics.json index 5f449270b448..97d352f94323 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/metrics.json +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/metrics.json @@ -5,7 +5,7 @@ }, { "MetricName": "backend_stalled_cycles", - "MetricExpr": "((STALL_BACKEND / CPU_CYCLES) * 100)", + "MetricExpr": "STALL_BACKEND / CPU_CYCLES * 100", "BriefDescription": "This metric is the percentage of cycles that = were stalled due to resource constraints in the backend unit of the process= or.", "MetricGroup": "Cycle_Accounting", "ScaleUnit": "1percent of cycles" @@ -16,45 +16,45 @@ }, { "MetricName": "branch_misprediction_ratio", - "MetricExpr": "(BR_MIS_PRED_RETIRED / BR_RETIRED)", + "MetricExpr": "BR_MIS_PRED_RETIRED / BR_RETIRED", "BriefDescription": "This metric measures the ratio of branches mi= spredicted to the total number of branches architecturally executed. This g= ives an indication of the effectiveness of the branch prediction unit.", "MetricGroup": "Miss_Ratio;Branch_Effectiveness", - "ScaleUnit": "1per branch" + "ScaleUnit": "100percent of branches" }, { "MetricName": "branch_mpki", - "MetricExpr": "((BR_MIS_PRED_RETIRED / INST_RETIRED) * 1000)", + "MetricExpr": "BR_MIS_PRED_RETIRED / INST_RETIRED * 1000", "BriefDescription": "This metric measures the number of branch mis= predictions per thousand instructions executed.", "MetricGroup": "MPKI;Branch_Effectiveness", "ScaleUnit": "1MPKI" }, { "MetricName": "branch_percentage", - "MetricExpr": "(((BR_IMMED_SPEC + BR_INDIRECT_SPEC) / INST_SPEC) *= 100)", + "MetricExpr": "(BR_IMMED_SPEC + BR_INDIRECT_SPEC) / INST_SPEC * 10= 0", "BriefDescription": "This metric measures branch operations as a p= ercentage of operations speculatively executed.", "MetricGroup": "Operation_Mix", "ScaleUnit": "1percent of operations" }, { "MetricName": "crypto_percentage", - "MetricExpr": "((CRYPTO_SPEC / INST_SPEC) * 100)", + "MetricExpr": "CRYPTO_SPEC / INST_SPEC * 100", "BriefDescription": "This metric measures crypto operations as a p= ercentage of operations speculatively executed.", "MetricGroup": "Operation_Mix", "ScaleUnit": "1percent of operations" }, { "MetricName": "dtlb_mpki", - "MetricExpr": "((DTLB_WALK / INST_RETIRED) * 1000)", + "MetricExpr": "DTLB_WALK / INST_RETIRED * 1000", "BriefDescription": "This metric measures the number of data TLB W= alks per thousand instructions executed.", "MetricGroup": "MPKI;DTLB_Effectiveness", "ScaleUnit": "1MPKI" }, { "MetricName": "dtlb_walk_ratio", - "MetricExpr": "(DTLB_WALK / L1D_TLB)", + "MetricExpr": "DTLB_WALK / L1D_TLB", "BriefDescription": "This metric measures the ratio of data TLB Wa= lks to the total number of data TLB accesses. This gives an indication of t= he effectiveness of the data TLB accesses.", "MetricGroup": "Miss_Ratio;DTLB_Effectiveness", - "ScaleUnit": "1per TLB access" + "ScaleUnit": "100percent of TLB accesses" }, { "ArchStdEvent": "frontend_bound", @@ -62,147 +62,147 @@ }, { "MetricName": "frontend_stalled_cycles", - "MetricExpr": "((STALL_FRONTEND / CPU_CYCLES) * 100)", + "MetricExpr": "STALL_FRONTEND / CPU_CYCLES * 100", "BriefDescription": "This metric is the percentage of cycles that = were stalled due to resource constraints in the frontend unit of the proces= sor.", "MetricGroup": "Cycle_Accounting", "ScaleUnit": "1percent of cycles" }, { "MetricName": "integer_dp_percentage", - "MetricExpr": "((DP_SPEC / INST_SPEC) * 100)", + "MetricExpr": "DP_SPEC / INST_SPEC * 100", "BriefDescription": "This metric measures scalar integer operation= s as a percentage of operations speculatively executed.", "MetricGroup": "Operation_Mix", "ScaleUnit": "1percent of operations" }, { "MetricName": "ipc", - "MetricExpr": "(INST_RETIRED / CPU_CYCLES)", + "MetricExpr": "INST_RETIRED / CPU_CYCLES", "BriefDescription": "This metric measures the number of instructio= ns retired per cycle.", "MetricGroup": "General", "ScaleUnit": "1per cycle" }, { "MetricName": "itlb_mpki", - "MetricExpr": "((ITLB_WALK / INST_RETIRED) * 1000)", + "MetricExpr": "ITLB_WALK / INST_RETIRED * 1000", "BriefDescription": "This metric measures the number of instructio= n TLB Walks per thousand instructions executed.", "MetricGroup": "MPKI;ITLB_Effectiveness", "ScaleUnit": "1MPKI" }, { "MetricName": "itlb_walk_ratio", - "MetricExpr": "(ITLB_WALK / L1I_TLB)", + "MetricExpr": "ITLB_WALK / L1I_TLB", "BriefDescription": "This metric measures the ratio of instruction= TLB Walks to the total number of instruction TLB accesses. This gives an i= ndication of the effectiveness of the instruction TLB accesses.", "MetricGroup": "Miss_Ratio;ITLB_Effectiveness", - "ScaleUnit": "1per TLB access" + "ScaleUnit": "100percent of TLB accesses" }, { "MetricName": "l1d_cache_miss_ratio", - "MetricExpr": "(L1D_CACHE_REFILL / L1D_CACHE)", + "MetricExpr": "L1D_CACHE_REFILL / L1D_CACHE", "BriefDescription": "This metric measures the ratio of level 1 dat= a cache accesses missed to the total number of level 1 data cache accesses.= This gives an indication of the effectiveness of the level 1 data cache.", "MetricGroup": "Miss_Ratio;L1D_Cache_Effectiveness", - "ScaleUnit": "1per cache access" + "ScaleUnit": "100percent of cache accesses" }, { "MetricName": "l1d_cache_mpki", - "MetricExpr": "((L1D_CACHE_REFILL / INST_RETIRED) * 1000)", + "MetricExpr": "L1D_CACHE_REFILL / INST_RETIRED * 1000", "BriefDescription": "This metric measures the number of level 1 da= ta cache accesses missed per thousand instructions executed.", "MetricGroup": "MPKI;L1D_Cache_Effectiveness", "ScaleUnit": "1MPKI" }, { "MetricName": "l1d_tlb_miss_ratio", - "MetricExpr": "(L1D_TLB_REFILL / L1D_TLB)", + "MetricExpr": "L1D_TLB_REFILL / L1D_TLB", "BriefDescription": "This metric measures the ratio of level 1 dat= a TLB accesses missed to the total number of level 1 data TLB accesses. Thi= s gives an indication of the effectiveness of the level 1 data TLB.", "MetricGroup": "Miss_Ratio;DTLB_Effectiveness", - "ScaleUnit": "1per TLB access" + "ScaleUnit": "100percent of TLB accesses" }, { "MetricName": "l1d_tlb_mpki", - "MetricExpr": "((L1D_TLB_REFILL / INST_RETIRED) * 1000)", - "BriefDescription": "This metric measures the number of level 1 in= struction TLB accesses missed per thousand instructions executed.", + "MetricExpr": "L1D_TLB_REFILL / INST_RETIRED * 1000", + "BriefDescription": "This metric measures the number of level 1 da= ta TLB accesses missed per thousand instructions executed.", "MetricGroup": "MPKI;DTLB_Effectiveness", "ScaleUnit": "1MPKI" }, { "MetricName": "l1i_cache_miss_ratio", - "MetricExpr": "(L1I_CACHE_REFILL / L1I_CACHE)", + "MetricExpr": "L1I_CACHE_REFILL / L1I_CACHE", "BriefDescription": "This metric measures the ratio of level 1 ins= truction cache accesses missed to the total number of level 1 instruction c= ache accesses. This gives an indication of the effectiveness of the level 1= instruction cache.", "MetricGroup": "Miss_Ratio;L1I_Cache_Effectiveness", - "ScaleUnit": "1per cache access" + "ScaleUnit": "100percent of cache accesses" }, { "MetricName": "l1i_cache_mpki", - "MetricExpr": "((L1I_CACHE_REFILL / INST_RETIRED) * 1000)", + "MetricExpr": "L1I_CACHE_REFILL / INST_RETIRED * 1000", "BriefDescription": "This metric measures the number of level 1 in= struction cache accesses missed per thousand instructions executed.", "MetricGroup": "MPKI;L1I_Cache_Effectiveness", "ScaleUnit": "1MPKI" }, { "MetricName": "l1i_tlb_miss_ratio", - "MetricExpr": "(L1I_TLB_REFILL / L1I_TLB)", + "MetricExpr": "L1I_TLB_REFILL / L1I_TLB", "BriefDescription": "This metric measures the ratio of level 1 ins= truction TLB accesses missed to the total number of level 1 instruction TLB= accesses. This gives an indication of the effectiveness of the level 1 ins= truction TLB.", "MetricGroup": "Miss_Ratio;ITLB_Effectiveness", - "ScaleUnit": "1per TLB access" + "ScaleUnit": "100percent of TLB accesses" }, { "MetricName": "l1i_tlb_mpki", - "MetricExpr": "((L1I_TLB_REFILL / INST_RETIRED) * 1000)", + "MetricExpr": "L1I_TLB_REFILL / INST_RETIRED * 1000", "BriefDescription": "This metric measures the number of level 1 in= struction TLB accesses missed per thousand instructions executed.", "MetricGroup": "MPKI;ITLB_Effectiveness", "ScaleUnit": "1MPKI" }, { "MetricName": "l2_cache_miss_ratio", - "MetricExpr": "(L2D_CACHE_REFILL / L2D_CACHE)", + "MetricExpr": "L2D_CACHE_REFILL / L2D_CACHE", "BriefDescription": "This metric measures the ratio of level 2 cac= he accesses missed to the total number of level 2 cache accesses. This give= s an indication of the effectiveness of the level 2 cache, which is a unifi= ed cache that stores both data and instruction. Note that cache accesses in= this cache are either data memory access or instruction fetch as this is a= unified cache.", "MetricGroup": "Miss_Ratio;L2_Cache_Effectiveness", - "ScaleUnit": "1per cache access" + "ScaleUnit": "100percent of cache accesses" }, { "MetricName": "l2_cache_mpki", - "MetricExpr": "((L2D_CACHE_REFILL / INST_RETIRED) * 1000)", + "MetricExpr": "L2D_CACHE_REFILL / INST_RETIRED * 1000", "BriefDescription": "This metric measures the number of level 2 un= ified cache accesses missed per thousand instructions executed. Note that c= ache accesses in this cache are either data memory access or instruction fe= tch as this is a unified cache.", "MetricGroup": "MPKI;L2_Cache_Effectiveness", "ScaleUnit": "1MPKI" }, { "MetricName": "l2_tlb_miss_ratio", - "MetricExpr": "(L2D_TLB_REFILL / L2D_TLB)", + "MetricExpr": "L2D_TLB_REFILL / L2D_TLB", "BriefDescription": "This metric measures the ratio of level 2 uni= fied TLB accesses missed to the total number of level 2 unified TLB accesse= s. This gives an indication of the effectiveness of the level 2 TLB.", "MetricGroup": "Miss_Ratio;ITLB_Effectiveness;DTLB_Effectiveness", - "ScaleUnit": "1per TLB access" + "ScaleUnit": "100percent of TLB accesses" }, { "MetricName": "l2_tlb_mpki", - "MetricExpr": "((L2D_TLB_REFILL / INST_RETIRED) * 1000)", + "MetricExpr": "L2D_TLB_REFILL / INST_RETIRED * 1000", "BriefDescription": "This metric measures the number of level 2 un= ified TLB accesses missed per thousand instructions executed.", "MetricGroup": "MPKI;ITLB_Effectiveness;DTLB_Effectiveness", "ScaleUnit": "1MPKI" }, { "MetricName": "ll_cache_read_hit_ratio", - "MetricExpr": "((LL_CACHE_RD - LL_CACHE_MISS_RD) / LL_CACHE_RD)", + "MetricExpr": "(LL_CACHE_RD - LL_CACHE_MISS_RD) / LL_CACHE_RD", "BriefDescription": "This metric measures the ratio of last level = cache read accesses hit in the cache to the total number of last level cach= e accesses. This gives an indication of the effectiveness of the last level= cache for read traffic. Note that cache accesses in this cache are either = data memory access or instruction fetch as this is a system level cache.", "MetricGroup": "LL_Cache_Effectiveness", - "ScaleUnit": "1per cache access" + "ScaleUnit": "100percent of cache accesses" }, { "MetricName": "ll_cache_read_miss_ratio", - "MetricExpr": "(LL_CACHE_MISS_RD / LL_CACHE_RD)", + "MetricExpr": "LL_CACHE_MISS_RD / LL_CACHE_RD", "BriefDescription": "This metric measures the ratio of last level = cache read accesses missed to the total number of last level cache accesses= . This gives an indication of the effectiveness of the last level cache for= read traffic. Note that cache accesses in this cache are either data memor= y access or instruction fetch as this is a system level cache.", "MetricGroup": "Miss_Ratio;LL_Cache_Effectiveness", - "ScaleUnit": "1per cache access" + "ScaleUnit": "100percent of cache accesses" }, { "MetricName": "ll_cache_read_mpki", - "MetricExpr": "((LL_CACHE_MISS_RD / INST_RETIRED) * 1000)", + "MetricExpr": "LL_CACHE_MISS_RD / INST_RETIRED * 1000", "BriefDescription": "This metric measures the number of last level= cache read accesses missed per thousand instructions executed.", "MetricGroup": "MPKI;LL_Cache_Effectiveness", "ScaleUnit": "1MPKI" }, { "MetricName": "load_percentage", - "MetricExpr": "((LD_SPEC / INST_SPEC) * 100)", + "MetricExpr": "LD_SPEC / INST_SPEC * 100", "BriefDescription": "This metric measures load operations as a per= centage of operations speculatively executed.", "MetricGroup": "Operation_Mix", "ScaleUnit": "1percent of operations" @@ -213,21 +213,21 @@ }, { "MetricName": "scalar_fp_percentage", - "MetricExpr": "((VFP_SPEC / INST_SPEC) * 100)", + "MetricExpr": "VFP_SPEC / INST_SPEC * 100", "BriefDescription": "This metric measures scalar floating point op= erations as a percentage of operations speculatively executed.", "MetricGroup": "Operation_Mix", "ScaleUnit": "1percent of operations" }, { "MetricName": "simd_percentage", - "MetricExpr": "((ASE_SPEC / INST_SPEC) * 100)", + "MetricExpr": "ASE_SPEC / INST_SPEC * 100", "BriefDescription": "This metric measures advanced SIMD operations= as a percentage of total operations speculatively executed.", "MetricGroup": "Operation_Mix", "ScaleUnit": "1percent of operations" }, { "MetricName": "store_percentage", - "MetricExpr": "((ST_SPEC / INST_SPEC) * 100)", + "MetricExpr": "ST_SPEC / INST_SPEC * 100", "BriefDescription": "This metric measures store operations as a pe= rcentage of operations speculatively executed.", "MetricGroup": "Operation_Mix", "ScaleUnit": "1percent of operations" @@ -300,5 +300,12 @@ "MetricGroup": "Operation_Mix", "MetricName": "branch_indirect_spec_rate", "ScaleUnit": "100%" + }, + { + "MetricName": "sve_all_percentage", + "MetricExpr": "SVE_INST_SPEC / INST_SPEC * 100", + "BriefDescription": "This metric measures scalable vector operatio= ns, including loads and stores, as a percentage of operations speculatively= executed.", + "MetricGroup": "Operation_Mix", + "ScaleUnit": "1percent of operations" } ] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/retired.js= on b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/retired.json index f297b049b62f..337e6a916f2b 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/retired.json +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/retired.json @@ -9,7 +9,7 @@ }, { "ArchStdEvent": "CID_WRITE_RETIRED", - "PublicDescription": "Counts architecturally executed writes to th= e CONTEXTIDR register, which usually contain the kernel PID and can be outp= ut with hardware trace." + "PublicDescription": "Counts architecturally executed writes to th= e CONTEXTIDR_EL1 register, which usually contain the kernel PID and can be = output with hardware trace." }, { "ArchStdEvent": "TTBR_WRITE_RETIRED", @@ -17,7 +17,7 @@ }, { "ArchStdEvent": "BR_RETIRED", - "PublicDescription": "Counts architecturally executed branches, wh= ether the branch is taken or not. Instructions that explicitly write to the= PC are also counted." + "PublicDescription": "Counts architecturally executed branches, wh= ether the branch is taken or not. Instructions that explicitly write to the= PC are also counted. Note that exception generating instructions, exceptio= n return instructions and context synchronization instructions are not coun= ted." }, { "ArchStdEvent": "BR_MIS_PRED_RETIRED", diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/spec_opera= tion.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/spec_operat= ion.json index 1af961f8a6c8..a7ea0d4c4ea4 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/spec_operation.js= on +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/spec_operation.js= on @@ -5,7 +5,7 @@ }, { "ArchStdEvent": "BR_PRED", - "PublicDescription": "Counts branches speculatively executed and w= ere predicted right." + "PublicDescription": "Counts all speculatively executed branches." }, { "ArchStdEvent": "INST_SPEC", @@ -29,7 +29,7 @@ }, { "ArchStdEvent": "LDREX_SPEC", - "PublicDescription": "Counts Load-Exclusive operations that have b= een speculatively executed. Eg: LDREX, LDX" + "PublicDescription": "Counts Load-Exclusive operations that have b= een speculatively executed. For example: LDREX, LDX" }, { "ArchStdEvent": "STREX_PASS_SPEC", @@ -73,15 +73,15 @@ }, { "ArchStdEvent": "BR_IMMED_SPEC", - "PublicDescription": "Counts immediate branch operations which are= speculatively executed." + "PublicDescription": "Counts direct branch operations which are sp= eculatively executed." }, { "ArchStdEvent": "BR_RETURN_SPEC", - "PublicDescription": "Counts procedure return operations (RET) whi= ch are speculatively executed." + "PublicDescription": "Counts procedure return operations (RET, RET= AA and RETAB) which are speculatively executed." }, { "ArchStdEvent": "BR_INDIRECT_SPEC", - "PublicDescription": "Counts indirect branch operations including = procedure returns, which are speculatively executed. This includes operatio= ns that force a software change of the PC, other than exception-generating = operations. Eg: BR Xn, RET" + "PublicDescription": "Counts indirect branch operations including = procedure returns, which are speculatively executed. This includes operatio= ns that force a software change of the PC, other than exception-generating = operations and direct branch instructions. Some examples of the instruction= s counted by this event include BR Xn, RET, etc..." }, { "ArchStdEvent": "ISB_SPEC", @@ -97,11 +97,11 @@ }, { "ArchStdEvent": "RC_LD_SPEC", - "PublicDescription": "Counts any load acquire operations that are = speculatively executed. Eg: LDAR, LDARH, LDARB" + "PublicDescription": "Counts any load acquire operations that are = speculatively executed. For example: LDAR, LDARH, LDARB" }, { "ArchStdEvent": "RC_ST_SPEC", - "PublicDescription": "Counts any store release operations that are= speculatively executed. Eg: STLR, STLRH, STLRB'" + "PublicDescription": "Counts any store release operations that are= speculatively executed. For example: STLR, STLRH, STLRB" }, { "ArchStdEvent": "ASE_INST_SPEC", diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/stall.json= b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/stall.json index bbbebc805034..1fcba19dfb7d 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/stall.json +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/stall.json @@ -1,7 +1,7 @@ [ { "ArchStdEvent": "STALL_FRONTEND", - "PublicDescription": "Counts cycles when frontend could not send a= ny micro-operations to the rename stage because of frontend resource stalls= caused by fetch memory latency or branch prediction flow stalls. All the f= rontend slots were empty during the cycle when this event counts." + "PublicDescription": "Counts cycles when frontend could not send a= ny micro-operations to the rename stage because of frontend resource stalls= caused by fetch memory latency or branch prediction flow stalls. STALL_FRO= NTEND_SLOTS counts SLOTS during the cycle when this event counts." }, { "ArchStdEvent": "STALL_BACKEND", @@ -9,11 +9,11 @@ }, { "ArchStdEvent": "STALL", - "PublicDescription": "Counts cycles when no operations are sent to= the rename unit from the frontend or from the rename unit to the backend f= or any reason (either frontend or backend stall)." + "PublicDescription": "Counts cycles when no operations are sent to= the rename unit from the frontend or from the rename unit to the backend f= or any reason (either frontend or backend stall). This event is the sum of = STALL_FRONTEND and STALL_BACKEND" }, { "ArchStdEvent": "STALL_SLOT_BACKEND", - "PublicDescription": "Counts slots per cycle in which no operation= s are sent from the rename unit to the backend due to backend resource cons= traints." + "PublicDescription": "Counts slots per cycle in which no operation= s are sent from the rename unit to the backend due to backend resource cons= traints. STALL_BACKEND counts during the cycle when STALL_SLOT_BACKEND coun= ts at least 1." }, { "ArchStdEvent": "STALL_SLOT_FRONTEND", @@ -21,7 +21,7 @@ }, { "ArchStdEvent": "STALL_SLOT", - "PublicDescription": "Counts slots per cycle in which no operation= s are sent to the rename unit from the frontend or from the rename unit to = the backend for any reason (either frontend or backend stall)." + "PublicDescription": "Counts slots per cycle in which no operation= s are sent to the rename unit from the frontend or from the rename unit to = the backend for any reason (either frontend or backend stall). STALL_SLOT i= s the sum of STALL_SLOT_FRONTEND and STALL_SLOT_BACKEND." }, { "ArchStdEvent": "STALL_BACKEND_MEM", diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/tlb.json b= /tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/tlb.json index b550af1831f5..5704f1e83af9 100644 --- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/tlb.json +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/tlb.json @@ -25,11 +25,11 @@ }, { "ArchStdEvent": "DTLB_WALK", - "PublicDescription": "Counts data memory translation table walks c= aused by a miss in the L2 TLB driven by a memory access. Note that partial = translations that also cause a table walk are counted. This event does not = count table walks caused by TLB maintenance operations." + "PublicDescription": "Counts number of demand data translation tab= le walks caused by a miss in the L2 TLB and performing at least one memory = access. Translation table walks are counted even if the translation ended u= p taking a translation fault for reasons different than EPD, E0PD and NFD. = Note that partial translations that cause a translation table walk are also= counted. Also note that this event counts walks triggered by software prel= oads, but not walks triggered by hardware prefetchers, and that this event = does not count walks triggered by TLB maintenance operations." }, { "ArchStdEvent": "ITLB_WALK", - "PublicDescription": "Counts instruction memory translation table = walks caused by a miss in the L2 TLB driven by a memory access. Partial tra= nslations that also cause a table walk are counted. This event does not cou= nt table walks caused by TLB maintenance operations." + "PublicDescription": "Counts number of instruction translation tab= le walks caused by a miss in the L2 TLB and performing at least one memory = access. Translation table walks are counted even if the translation ended u= p taking a translation fault for reasons different than EPD, E0PD and NFD. = Note that partial translations that cause a translation table walk are also= counted. Also note that this event does not count walks triggered by TLB m= aintenance operations." }, { "ArchStdEvent": "L1D_TLB_REFILL_RD", --=20 2.34.1