From nobody Tue Feb 10 20:48:42 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DACAB1AA1D6; Wed, 20 Nov 2024 12:44:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732106687; cv=none; b=K/fw5RxxTd102+YrCARwcbQIlTKIOPpojGrIYBR+FL9F/NyQptKsWBIpZqRW3T/EtkUz55r5a0zxvLQSCEDQ4IeKL8dpc8fE5ac9PLvb4SimJBFACEmttuOE9T0MHNuMC2Hd3yjQhFzvS//SV4ZmihLTtbblZaOVFfLh3Cmk/vo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732106687; c=relaxed/simple; bh=RJe8c7MYfmPTa2lD+j4Ucz0NI9LMpabKY+Q8Fh/gjSE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fLgxPC7BelPJOzVLVQvFt6uIsFo6q3LrVtOGUs3oSbQqhJMDEXKLF4smZKSI2l4VnrPs/3wPOhgJSHcuz71vNwr+4gTqe4FUbOnXFPq7RgJ4ADYFGTKG4y9J7+Vp3m4L4om0406fkAGDDNqKbsBwQ0I9TNZYHaknQb4rAiNTWw4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=YHPFF9q/; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="YHPFF9q/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1732106684; bh=RJe8c7MYfmPTa2lD+j4Ucz0NI9LMpabKY+Q8Fh/gjSE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YHPFF9q/C0Pc365bsElM59wmOSMOCI+u6rrS2CvrPnJqTwMcE/IsOJTajV/J2NEtk X3TZcZAw+y4WjzpppU1QdkTPGiE3wjElSwMpZLB5tgOHpzbqegVPiSm3jkPhtG0dk0 p3pLOppRKtrLkoMJ3doa4VjNsUokbbKRyhlJtetWQ7F0aGNGlqx8Gx7wBwFBp/7lTQ A8QfXBnDrIYUE9Ytjv3cElwVmkO0O+nTovjn7qYBHCL3O1L496pcBamzStmjdhmQSx l8L/TM59cvBY9UOW5ewYgxZ/oBSNPuCperPOZCv80zbhLSyUEl8laDCc5VWQ4obNz+ qKWfKZlpGWoJA== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 453A317E3684; Wed, 20 Nov 2024 13:44:43 +0100 (CET) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, ck.hu@mediatek.com, jitao.shi@mediatek.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH v1 4/6] drm/mediatek: mtk_dpi: Move pixel clock setting flow to function Date: Wed, 20 Nov 2024 13:44:18 +0100 Message-ID: <20241120124420.133914-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241120124420.133914-1-angelogioacchino.delregno@collabora.com> References: <20241120124420.133914-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for adding support for the DPI IP found in MT8195 and in MT8188 used for HDMI, move the code flow for calculation and setting of the DPI pixel clock to a separate function called mtk_dpi_set_pixel_clk(). This was done because, on those platforms, the DPI instance that is used for HDMI will get its pixel clock from the HDMI clock, hence it is not necessary, nor desirable, to calculate or set the pixel clock in DPI. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dpi.c | 43 +++++++++++++++++------------- 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 9f59ee679ce1..378b49b6bdfb 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -536,26 +536,17 @@ static unsigned int mtk_dpi_calculate_factor(struct m= tk_dpi *dpi, int mode_clk) return dpi_factor[dpi->conf->num_dpi_factor - 1].factor; } =20 -static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, - struct drm_display_mode *mode) +static void mtk_dpi_set_pixel_clk(struct mtk_dpi *dpi, struct videomode *v= m, int mode_clk) { - struct mtk_dpi_polarities dpi_pol; - struct mtk_dpi_sync_param hsync; - struct mtk_dpi_sync_param vsync_lodd =3D { 0 }; - struct mtk_dpi_sync_param vsync_leven =3D { 0 }; - struct mtk_dpi_sync_param vsync_rodd =3D { 0 }; - struct mtk_dpi_sync_param vsync_reven =3D { 0 }; - struct videomode vm =3D { 0 }; unsigned long pll_rate; unsigned int factor; =20 /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */ factor =3D mtk_dpi_calculate_factor(dpi, mode_clk); - drm_display_mode_to_videomode(mode, &vm); - pll_rate =3D vm.pixelclock * factor; + pll_rate =3D vm->pixelclock * factor; =20 dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n", - pll_rate, vm.pixelclock); + pll_rate, vm->pixelclock); =20 clk_set_rate(dpi->tvd_clk, pll_rate); pll_rate =3D clk_get_rate(dpi->tvd_clk); @@ -565,20 +556,34 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *d= pi, * pixels for each iteration: divide the clock by this number and * adjust the display porches accordingly. */ - vm.pixelclock =3D pll_rate / factor; - vm.pixelclock /=3D dpi->conf->pixels_per_iter; + vm->pixelclock =3D pll_rate / factor; + vm->pixelclock /=3D dpi->conf->pixels_per_iter; =20 if ((dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_LE) || (dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_BE)) - clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2); + clk_set_rate(dpi->pixel_clk, vm->pixelclock * 2); else - clk_set_rate(dpi->pixel_clk, vm.pixelclock); + clk_set_rate(dpi->pixel_clk, vm->pixelclock); =20 - - vm.pixelclock =3D clk_get_rate(dpi->pixel_clk); + vm->pixelclock =3D clk_get_rate(dpi->pixel_clk); =20 dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", - pll_rate, vm.pixelclock); + pll_rate, vm->pixelclock); +} + +static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, + struct drm_display_mode *mode) +{ + struct mtk_dpi_polarities dpi_pol; + struct mtk_dpi_sync_param hsync; + struct mtk_dpi_sync_param vsync_lodd =3D { 0 }; + struct mtk_dpi_sync_param vsync_leven =3D { 0 }; + struct mtk_dpi_sync_param vsync_rodd =3D { 0 }; + struct mtk_dpi_sync_param vsync_reven =3D { 0 }; + struct videomode vm =3D { 0 }; + + drm_display_mode_to_videomode(mode, &vm); + mtk_dpi_set_pixel_clk(dpi, &vm, mode->clock); =20 dpi_pol.ck_pol =3D MTK_DPI_POLARITY_FALLING; dpi_pol.de_pol =3D MTK_DPI_POLARITY_RISING; --=20 2.47.0