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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Nov 2024 12:10:35.3578 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 27b81cc3-f5b1-42c9-d6d2-08dd095c56ce X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.12];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9313 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible string to support OSPI controller device reset IP feature on Versal Gen2 platform. Signed-off-by: Srikanth Boyapally Acked-by: Conor Dooley --- Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Doc= umentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index d48ecd6cd5ad..b6bc71d19286 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -68,6 +68,7 @@ properties: - items: - enum: - amd,pensando-elba-qspi + - amd,versal2-ospi - intel,lgm-qspi - intel,socfpga-qspi - mobileye,eyeq5-ospi --=20 2.34.1 From nobody Thu Nov 21 17:01:30 2024 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2043.outbound.protection.outlook.com [40.107.243.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9ACC919F43A; Wed, 20 Nov 2024 12:10:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Nov 2024 12:10:39.7799 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5bbc9806-1dfd-47a8-5d85-08dd095c5976 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.12];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8892 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove device compatible property check and instead use quirks to program DMA addressing. Signed-off-by: Srikanth Boyapally --- drivers/spi/spi-cadence-quadspi.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 1755ca026f08..fb75400518e0 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -43,6 +43,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <=3D SPI_CS_CNT_MAX); #define CQSPI_SLOW_SRAM BIT(4) #define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) #define CQSPI_RD_NO_IRQ BIT(6) +#define CQSPI_DMA_SET_MASK BIT(7) =20 /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -1881,8 +1882,7 @@ static int cqspi_probe(struct platform_device *pdev) goto probe_reset_failed; } =20 - if (of_device_is_compatible(pdev->dev.of_node, - "xlnx,versal-ospi-1.0")) { + if (ddata->quirks & CQSPI_DMA_SET_MASK) { ret =3D dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); if (ret) goto probe_reset_failed; @@ -2048,7 +2048,8 @@ static const struct cqspi_driver_platdata socfpga_qsp= i =3D { =20 static const struct cqspi_driver_platdata versal_ospi =3D { .hwcaps_mask =3D CQSPI_SUPPORTS_OCTAL, - .quirks =3D CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA, + .quirks =3D CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA + | CQSPI_DMA_SET_MASK, .indirect_read_dma =3D cqspi_versal_indirect_read_dma, .get_dma_status =3D cqspi_get_versal_dma_status, }; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Nov 2024 12:10:42.8892 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 83dd6e20-fa53-4c06-0d3e-08dd095c5b4c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.12];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8705 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for flash device reset via ospi controller, instead of using GPIO, as ospi IP has device reset feature on Versal Gen2 platform. Signed-off-by: Srikanth Boyapally --- drivers/spi/spi-cadence-quadspi.c | 40 ++++++++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index fb75400518e0..82df3d0683d6 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -44,6 +44,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <=3D SPI_CS_CNT_MAX); #define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) #define CQSPI_RD_NO_IRQ BIT(6) #define CQSPI_DMA_SET_MASK BIT(7) +#define CQSPI_SUPPORT_DEVICE_RESET BIT(8) =20 /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -110,7 +111,7 @@ struct cqspi_st { =20 struct cqspi_driver_platdata { u32 hwcaps_mask; - u8 quirks; + u16 quirks; int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata, u_char *rxbuf, loff_t from_addr, size_t n_rx); u32 (*get_dma_status)(struct cqspi_st *cqspi); @@ -145,6 +146,8 @@ struct cqspi_driver_platdata { #define CQSPI_REG_CONFIG_IDLE_LSB 31 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF #define CQSPI_REG_CONFIG_BAUD_MASK 0xF +#define CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK BIT(5) +#define CQSPI_REG_CONFIG_RESET_CFG_FLD_MASK BIT(6) =20 #define CQSPI_REG_RD_INSTR 0x04 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 @@ -831,6 +834,25 @@ static int cqspi_indirect_read_execute(struct cqspi_fl= ash_pdata *f_pdata, return ret; } =20 +static void cqspi_device_reset(struct cqspi_st *cqspi) +{ + u32 reg; + + reg =3D readl(cqspi->iobase + CQSPI_REG_CONFIG); + reg |=3D CQSPI_REG_CONFIG_RESET_CFG_FLD_MASK; + writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); + /* + * NOTE: Delay timing implementation is derived from + * spi_nor_hw_reset() + */ + writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_= REG_CONFIG); + usleep_range(1, 5); + writel(reg | CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_R= EG_CONFIG); + usleep_range(100, 150); + writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, cqspi->iobase + CQSPI_= REG_CONFIG); + usleep_range(1000, 1200); +} + static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable) { void __iomem *reg_base =3D cqspi->iobase; @@ -1912,6 +1934,9 @@ static int cqspi_probe(struct platform_device *pdev) =20 host->num_chipselect =3D cqspi->num_chipselect; =20 + if (ddata->quirks & CQSPI_SUPPORT_DEVICE_RESET) + cqspi_device_reset(cqspi); + if (cqspi->use_direct_mode) { ret =3D cqspi_request_mmap_dma(cqspi); if (ret =3D=3D -EPROBE_DEFER) @@ -2054,6 +2079,15 @@ static const struct cqspi_driver_platdata versal_osp= i =3D { .get_dma_status =3D cqspi_get_versal_dma_status, }; =20 +static const struct cqspi_driver_platdata versal2_ospi =3D { + .hwcaps_mask =3D CQSPI_SUPPORTS_OCTAL, + .quirks =3D CQSPI_DISABLE_DAC_MODE | CQSPI_SUPPORT_EXTERNAL_DMA + | CQSPI_DMA_SET_MASK + | CQSPI_SUPPORT_DEVICE_RESET, + .indirect_read_dma =3D cqspi_versal_indirect_read_dma, + .get_dma_status =3D cqspi_get_versal_dma_status, +}; + static const struct cqspi_driver_platdata jh7110_qspi =3D { .quirks =3D CQSPI_DISABLE_DAC_MODE, .jh7110_clk_init =3D cqspi_jh7110_clk_init, @@ -2106,6 +2140,10 @@ static const struct of_device_id cqspi_dt_ids[] =3D { .compatible =3D "mobileye,eyeq5-ospi", .data =3D &mobileye_eyeq5_ospi, }, + { + .compatible =3D "amd,versal2-ospi", + .data =3D &versal2_ospi, + }, { /* end of table */ } }; =20 --=20 2.34.1