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charset="utf-8" move rochchip inno hdmi connector to a newly created directory named inno-hdmi.c, and rename rockchip/inno_hdmi.c to rockchip/inno_hdmi-rockchip.c This patch refines the Innosilicon HDMI architecture by abstracting the existing connector into a bridge architecture. The drm_bridge_connector_init function is used to create the connector. Signed-off-by: keith zhao --- MAINTAINERS | 2 + drivers/gpu/drm/bridge/Kconfig | 2 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/innosilicon/Kconfig | 6 + drivers/gpu/drm/bridge/innosilicon/Makefile | 2 + .../gpu/drm/bridge/innosilicon/inno-hdmi.c | 376 ++++++ .../gpu/drm/bridge/innosilicon/inno-hdmi.h | 34 + drivers/gpu/drm/rockchip/Kconfig | 1 + drivers/gpu/drm/rockchip/Makefile | 2 +- drivers/gpu/drm/rockchip/inno_hdmi-rockchip.c | 690 +++++++++++ .../{inno_hdmi.h =3D> inno_hdmi-rockchip.h} | 0 drivers/gpu/drm/rockchip/inno_hdmi.c | 1025 ----------------- include/drm/bridge/inno_hdmi.h | 56 + 13 files changed, 1171 insertions(+), 1026 deletions(-) create mode 100644 drivers/gpu/drm/bridge/innosilicon/Kconfig create mode 100644 drivers/gpu/drm/bridge/innosilicon/Makefile create mode 100644 drivers/gpu/drm/bridge/innosilicon/inno-hdmi.c create mode 100644 drivers/gpu/drm/bridge/innosilicon/inno-hdmi.h create mode 100644 drivers/gpu/drm/rockchip/inno_hdmi-rockchip.c rename drivers/gpu/drm/rockchip/{inno_hdmi.h =3D> inno_hdmi-rockchip.h} (1= 00%) delete mode 100644 drivers/gpu/drm/rockchip/inno_hdmi.c create mode 100644 include/drm/bridge/inno_hdmi.h diff --git a/MAINTAINERS b/MAINTAINERS index f787dd625497..7766ee0bdd74 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7439,6 +7439,8 @@ S: Maintained T: git https://gitlab.freedesktop.org/drm/misc/kernel.git F: Documentation/devicetree/bindings/display/bridge/innosilicon,inno-hdmi.= yaml F: Documentation/devicetree/bindings/display/starfive/ +F: drivers/gpu/drm/bridge/innosilicon/ +F: include/drm/bridge/inno_hdmi.h =20 DRM DRIVER FOR SYNAPTICS R63353 PANELS M: Michael Trimarchi diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 683cb33805b2..37be5dd5213f 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -423,6 +423,8 @@ source "drivers/gpu/drm/bridge/cadence/Kconfig" =20 source "drivers/gpu/drm/bridge/imx/Kconfig" =20 +source "drivers/gpu/drm/bridge/innosilicon/Kconfig" + source "drivers/gpu/drm/bridge/synopsys/Kconfig" =20 endmenu diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makef= ile index 3daf803ce80b..866d1e0fd8aa 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -41,4 +41,5 @@ obj-$(CONFIG_DRM_ITE_IT66121) +=3D ite-it66121.o obj-y +=3D analogix/ obj-y +=3D cadence/ obj-y +=3D imx/ +obj-y +=3D innosilicon/ obj-y +=3D synopsys/ diff --git a/drivers/gpu/drm/bridge/innosilicon/Kconfig b/drivers/gpu/drm/b= ridge/innosilicon/Kconfig new file mode 100644 index 000000000000..73dbed3b1c4d --- /dev/null +++ b/drivers/gpu/drm/bridge/innosilicon/Kconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +config DRM_INNO_HDMI + tristate + help + Support the common interface which is part of the INNO + Designware HDMI block. diff --git a/drivers/gpu/drm/bridge/innosilicon/Makefile b/drivers/gpu/drm/= bridge/innosilicon/Makefile new file mode 100644 index 000000000000..3b3a961ab9fb --- /dev/null +++ b/drivers/gpu/drm/bridge/innosilicon/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_DRM_INNO_HDMI) +=3D inno-hdmi.o diff --git a/drivers/gpu/drm/bridge/innosilicon/inno-hdmi.c b/drivers/gpu/d= rm/bridge/innosilicon/inno-hdmi.c new file mode 100644 index 000000000000..c26132b41bdf --- /dev/null +++ b/drivers/gpu/drm/bridge/innosilicon/inno-hdmi.c @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd + * Zheng Yang + * Yakir Yang + * Copyright (C) StarFive Technology Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "inno-hdmi.h" + +u8 hdmi_readb(struct inno_hdmi *hdmi, u16 offset) +{ + return readl_relaxed(hdmi->regs + (offset) * 0x04); +} +EXPORT_SYMBOL_GPL(hdmi_readb); + +void hdmi_writeb(struct inno_hdmi *hdmi, u16 offset, u32 val) +{ + writel_relaxed(val, hdmi->regs + (offset) * 0x04); +} +EXPORT_SYMBOL_GPL(hdmi_writeb); + +void hdmi_modb(struct inno_hdmi *hdmi, u16 offset, u32 msk, u32 val) +{ + u8 temp =3D hdmi_readb(hdmi, offset) & ~msk; + + temp |=3D val & msk; + hdmi_writeb(hdmi, offset, temp); +} +EXPORT_SYMBOL_GPL(hdmi_modb); + +void inno_hdmi_i2c_init(struct inno_hdmi *hdmi, unsigned long long rate) +{ + unsigned long long ddc_bus_freq =3D rate >> 2; + + do_div(ddc_bus_freq, HDMI_SCL_RATE); + + hdmi_writeb(hdmi, DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF); + hdmi_writeb(hdmi, DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF); + + /* Clear the EDID interrupt flag and mute the interrupt */ + hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0); + hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY); +} +EXPORT_SYMBOL_GPL(inno_hdmi_i2c_init); + +static irqreturn_t inno_hdmi_i2c_irq(struct inno_hdmi *hdmi) +{ + struct inno_hdmi_i2c *i2c =3D hdmi->i2c; + u8 stat; + + stat =3D hdmi_readb(hdmi, HDMI_INTERRUPT_STATUS1); + if (!(stat & m_INT_EDID_READY)) + return IRQ_NONE; + + /* Clear HDMI EDID interrupt flag */ + hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY); + + complete(&i2c->cmp); + + return IRQ_HANDLED; +} + +static irqreturn_t inno_hdmi_hardirq(int irq, void *dev_id) +{ + struct inno_hdmi *hdmi =3D dev_id; + irqreturn_t ret =3D IRQ_NONE; + u8 interrupt; + + if (hdmi->i2c) + ret =3D inno_hdmi_i2c_irq(hdmi); + + interrupt =3D hdmi_readb(hdmi, HDMI_STATUS); + if (interrupt & m_INT_HOTPLUG) { + hdmi_modb(hdmi, HDMI_STATUS, m_INT_HOTPLUG, m_INT_HOTPLUG); + ret =3D IRQ_WAKE_THREAD; + } + + return ret; +} + +static irqreturn_t inno_hdmi_irq(int irq, void *dev_id) +{ + struct inno_hdmi *hdmi =3D dev_id; + + drm_helper_hpd_irq_event(hdmi->bridge.dev); + + return IRQ_HANDLED; +} + +static int inno_hdmi_i2c_read(struct inno_hdmi *hdmi, struct i2c_msg *msgs) +{ + int length =3D msgs->len; + u8 *buf =3D msgs->buf; + int ret; + + ret =3D wait_for_completion_timeout(&hdmi->i2c->cmp, HZ / 10); + if (!ret) + return -EAGAIN; + + while (length--) + *buf++ =3D hdmi_readb(hdmi, HDMI_EDID_FIFO_ADDR); + + return 0; +} + +static int inno_hdmi_i2c_write(struct inno_hdmi *hdmi, struct i2c_msg *msg= s) +{ + /* + * The DDC module only support read EDID message, so + * we assume that each word write to this i2c adapter + * should be the offset of EDID word address. + */ + if (msgs->len !=3D 1 || (msgs->addr !=3D DDC_ADDR && msgs->addr !=3D DDC_= SEGMENT_ADDR)) + return -EINVAL; + + reinit_completion(&hdmi->i2c->cmp); + + if (msgs->addr =3D=3D DDC_SEGMENT_ADDR) + hdmi->i2c->segment_addr =3D msgs->buf[0]; + if (msgs->addr =3D=3D DDC_ADDR) + hdmi->i2c->ddc_addr =3D msgs->buf[0]; + + /* Set edid fifo first addr */ + hdmi_writeb(hdmi, HDMI_EDID_FIFO_OFFSET, 0x00); + + /* Set edid word address 0x00/0x80 */ + hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr); + + /* Set edid segment pointer */ + hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr); + + return 0; +} + +static int inno_hdmi_i2c_xfer(struct i2c_adapter *adap, + struct i2c_msg *msgs, int num) +{ + struct inno_hdmi *hdmi =3D i2c_get_adapdata(adap); + struct inno_hdmi_i2c *i2c =3D hdmi->i2c; + int i, ret =3D 0; + + guard(mutex)(&i2c->lock); + /* Clear the EDID interrupt flag and unmute the interrupt */ + hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, m_INT_EDID_READY); + hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY); + + for (i =3D 0; i < num; i++) { + DRM_DEV_DEBUG(hdmi->dev, + "xfer: num: %d/%d, len: %d, flags: %#x\n", + i + 1, num, msgs[i].len, msgs[i].flags); + + if (msgs[i].flags & I2C_M_RD) + ret =3D inno_hdmi_i2c_read(hdmi, &msgs[i]); + else + ret =3D inno_hdmi_i2c_write(hdmi, &msgs[i]); + + if (ret < 0) + break; + } + + if (!ret) + ret =3D num; + + /* Mute HDMI EDID interrupt */ + hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0); + + return ret; +} + +static u32 inno_hdmi_i2c_func(struct i2c_adapter *adapter) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static const struct i2c_algorithm inno_hdmi_algorithm =3D { + .master_xfer =3D inno_hdmi_i2c_xfer, + .functionality =3D inno_hdmi_i2c_func, +}; + +static struct i2c_adapter *inno_hdmi_i2c_adapter(struct inno_hdmi *hdmi) +{ + struct i2c_adapter *adap; + struct inno_hdmi_i2c *i2c; + int ret; + + i2c =3D devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); + if (!i2c) + return ERR_PTR(-ENOMEM); + + mutex_init(&i2c->lock); + init_completion(&i2c->cmp); + + adap =3D &i2c->adap; + adap->owner =3D THIS_MODULE; + adap->dev.parent =3D hdmi->dev; + adap->dev.of_node =3D hdmi->dev->of_node; + adap->algo =3D &inno_hdmi_algorithm; + strscpy(adap->name, "Inno HDMI", sizeof(adap->name)); + i2c_set_adapdata(adap, hdmi); + + ret =3D devm_i2c_add_adapter(hdmi->dev, adap); + if (ret) { + dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); + return ERR_PTR(ret); + } + + hdmi->i2c =3D i2c; + + DRM_DEV_DEBUG(hdmi->dev, "registered %s I2C bus driver\n", adap->name); + + return adap; +} + +static int inno_bridge_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct inno_hdmi *hdmi =3D bridge->driver_private; + + if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) + return drm_bridge_attach(bridge->encoder, hdmi->next_bridge, + bridge, flags); + + return 0; +} + +static enum drm_connector_status +inno_hdmi_bridge_detect(struct drm_bridge *bridge) +{ + struct inno_hdmi *hdmi =3D bridge->driver_private; + + return (hdmi_readb(hdmi, HDMI_STATUS) & m_HOTPLUG) ? + connector_status_connected : connector_status_disconnected; +} + +static const struct drm_edid *inno_bridge_edid_read(struct drm_bridge *bri= dge, + struct drm_connector *connector) +{ + struct inno_hdmi *hdmi =3D bridge->driver_private; + + return drm_edid_read_ddc(connector, hdmi->bridge.ddc); +} + +static enum drm_mode_status +inno_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + struct inno_hdmi *hdmi =3D bridge->driver_private; + + enum drm_mode_status mode_status =3D MODE_OK; + + if (hdmi->plat_data->mode_valid) + mode_status =3D hdmi->plat_data->mode_valid(hdmi, mode); + + return mode_status; +} + +static int inno_hdmi_clear_infoframe(struct drm_bridge *bridge, + enum hdmi_infoframe_type type) +{ + struct inno_hdmi *hdmi =3D bridge->driver_private; + int ret =3D 0; + + if (hdmi->plat_data->hdmi_clear_infoframe) + ret =3D hdmi->plat_data->hdmi_clear_infoframe(hdmi, type); + + return ret; +} + +static int inno_write_infoframe(struct drm_bridge *bridge, + enum hdmi_infoframe_type type, + const u8 *buffer, size_t len) +{ + struct inno_hdmi *hdmi =3D bridge->driver_private; + int ret =3D 0; + + if (hdmi->plat_data->hdmi_write_infoframe) + ret =3D hdmi->plat_data->hdmi_write_infoframe(hdmi, type, buffer, len); + + return ret; +} + +static int inno_bridge_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + return drm_atomic_helper_connector_hdmi_check(conn_state->connector, + bridge_state->base.state); +} + +static const struct drm_bridge_funcs inno_bridge_funcs =3D { + .atomic_check =3D inno_bridge_atomic_check, + .atomic_duplicate_state =3D drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_bridge_destroy_state, + .atomic_reset =3D drm_atomic_helper_bridge_reset, + .attach =3D inno_bridge_attach, + .detect =3D inno_hdmi_bridge_detect, + .edid_read =3D inno_bridge_edid_read, + .mode_valid =3D inno_bridge_mode_valid, + .hdmi_clear_infoframe =3D inno_hdmi_clear_infoframe, + .hdmi_write_infoframe =3D inno_write_infoframe, +}; + +int inno_hdmi_bind(struct drm_device *drm, struct inno_hdmi *hdmi, struct = drm_encoder *encoder) +{ + int ret, irq; + struct platform_device *pdev =3D to_platform_device(hdmi->dev); + + irq =3D platform_get_irq(pdev, 0); + if (irq < 0) { + ret =3D irq; + return ret; + } + + hdmi->ddc =3D inno_hdmi_i2c_adapter(hdmi); + if (IS_ERR(hdmi->ddc)) { + ret =3D PTR_ERR(hdmi->ddc); + hdmi->ddc =3D NULL; + return ret; + } + + hdmi->next_bridge =3D devm_drm_of_get_bridge(hdmi->dev, hdmi->dev->of_nod= e, 1, 0); + if (IS_ERR(hdmi->next_bridge)) + return dev_err_probe(hdmi->dev, PTR_ERR(hdmi->next_bridge), + "failed to acquire drm_bridge\n"); + + hdmi->bridge.driver_private =3D hdmi; + hdmi->bridge.funcs =3D &inno_bridge_funcs; + hdmi->bridge.ddc =3D hdmi->ddc; +#ifdef CONFIG_OF + hdmi->bridge.of_node =3D hdmi->dev->of_node; +#endif + hdmi->bridge.ops =3D DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | + DRM_BRIDGE_OP_HPD | DRM_BRIDGE_OP_HDMI; + hdmi->bridge.type =3D DRM_MODE_CONNECTOR_HDMIA; + + hdmi->bridge.vendor =3D hdmi->plat_data->vendor; + hdmi->bridge.product =3D hdmi->plat_data->product; + + devm_drm_bridge_add(hdmi->dev, &hdmi->bridge); + + /* Unmute hotplug interrupt */ + hdmi_modb(hdmi, HDMI_STATUS, m_MASK_INT_HOTPLUG, v_MASK_INT_HOTPLUG(1)); + + ret =3D devm_request_threaded_irq(hdmi->dev, irq, inno_hdmi_hardirq, + inno_hdmi_irq, IRQF_SHARED, + dev_name(hdmi->dev), hdmi); + return ret; +} +EXPORT_SYMBOL_GPL(inno_hdmi_bind); + +MODULE_AUTHOR("Keith Zhao "); +MODULE_DESCRIPTION("INNO HDMI transmitter driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:inno-hdmi"); diff --git a/drivers/gpu/drm/bridge/innosilicon/inno-hdmi.h b/drivers/gpu/d= rm/bridge/innosilicon/inno-hdmi.h new file mode 100644 index 000000000000..75e3e002947f --- /dev/null +++ b/drivers/gpu/drm/bridge/innosilicon/inno-hdmi.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd + * Zheng Yang + * Yakir Yang + * Copyright (C) StarFive Technology Co., Ltd. + */ + +#ifndef __INNO_H__ +#define __INNO_H__ + +#define DDC_SEGMENT_ADDR 0x30 + +#define HDMI_SCL_RATE (100 * 1000) +#define DDC_BUS_FREQ_L 0x4b +#define DDC_BUS_FREQ_H 0x4c + +#define HDMI_EDID_SEGMENT_POINTER 0x4d +#define HDMI_EDID_WORD_ADDR 0x4e +#define HDMI_EDID_FIFO_OFFSET 0x4f +#define HDMI_EDID_FIFO_ADDR 0x50 + +#define HDMI_INTERRUPT_MASK1 0xc0 +#define HDMI_INTERRUPT_STATUS1 0xc1 +#define m_INT_ACTIVE_VSYNC (1 << 5) +#define m_INT_EDID_READY (1 << 2) + +#define HDMI_STATUS 0xc8 +#define m_HOTPLUG (1 << 7) +#define m_MASK_INT_HOTPLUG (1 << 5) +#define m_INT_HOTPLUG (1 << 1) +#define v_MASK_INT_HOTPLUG(n) (((n) & 0x1) << 5) + +#endif /* __INNO_H__ */ diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kc= onfig index 258dd38e1a8e..e728b5ee2219 100644 --- a/drivers/gpu/drm/rockchip/Kconfig +++ b/drivers/gpu/drm/rockchip/Kconfig @@ -78,6 +78,7 @@ config ROCKCHIP_INNO_HDMI select DRM_DISPLAY_HDMI_HELPER select DRM_DISPLAY_HDMI_STATE_HELPER select DRM_DISPLAY_HELPER + select DRM_INNO_HDMI help This selects support for Rockchip SoC specific extensions for the Innosilicon HDMI driver. If you want to enable diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/M= akefile index 3ff7b21c0414..4b2d0cba8db3 100644 --- a/drivers/gpu/drm/rockchip/Makefile +++ b/drivers/gpu/drm/rockchip/Makefile @@ -12,7 +12,7 @@ rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) +=3D analogix_= dp-rockchip.o rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) +=3D cdn-dp-core.o cdn-dp-reg.o rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) +=3D dw_hdmi-rockchip.o rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) +=3D dw-mipi-dsi-rockchip.o -rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) +=3D inno_hdmi.o +rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) +=3D inno_hdmi-rockchip.o rockchipdrm-$(CONFIG_ROCKCHIP_LVDS) +=3D rockchip_lvds.o rockchipdrm-$(CONFIG_ROCKCHIP_RGB) +=3D rockchip_rgb.o rockchipdrm-$(CONFIG_ROCKCHIP_RK3066_HDMI) +=3D rk3066_hdmi.o diff --git a/drivers/gpu/drm/rockchip/inno_hdmi-rockchip.c b/drivers/gpu/dr= m/rockchip/inno_hdmi-rockchip.c new file mode 100644 index 000000000000..2bde9d539e9e --- /dev/null +++ b/drivers/gpu/drm/rockchip/inno_hdmi-rockchip.c @@ -0,0 +1,690 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd + * Zheng Yang + * Yakir Yang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "rockchip_drm_drv.h" + +#include "inno_hdmi-rockchip.h" + +#define INNO_HDMI_MIN_TMDS_CLOCK 25000000U + +struct inno_hdmi_rockchip_phy_config { + unsigned long pixelclock; + u8 pre_emphasis; + u8 voltage_level_control; +}; + +struct inno_hdmi_rockchip_variant { + struct inno_hdmi_rockchip_phy_config *phy_configs; + struct inno_hdmi_rockchip_phy_config *default_phy_config; + const struct inno_hdmi_plat_data *plat_data; +}; + +struct rockchip_inno_hdmi { + struct device *dev; + + struct clk *pclk; + struct clk *refclk; + + struct inno_hdmi inno_hdmi; + struct drm_connector *connector; + struct rockchip_encoder encoder; + + const struct inno_hdmi_rockchip_variant *variant; + unsigned int colorimetry; +}; + +static struct rockchip_inno_hdmi *encoder_to_rk_hdmi(struct drm_encoder *e= ncoder) +{ + struct rockchip_encoder *rkencoder =3D to_rockchip_encoder(encoder); + + return container_of(rkencoder, struct rockchip_inno_hdmi, encoder); +} + +static struct rockchip_inno_hdmi *inno_hdmi_to_rk_hdmi(struct inno_hdmi *i= nno_hdmi) +{ + return container_of(inno_hdmi, struct rockchip_inno_hdmi, inno_hdmi); +} + +enum { + CSC_RGB_0_255_TO_ITU601_16_235_8BIT, + CSC_RGB_0_255_TO_ITU709_16_235_8BIT, + CSC_RGB_0_255_TO_RGB_16_235_8BIT, +}; + +static const char coeff_csc[][24] =3D { + /* + * RGB2YUV:601 SD mode: + * Cb =3D -0.291G - 0.148R + 0.439B + 128 + * Y =3D 0.504G + 0.257R + 0.098B + 16 + * Cr =3D -0.368G + 0.439R - 0.071B + 128 + */ + { + 0x11, 0x5f, 0x01, 0x82, 0x10, 0x23, 0x00, 0x80, + 0x02, 0x1c, 0x00, 0xa1, 0x00, 0x36, 0x00, 0x1e, + 0x11, 0x29, 0x10, 0x59, 0x01, 0x82, 0x00, 0x80 + }, + /* + * RGB2YUV:709 HD mode: + * Cb =3D - 0.338G - 0.101R + 0.439B + 128 + * Y =3D 0.614G + 0.183R + 0.062B + 16 + * Cr =3D - 0.399G + 0.439R - 0.040B + 128 + */ + { + 0x11, 0x98, 0x01, 0xc1, 0x10, 0x28, 0x00, 0x80, + 0x02, 0x74, 0x00, 0xbb, 0x00, 0x3f, 0x00, 0x10, + 0x11, 0x5a, 0x10, 0x67, 0x01, 0xc1, 0x00, 0x80 + }, + /* + * RGB[0:255]2RGB[16:235]: + * R' =3D R x (235-16)/255 + 16; + * G' =3D G x (235-16)/255 + 16; + * B' =3D B x (235-16)/255 + 16; + */ + { + 0x00, 0x00, 0x03, 0x6F, 0x00, 0x00, 0x00, 0x10, + 0x03, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, + 0x00, 0x00, 0x00, 0x00, 0x03, 0x6F, 0x00, 0x10 + }, +}; + +static struct inno_hdmi_rockchip_phy_config rk3036_hdmi_phy_configs[] =3D { + { 74250000, 0x3f, 0xbb }, + { 165000000, 0x6f, 0xbb }, + { ~0UL, 0x00, 0x00 } +}; + +static struct inno_hdmi_rockchip_phy_config rk3128_hdmi_phy_configs[] =3D { + { 74250000, 0x3f, 0xaa }, + { 165000000, 0x5f, 0xaa }, + { ~0UL, 0x00, 0x00 } +}; + +static int inno_hdmi_rockchip_find_phy_config(struct rockchip_inno_hdmi *r= k_hdmi, + unsigned long pixelclk) +{ + const struct inno_hdmi_rockchip_phy_config *phy_configs =3D + rk_hdmi->variant->phy_configs; + int i; + + for (i =3D 0; phy_configs[i].pixelclock !=3D ~0UL; i++) { + if (pixelclk <=3D phy_configs[i].pixelclock) + return i; + } + + DRM_DEV_DEBUG(rk_hdmi->dev, "No phy configuration for pixelclock %lu\n", + pixelclk); + + return -EINVAL; +} + +static void inno_hdmi_rockchip_sys_power(struct inno_hdmi *hdmi, bool enab= le) +{ + if (enable) + hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_ON); + else + hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_OFF); +} + +static void inno_hdmi_rockchip_standby(struct inno_hdmi *hdmi) +{ + inno_hdmi_rockchip_sys_power(hdmi, false); + + hdmi_writeb(hdmi, HDMI_PHY_DRIVER, 0x00); + hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, 0x00); + hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x00); + hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15); +}; + +static void inno_hdmi_rockchip_power_up(struct rockchip_inno_hdmi *rk_hdmi, + unsigned long mpixelclock) +{ + struct inno_hdmi_rockchip_phy_config *phy_config; + struct inno_hdmi *hdmi =3D &rk_hdmi->inno_hdmi; + int ret =3D inno_hdmi_rockchip_find_phy_config(rk_hdmi, mpixelclock); + + if (ret < 0) { + phy_config =3D rk_hdmi->variant->default_phy_config; + DRM_DEV_ERROR(rk_hdmi->dev, + "Using default phy configuration for TMDS rate %lu", + mpixelclock); + } else { + phy_config =3D &rk_hdmi->variant->phy_configs[ret]; + } + + inno_hdmi_rockchip_sys_power(hdmi, false); + + hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, phy_config->pre_emphasis); + hdmi_writeb(hdmi, HDMI_PHY_DRIVER, phy_config->voltage_level_control); + hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15); + hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x14); + hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x10); + hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x0f); + hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x00); + hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x01); + + inno_hdmi_rockchip_sys_power(hdmi, true); +}; + +static void inno_hdmi_rockchip_reset(struct inno_hdmi *hdmi) +{ + u32 val; + u32 msk; + + hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_DIGITAL, v_NOT_RST_DIGITAL); + udelay(100); + + hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_ANALOG, v_NOT_RST_ANALOG); + udelay(100); + + msk =3D m_REG_CLK_INV | m_REG_CLK_SOURCE | m_POWER | m_INT_POL; + val =3D v_REG_CLK_INV | v_REG_CLK_SOURCE_SYS | v_PWR_ON | v_INT_POL_HIGH; + hdmi_modb(hdmi, HDMI_SYS_CTRL, msk, val); + + inno_hdmi_rockchip_standby(hdmi); +} + +static int inno_hdmi_rockchip_disable_frame(struct inno_hdmi *hdmi, + enum hdmi_infoframe_type type) +{ + if (type !=3D HDMI_INFOFRAME_TYPE_AVI) { + drm_err(hdmi->bridge.dev, + "Unsupported infoframe type: %u\n", type); + return 0; + } + + hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_BUF_INDEX, INFOFRAME_AVI); + + return 0; +} + +static int inno_hdmi_rockchip_upload_frame(struct inno_hdmi *hdmi, + enum hdmi_infoframe_type type, + const u8 *buffer, size_t len) +{ + ssize_t i; + + if (type !=3D HDMI_INFOFRAME_TYPE_AVI) { + drm_err(hdmi->bridge.dev, + "Unsupported infoframe type: %u\n", type); + return 0; + } + + inno_hdmi_rockchip_disable_frame(hdmi, type); + + for (i =3D 0; i < len; i++) + hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_ADDR + i, buffer[i]); + + return 0; +} + +static int inno_hdmi_rockchip_config_video_csc(struct rockchip_inno_hdmi *= rk_hdmi) +{ + struct drm_connector *connector =3D rk_hdmi->connector; + struct drm_connector_state *conn_state =3D connector->state; + struct inno_hdmi *hdmi =3D &rk_hdmi->inno_hdmi; + + int c0_c2_change =3D 0; + int csc_enable =3D 0; + int csc_mode =3D 0; + int auto_csc =3D 0; + int value; + int i; + + /* Input video mode is SDR RGB24bit, data enable signal from external */ + hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL1, v_DE_EXTERNAL | + v_VIDEO_INPUT_FORMAT(VIDEO_INPUT_SDR_RGB444)); + + /* Input color hardcode to RGB, and output color hardcode to RGB888 */ + value =3D v_VIDEO_INPUT_BITS(VIDEO_INPUT_8BITS) | + v_VIDEO_OUTPUT_COLOR(0) | + v_VIDEO_INPUT_CSP(0); + hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL2, value); + + if (conn_state->hdmi.output_format =3D=3D HDMI_COLORSPACE_RGB) { + if (conn_state->hdmi.is_limited_range) { + csc_mode =3D CSC_RGB_0_255_TO_RGB_16_235_8BIT; + auto_csc =3D AUTO_CSC_DISABLE; + c0_c2_change =3D C0_C2_CHANGE_DISABLE; + csc_enable =3D v_CSC_ENABLE; + + } else { + value =3D v_SOF_DISABLE | v_COLOR_DEPTH_NOT_INDICATED(1); + hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value); + + hdmi_modb(hdmi, HDMI_VIDEO_CONTRL, + m_VIDEO_AUTO_CSC | m_VIDEO_C0_C2_SWAP, + v_VIDEO_AUTO_CSC(AUTO_CSC_DISABLE) | + v_VIDEO_C0_C2_SWAP(C0_C2_CHANGE_DISABLE)); + return 0; + } + } else { + if (rk_hdmi->colorimetry =3D=3D HDMI_COLORIMETRY_ITU_601) { + if (conn_state->hdmi.output_format =3D=3D HDMI_COLORSPACE_YUV444) { + csc_mode =3D CSC_RGB_0_255_TO_ITU601_16_235_8BIT; + auto_csc =3D AUTO_CSC_DISABLE; + c0_c2_change =3D C0_C2_CHANGE_DISABLE; + csc_enable =3D v_CSC_ENABLE; + } + } else { + if (conn_state->hdmi.output_format =3D=3D HDMI_COLORSPACE_YUV444) { + csc_mode =3D CSC_RGB_0_255_TO_ITU709_16_235_8BIT; + auto_csc =3D AUTO_CSC_DISABLE; + c0_c2_change =3D C0_C2_CHANGE_DISABLE; + csc_enable =3D v_CSC_ENABLE; + } + } + } + + for (i =3D 0; i < 24; i++) + hdmi_writeb(hdmi, HDMI_VIDEO_CSC_COEF + i, + coeff_csc[csc_mode][i]); + + value =3D v_SOF_DISABLE | csc_enable | v_COLOR_DEPTH_NOT_INDICATED(1); + hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value); + hdmi_modb(hdmi, HDMI_VIDEO_CONTRL, m_VIDEO_AUTO_CSC | + m_VIDEO_C0_C2_SWAP, v_VIDEO_AUTO_CSC(auto_csc) | + v_VIDEO_C0_C2_SWAP(c0_c2_change)); + + return 0; +} + +static int inno_hdmi_rockchip_config_video_timing(struct inno_hdmi *hdmi, + struct drm_display_mode *mode) +{ + int value; + + /* Set detail external video timing polarity and interlace mode */ + value =3D v_EXTERANL_VIDEO(1); + value |=3D mode->flags & DRM_MODE_FLAG_PHSYNC ? + v_HSYNC_POLARITY(1) : v_HSYNC_POLARITY(0); + value |=3D mode->flags & DRM_MODE_FLAG_PVSYNC ? + v_VSYNC_POLARITY(1) : v_VSYNC_POLARITY(0); + value |=3D mode->flags & DRM_MODE_FLAG_INTERLACE ? + v_INETLACE(1) : v_INETLACE(0); + hdmi_writeb(hdmi, HDMI_VIDEO_TIMING_CTL, value); + + /* Set detail external video timing */ + value =3D mode->htotal; + hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_L, value & 0xFF); + hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_H, (value >> 8) & 0xFF); + + value =3D mode->htotal - mode->hdisplay; + hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_L, value & 0xFF); + hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_H, (value >> 8) & 0xFF); + + value =3D mode->htotal - mode->hsync_start; + hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_L, value & 0xFF); + hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_H, (value >> 8) & 0xFF); + + value =3D mode->hsync_end - mode->hsync_start; + hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_L, value & 0xFF); + hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_H, (value >> 8) & 0xFF); + + value =3D mode->vtotal; + hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_L, value & 0xFF); + hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_H, (value >> 8) & 0xFF); + + value =3D mode->vtotal - mode->vdisplay; + hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VBLANK, value & 0xFF); + + value =3D mode->vtotal - mode->vsync_start; + hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDELAY, value & 0xFF); + + value =3D mode->vsync_end - mode->vsync_start; + hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDURATION, value & 0xFF); + + hdmi_writeb(hdmi, HDMI_PHY_PRE_DIV_RATIO, 0x1e); + hdmi_writeb(hdmi, HDMI_PHY_FEEDBACK_DIV_RATIO_LOW, 0x2c); + hdmi_writeb(hdmi, HDMI_PHY_FEEDBACK_DIV_RATIO_HIGH, 0x01); + + return 0; +} + +static int inno_hdmi_rockchip_setup(struct rockchip_inno_hdmi *rk_hdmi, + struct drm_atomic_state *state) +{ + struct inno_hdmi *hdmi =3D &rk_hdmi->inno_hdmi; + struct drm_connector *connector =3D rk_hdmi->connector; + struct drm_display_info *display =3D &connector->display_info; + struct drm_connector_state *new_conn_state; + struct drm_crtc_state *new_crtc_state; + + new_conn_state =3D drm_atomic_get_new_connector_state(state, connector); + if (WARN_ON(!new_conn_state)) + return -EINVAL; + + new_crtc_state =3D drm_atomic_get_new_crtc_state(state, new_conn_state->c= rtc); + if (WARN_ON(!new_crtc_state)) + return -EINVAL; + + /* Mute video and audio output */ + hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK, + v_AUDIO_MUTE(1) | v_VIDEO_MUTE(1)); + + /* Set HDMI Mode */ + hdmi_writeb(hdmi, HDMI_HDCP_CTRL, + v_HDMI_DVI(display->is_hdmi)); + + inno_hdmi_rockchip_config_video_timing(hdmi, &new_crtc_state->adjusted_mo= de); + + inno_hdmi_rockchip_config_video_csc(rk_hdmi); + + drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); + + /* + * When IP controller have configured to an accurate video + * timing, then the TMDS clock source would be switched to + * DCLK_LCDC, so we need to init the TMDS rate to mode pixel + * clock rate, and reconfigure the DDC clock. + */ + inno_hdmi_i2c_init(hdmi, new_conn_state->hdmi.tmds_char_rate); + + /* Unmute video and audio output */ + hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK, + v_AUDIO_MUTE(0) | v_VIDEO_MUTE(0)); + + inno_hdmi_rockchip_power_up(rk_hdmi, new_conn_state->hdmi.tmds_char_rate); + + return 0; +} + +static enum drm_mode_status inno_hdmi_rockchip_mode_valid(struct inno_hdmi= *hdmi, + const struct drm_display_mode *mode) +{ + unsigned long mpixelclk, max_tolerance; + long rounded_refclk; + struct rockchip_inno_hdmi *rk_hdmi =3D inno_hdmi_to_rk_hdmi(hdmi); + + /* No support for double-clock modes */ + if (mode->flags & DRM_MODE_FLAG_DBLCLK) + return MODE_BAD; + + mpixelclk =3D mode->clock * 1000; + + if (mpixelclk < INNO_HDMI_MIN_TMDS_CLOCK) + return MODE_CLOCK_LOW; + + if (inno_hdmi_rockchip_find_phy_config(rk_hdmi, mpixelclk) < 0) + return MODE_CLOCK_HIGH; + + if (rk_hdmi->refclk) { + rounded_refclk =3D clk_round_rate(rk_hdmi->refclk, mpixelclk); + if (rounded_refclk < 0) + return MODE_BAD; + + /* Vesa DMT standard mentions +/- 0.5% max tolerance */ + max_tolerance =3D mpixelclk / 200; + if (abs_diff((unsigned long)rounded_refclk, mpixelclk) > max_tolerance) + return MODE_NOCLOCK; + } + + return MODE_OK; +} + +static void inno_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder, + struct drm_atomic_state *state) +{ + struct rockchip_inno_hdmi *rk_hdmi =3D encoder_to_rk_hdmi(encoder); + + inno_hdmi_rockchip_setup(rk_hdmi, state); +} + +static void inno_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder, + struct drm_atomic_state *state) +{ + struct rockchip_inno_hdmi *rk_hdmi =3D encoder_to_rk_hdmi(encoder); + + inno_hdmi_rockchip_standby(&rk_hdmi->inno_hdmi); +} + +static int +inno_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct rockchip_crtc_state *s =3D to_rockchip_crtc_state(crtc_state); + struct drm_display_mode *mode =3D &crtc_state->adjusted_mode; + u8 vic =3D drm_match_cea_mode(mode); + struct rockchip_inno_hdmi *rk_hdmi =3D encoder_to_rk_hdmi(encoder); + + s->output_mode =3D ROCKCHIP_OUT_MODE_P888; + s->output_type =3D DRM_MODE_CONNECTOR_HDMIA; + + if (vic =3D=3D 6 || vic =3D=3D 7 || + vic =3D=3D 21 || vic =3D=3D 22 || + vic =3D=3D 2 || vic =3D=3D 3 || + vic =3D=3D 17 || vic =3D=3D 18) + rk_hdmi->colorimetry =3D HDMI_COLORIMETRY_ITU_601; + else + rk_hdmi->colorimetry =3D HDMI_COLORIMETRY_ITU_709; + + return 0; +} + +static const struct drm_encoder_helper_funcs inno_hdmi_rockchip_encoder_he= lper_funcs =3D { + .atomic_check =3D inno_hdmi_rockchip_encoder_atomic_check, + .atomic_enable =3D inno_hdmi_rockchip_encoder_enable, + .atomic_disable =3D inno_hdmi_rockchip_encoder_disable, +}; + +static int inno_hdmi_rockchip_register(struct drm_device *drm, struct inno= _hdmi *hdmi) +{ + struct rockchip_inno_hdmi *rk_hdmi =3D inno_hdmi_to_rk_hdmi(hdmi); + struct drm_encoder *encoder =3D &rk_hdmi->encoder.encoder; + struct device *dev =3D hdmi->dev; + int ret; + + encoder->possible_crtcs =3D drm_of_find_possible_crtcs(drm, dev->of_node); + + /* + * If we failed to find the CRTC(s) which this encoder is + * supposed to be connected to, it's because the CRTC has + * not been registered yet. Defer probing, and hope that + * the required CRTC is added later. + */ + if (encoder->possible_crtcs =3D=3D 0) + return -EPROBE_DEFER; + + drm_encoder_helper_add(encoder, &inno_hdmi_rockchip_encoder_helper_funcs); + drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); + + ret =3D inno_hdmi_bind(drm, hdmi, encoder); + if (ret) + goto err_cleanup_encoder; + + ret =3D drm_bridge_attach(encoder, &hdmi->bridge, NULL, DRM_BRIDGE_ATTACH= _NO_CONNECTOR); + if (ret) + goto err_cleanup_encoder; + + rk_hdmi->connector =3D drm_bridge_connector_init(drm, encoder); + if (IS_ERR(rk_hdmi->connector)) { + dev_err(dev, "Unable to create bridge connector\n"); + ret =3D PTR_ERR(rk_hdmi->connector); + return ret; + } + + drm_connector_attach_encoder(rk_hdmi->connector, encoder); + + return 0; + +err_cleanup_encoder: + drm_encoder_cleanup(encoder); + return ret; +} + +static int inno_hdmi_rockchip_bind(struct device *dev, struct device *mast= er, void *data) +{ + struct platform_device *pdev =3D to_platform_device(dev); + struct drm_device *drm =3D data; + struct rockchip_inno_hdmi *rk_hdmi; + struct inno_hdmi *hdmi; + const struct inno_hdmi_rockchip_variant *variant; + int ret; + + rk_hdmi =3D devm_kzalloc(dev, sizeof(*rk_hdmi), GFP_KERNEL); + if (!rk_hdmi) + return -ENOMEM; + + rk_hdmi->dev =3D dev; + hdmi =3D &rk_hdmi->inno_hdmi; + hdmi->dev =3D dev; + + variant =3D of_device_get_match_data(hdmi->dev); + if (!variant) + return -EINVAL; + + rk_hdmi->variant =3D variant; + hdmi->plat_data =3D variant->plat_data; + + hdmi->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(hdmi->regs)) + return PTR_ERR(hdmi->regs); + + rk_hdmi->pclk =3D devm_clk_get(hdmi->dev, "pclk"); + if (IS_ERR(rk_hdmi->pclk)) { + DRM_DEV_ERROR(rk_hdmi->dev, "Unable to get HDMI pclk clk\n"); + return PTR_ERR(rk_hdmi->pclk); + } + + ret =3D clk_prepare_enable(rk_hdmi->pclk); + if (ret) { + DRM_DEV_ERROR(rk_hdmi->dev, + "Cannot enable HDMI pclk clock: %d\n", ret); + return ret; + } + + rk_hdmi->refclk =3D devm_clk_get_optional(rk_hdmi->dev, "ref"); + if (IS_ERR(rk_hdmi->refclk)) { + DRM_DEV_ERROR(rk_hdmi->dev, "Unable to get HDMI reference clock\n"); + ret =3D PTR_ERR(rk_hdmi->refclk); + goto err_disable_pclk; + } + + ret =3D clk_prepare_enable(rk_hdmi->refclk); + if (ret) { + DRM_DEV_ERROR(rk_hdmi->dev, + "Cannot enable HDMI reference clock: %d\n", ret); + goto err_disable_pclk; + } + + inno_hdmi_rockchip_reset(hdmi); + + /* + * When the controller isn't configured to an accurate + * video timing and there is no reference clock available, + * then the TMDS clock source would be switched to PCLK_HDMI, + * so we need to init the TMDS rate to PCLK rate, and + * reconfigure the DDC clock. + */ + if (rk_hdmi->refclk) + inno_hdmi_i2c_init(hdmi, clk_get_rate(rk_hdmi->refclk)); + else + inno_hdmi_i2c_init(hdmi, clk_get_rate(rk_hdmi->pclk)); + + ret =3D inno_hdmi_rockchip_register(drm, hdmi); + if (ret) + goto err_disable_clk; + + dev_set_drvdata(dev, hdmi); + + return 0; + +err_disable_clk: + clk_disable_unprepare(rk_hdmi->refclk); +err_disable_pclk: + clk_disable_unprepare(rk_hdmi->pclk); + return ret; +} + +static void inno_hdmi_rockchip_unbind(struct device *dev, struct device *m= aster, + void *data) +{ + struct inno_hdmi *hdmi =3D dev_get_drvdata(dev); + struct rockchip_inno_hdmi *rk_hdmi =3D inno_hdmi_to_rk_hdmi(hdmi); + + rk_hdmi->encoder.encoder.funcs->destroy(&rk_hdmi->encoder.encoder); + + clk_disable_unprepare(rk_hdmi->refclk); + clk_disable_unprepare(rk_hdmi->pclk); +} + +static const struct component_ops inno_hdmi_rockchip_ops =3D { + .bind =3D inno_hdmi_rockchip_bind, + .unbind =3D inno_hdmi_rockchip_unbind, +}; + +static int inno_hdmi_rockchip_probe(struct platform_device *pdev) +{ + return component_add(&pdev->dev, &inno_hdmi_rockchip_ops); +} + +static void inno_hdmi_rockchip_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &inno_hdmi_rockchip_ops); +} + +const struct inno_hdmi_plat_data data_inno =3D { + .vendor =3D "Rockchip", + .product =3D "Inno HDMI", + .mode_valid =3D inno_hdmi_rockchip_mode_valid, + .hdmi_clear_infoframe =3D inno_hdmi_rockchip_disable_frame, + .hdmi_write_infoframe =3D inno_hdmi_rockchip_upload_frame, +}; + +static const struct inno_hdmi_rockchip_variant rk3036_inno_hdmi_variant = =3D { + .phy_configs =3D rk3036_hdmi_phy_configs, + .default_phy_config =3D &rk3036_hdmi_phy_configs[1], + .plat_data =3D &data_inno, +}; + +static const struct inno_hdmi_rockchip_variant rk3128_inno_hdmi_variant = =3D { + .phy_configs =3D rk3128_hdmi_phy_configs, + .default_phy_config =3D &rk3128_hdmi_phy_configs[1], + .plat_data =3D &data_inno, +}; + +static const struct of_device_id inno_hdmi_dt_ids[] =3D { + { .compatible =3D "rockchip,rk3036-inno-hdmi", + .data =3D &rk3036_inno_hdmi_variant, + }, + { .compatible =3D "rockchip,rk3128-inno-hdmi", + .data =3D &rk3128_inno_hdmi_variant, + }, + {}, +}; +MODULE_DEVICE_TABLE(of, inno_hdmi_dt_ids); + +struct platform_driver inno_hdmi_driver =3D { + .probe =3D inno_hdmi_rockchip_probe, + .remove_new =3D inno_hdmi_rockchip_remove, + .driver =3D { + .name =3D "innohdmi-rockchip", + .of_match_table =3D inno_hdmi_dt_ids, + }, +}; diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.h b/drivers/gpu/drm/rockchi= p/inno_hdmi-rockchip.h similarity index 100% rename from drivers/gpu/drm/rockchip/inno_hdmi.h rename to drivers/gpu/drm/rockchip/inno_hdmi-rockchip.h diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.c b/drivers/gpu/drm/rockchi= p/inno_hdmi.c deleted file mode 100644 index 42ef62aa0a1e..000000000000 --- a/drivers/gpu/drm/rockchip/inno_hdmi.c +++ /dev/null @@ -1,1025 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd - * Zheng Yang - * Yakir Yang - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "rockchip_drm_drv.h" - -#include "inno_hdmi.h" - -#define INNO_HDMI_MIN_TMDS_CLOCK 25000000U - -struct inno_hdmi_phy_config { - unsigned long pixelclock; - u8 pre_emphasis; - u8 voltage_level_control; -}; - -struct inno_hdmi_variant { - struct inno_hdmi_phy_config *phy_configs; - struct inno_hdmi_phy_config *default_phy_config; -}; - -struct inno_hdmi_i2c { - struct i2c_adapter adap; - - u8 ddc_addr; - u8 segment_addr; - - struct mutex lock; - struct completion cmp; -}; - -struct inno_hdmi { - struct device *dev; - - struct clk *pclk; - struct clk *refclk; - void __iomem *regs; - - struct drm_connector connector; - struct rockchip_encoder encoder; - - struct inno_hdmi_i2c *i2c; - struct i2c_adapter *ddc; - - const struct inno_hdmi_variant *variant; -}; - -struct inno_hdmi_connector_state { - struct drm_connector_state base; - unsigned int colorimetry; -}; - -static struct inno_hdmi *encoder_to_inno_hdmi(struct drm_encoder *encoder) -{ - struct rockchip_encoder *rkencoder =3D to_rockchip_encoder(encoder); - - return container_of(rkencoder, struct inno_hdmi, encoder); -} - -static struct inno_hdmi *connector_to_inno_hdmi(struct drm_connector *conn= ector) -{ - return container_of(connector, struct inno_hdmi, connector); -} - -#define to_inno_hdmi_conn_state(conn_state) \ - container_of_const(conn_state, struct inno_hdmi_connector_state, base) - -enum { - CSC_RGB_0_255_TO_ITU601_16_235_8BIT, - CSC_RGB_0_255_TO_ITU709_16_235_8BIT, - CSC_RGB_0_255_TO_RGB_16_235_8BIT, -}; - -static const char coeff_csc[][24] =3D { - /* - * RGB2YUV:601 SD mode: - * Cb =3D -0.291G - 0.148R + 0.439B + 128 - * Y =3D 0.504G + 0.257R + 0.098B + 16 - * Cr =3D -0.368G + 0.439R - 0.071B + 128 - */ - { - 0x11, 0x5f, 0x01, 0x82, 0x10, 0x23, 0x00, 0x80, - 0x02, 0x1c, 0x00, 0xa1, 0x00, 0x36, 0x00, 0x1e, - 0x11, 0x29, 0x10, 0x59, 0x01, 0x82, 0x00, 0x80 - }, - /* - * RGB2YUV:709 HD mode: - * Cb =3D - 0.338G - 0.101R + 0.439B + 128 - * Y =3D 0.614G + 0.183R + 0.062B + 16 - * Cr =3D - 0.399G + 0.439R - 0.040B + 128 - */ - { - 0x11, 0x98, 0x01, 0xc1, 0x10, 0x28, 0x00, 0x80, - 0x02, 0x74, 0x00, 0xbb, 0x00, 0x3f, 0x00, 0x10, - 0x11, 0x5a, 0x10, 0x67, 0x01, 0xc1, 0x00, 0x80 - }, - /* - * RGB[0:255]2RGB[16:235]: - * R' =3D R x (235-16)/255 + 16; - * G' =3D G x (235-16)/255 + 16; - * B' =3D B x (235-16)/255 + 16; - */ - { - 0x00, 0x00, 0x03, 0x6F, 0x00, 0x00, 0x00, 0x10, - 0x03, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, - 0x00, 0x00, 0x00, 0x00, 0x03, 0x6F, 0x00, 0x10 - }, -}; - -static struct inno_hdmi_phy_config rk3036_hdmi_phy_configs[] =3D { - { 74250000, 0x3f, 0xbb }, - { 165000000, 0x6f, 0xbb }, - { ~0UL, 0x00, 0x00 } -}; - -static struct inno_hdmi_phy_config rk3128_hdmi_phy_configs[] =3D { - { 74250000, 0x3f, 0xaa }, - { 165000000, 0x5f, 0xaa }, - { ~0UL, 0x00, 0x00 } -}; - -static int inno_hdmi_find_phy_config(struct inno_hdmi *hdmi, - unsigned long pixelclk) -{ - const struct inno_hdmi_phy_config *phy_configs =3D - hdmi->variant->phy_configs; - int i; - - for (i =3D 0; phy_configs[i].pixelclock !=3D ~0UL; i++) { - if (pixelclk <=3D phy_configs[i].pixelclock) - return i; - } - - DRM_DEV_DEBUG(hdmi->dev, "No phy configuration for pixelclock %lu\n", - pixelclk); - - return -EINVAL; -} - -static inline u8 hdmi_readb(struct inno_hdmi *hdmi, u16 offset) -{ - return readl_relaxed(hdmi->regs + (offset) * 0x04); -} - -static inline void hdmi_writeb(struct inno_hdmi *hdmi, u16 offset, u32 val) -{ - writel_relaxed(val, hdmi->regs + (offset) * 0x04); -} - -static inline void hdmi_modb(struct inno_hdmi *hdmi, u16 offset, - u32 msk, u32 val) -{ - u8 temp =3D hdmi_readb(hdmi, offset) & ~msk; - - temp |=3D val & msk; - hdmi_writeb(hdmi, offset, temp); -} - -static void inno_hdmi_i2c_init(struct inno_hdmi *hdmi, unsigned long long = rate) -{ - unsigned long long ddc_bus_freq =3D rate >> 2; - - do_div(ddc_bus_freq, HDMI_SCL_RATE); - - hdmi_writeb(hdmi, DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF); - hdmi_writeb(hdmi, DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF); - - /* Clear the EDID interrupt flag and mute the interrupt */ - hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0); - hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY); -} - -static void inno_hdmi_sys_power(struct inno_hdmi *hdmi, bool enable) -{ - if (enable) - hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_ON); - else - hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_OFF); -} - -static void inno_hdmi_standby(struct inno_hdmi *hdmi) -{ - inno_hdmi_sys_power(hdmi, false); - - hdmi_writeb(hdmi, HDMI_PHY_DRIVER, 0x00); - hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, 0x00); - hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x00); - hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15); -}; - -static void inno_hdmi_power_up(struct inno_hdmi *hdmi, - unsigned long mpixelclock) -{ - struct inno_hdmi_phy_config *phy_config; - int ret =3D inno_hdmi_find_phy_config(hdmi, mpixelclock); - - if (ret < 0) { - phy_config =3D hdmi->variant->default_phy_config; - DRM_DEV_ERROR(hdmi->dev, - "Using default phy configuration for TMDS rate %lu", - mpixelclock); - } else { - phy_config =3D &hdmi->variant->phy_configs[ret]; - } - - inno_hdmi_sys_power(hdmi, false); - - hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, phy_config->pre_emphasis); - hdmi_writeb(hdmi, HDMI_PHY_DRIVER, phy_config->voltage_level_control); - hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15); - hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x14); - hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x10); - hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x0f); - hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x00); - hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x01); - - inno_hdmi_sys_power(hdmi, true); -}; - -static void inno_hdmi_reset(struct inno_hdmi *hdmi) -{ - u32 val; - u32 msk; - - hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_DIGITAL, v_NOT_RST_DIGITAL); - udelay(100); - - hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_ANALOG, v_NOT_RST_ANALOG); - udelay(100); - - msk =3D m_REG_CLK_INV | m_REG_CLK_SOURCE | m_POWER | m_INT_POL; - val =3D v_REG_CLK_INV | v_REG_CLK_SOURCE_SYS | v_PWR_ON | v_INT_POL_HIGH; - hdmi_modb(hdmi, HDMI_SYS_CTRL, msk, val); - - inno_hdmi_standby(hdmi); -} - -static int inno_hdmi_disable_frame(struct drm_connector *connector, - enum hdmi_infoframe_type type) -{ - struct inno_hdmi *hdmi =3D connector_to_inno_hdmi(connector); - - if (type !=3D HDMI_INFOFRAME_TYPE_AVI) { - drm_err(connector->dev, - "Unsupported infoframe type: %u\n", type); - return 0; - } - - hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_BUF_INDEX, INFOFRAME_AVI); - - return 0; -} - -static int inno_hdmi_upload_frame(struct drm_connector *connector, - enum hdmi_infoframe_type type, - const u8 *buffer, size_t len) -{ - struct inno_hdmi *hdmi =3D connector_to_inno_hdmi(connector); - ssize_t i; - - if (type !=3D HDMI_INFOFRAME_TYPE_AVI) { - drm_err(connector->dev, - "Unsupported infoframe type: %u\n", type); - return 0; - } - - inno_hdmi_disable_frame(connector, type); - - for (i =3D 0; i < len; i++) - hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_ADDR + i, buffer[i]); - - return 0; -} - -static const struct drm_connector_hdmi_funcs inno_hdmi_hdmi_connector_func= s =3D { - .clear_infoframe =3D inno_hdmi_disable_frame, - .write_infoframe =3D inno_hdmi_upload_frame, -}; - -static int inno_hdmi_config_video_csc(struct inno_hdmi *hdmi) -{ - struct drm_connector *connector =3D &hdmi->connector; - struct drm_connector_state *conn_state =3D connector->state; - struct inno_hdmi_connector_state *inno_conn_state =3D - to_inno_hdmi_conn_state(conn_state); - int c0_c2_change =3D 0; - int csc_enable =3D 0; - int csc_mode =3D 0; - int auto_csc =3D 0; - int value; - int i; - - /* Input video mode is SDR RGB24bit, data enable signal from external */ - hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL1, v_DE_EXTERNAL | - v_VIDEO_INPUT_FORMAT(VIDEO_INPUT_SDR_RGB444)); - - /* Input color hardcode to RGB, and output color hardcode to RGB888 */ - value =3D v_VIDEO_INPUT_BITS(VIDEO_INPUT_8BITS) | - v_VIDEO_OUTPUT_COLOR(0) | - v_VIDEO_INPUT_CSP(0); - hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL2, value); - - if (conn_state->hdmi.output_format =3D=3D HDMI_COLORSPACE_RGB) { - if (conn_state->hdmi.is_limited_range) { - csc_mode =3D CSC_RGB_0_255_TO_RGB_16_235_8BIT; - auto_csc =3D AUTO_CSC_DISABLE; - c0_c2_change =3D C0_C2_CHANGE_DISABLE; - csc_enable =3D v_CSC_ENABLE; - - } else { - value =3D v_SOF_DISABLE | v_COLOR_DEPTH_NOT_INDICATED(1); - hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value); - - hdmi_modb(hdmi, HDMI_VIDEO_CONTRL, - m_VIDEO_AUTO_CSC | m_VIDEO_C0_C2_SWAP, - v_VIDEO_AUTO_CSC(AUTO_CSC_DISABLE) | - v_VIDEO_C0_C2_SWAP(C0_C2_CHANGE_DISABLE)); - return 0; - } - } else { - if (inno_conn_state->colorimetry =3D=3D HDMI_COLORIMETRY_ITU_601) { - if (conn_state->hdmi.output_format =3D=3D HDMI_COLORSPACE_YUV444) { - csc_mode =3D CSC_RGB_0_255_TO_ITU601_16_235_8BIT; - auto_csc =3D AUTO_CSC_DISABLE; - c0_c2_change =3D C0_C2_CHANGE_DISABLE; - csc_enable =3D v_CSC_ENABLE; - } - } else { - if (conn_state->hdmi.output_format =3D=3D HDMI_COLORSPACE_YUV444) { - csc_mode =3D CSC_RGB_0_255_TO_ITU709_16_235_8BIT; - auto_csc =3D AUTO_CSC_DISABLE; - c0_c2_change =3D C0_C2_CHANGE_DISABLE; - csc_enable =3D v_CSC_ENABLE; - } - } - } - - for (i =3D 0; i < 24; i++) - hdmi_writeb(hdmi, HDMI_VIDEO_CSC_COEF + i, - coeff_csc[csc_mode][i]); - - value =3D v_SOF_DISABLE | csc_enable | v_COLOR_DEPTH_NOT_INDICATED(1); - hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value); - hdmi_modb(hdmi, HDMI_VIDEO_CONTRL, m_VIDEO_AUTO_CSC | - m_VIDEO_C0_C2_SWAP, v_VIDEO_AUTO_CSC(auto_csc) | - v_VIDEO_C0_C2_SWAP(c0_c2_change)); - - return 0; -} - -static int inno_hdmi_config_video_timing(struct inno_hdmi *hdmi, - struct drm_display_mode *mode) -{ - int value; - - /* Set detail external video timing polarity and interlace mode */ - value =3D v_EXTERANL_VIDEO(1); - value |=3D mode->flags & DRM_MODE_FLAG_PHSYNC ? - v_HSYNC_POLARITY(1) : v_HSYNC_POLARITY(0); - value |=3D mode->flags & DRM_MODE_FLAG_PVSYNC ? - v_VSYNC_POLARITY(1) : v_VSYNC_POLARITY(0); - value |=3D mode->flags & DRM_MODE_FLAG_INTERLACE ? - v_INETLACE(1) : v_INETLACE(0); - hdmi_writeb(hdmi, HDMI_VIDEO_TIMING_CTL, value); - - /* Set detail external video timing */ - value =3D mode->htotal; - hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_L, value & 0xFF); - hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_H, (value >> 8) & 0xFF); - - value =3D mode->htotal - mode->hdisplay; - hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_L, value & 0xFF); - hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_H, (value >> 8) & 0xFF); - - value =3D mode->htotal - mode->hsync_start; - hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_L, value & 0xFF); - hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_H, (value >> 8) & 0xFF); - - value =3D mode->hsync_end - mode->hsync_start; - hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_L, value & 0xFF); - hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_H, (value >> 8) & 0xFF); - - value =3D mode->vtotal; - hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_L, value & 0xFF); - hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_H, (value >> 8) & 0xFF); - - value =3D mode->vtotal - mode->vdisplay; - hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VBLANK, value & 0xFF); - - value =3D mode->vtotal - mode->vsync_start; - hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDELAY, value & 0xFF); - - value =3D mode->vsync_end - mode->vsync_start; - hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDURATION, value & 0xFF); - - hdmi_writeb(hdmi, HDMI_PHY_PRE_DIV_RATIO, 0x1e); - hdmi_writeb(hdmi, HDMI_PHY_FEEDBACK_DIV_RATIO_LOW, 0x2c); - hdmi_writeb(hdmi, HDMI_PHY_FEEDBACK_DIV_RATIO_HIGH, 0x01); - - return 0; -} - -static int inno_hdmi_setup(struct inno_hdmi *hdmi, - struct drm_atomic_state *state) -{ - struct drm_connector *connector =3D &hdmi->connector; - struct drm_display_info *display =3D &connector->display_info; - struct drm_connector_state *new_conn_state; - struct drm_crtc_state *new_crtc_state; - - new_conn_state =3D drm_atomic_get_new_connector_state(state, connector); - if (WARN_ON(!new_conn_state)) - return -EINVAL; - - new_crtc_state =3D drm_atomic_get_new_crtc_state(state, new_conn_state->c= rtc); - if (WARN_ON(!new_crtc_state)) - return -EINVAL; - - /* Mute video and audio output */ - hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK, - v_AUDIO_MUTE(1) | v_VIDEO_MUTE(1)); - - /* Set HDMI Mode */ - hdmi_writeb(hdmi, HDMI_HDCP_CTRL, - v_HDMI_DVI(display->is_hdmi)); - - inno_hdmi_config_video_timing(hdmi, &new_crtc_state->adjusted_mode); - - inno_hdmi_config_video_csc(hdmi); - - drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); - - /* - * When IP controller have configured to an accurate video - * timing, then the TMDS clock source would be switched to - * DCLK_LCDC, so we need to init the TMDS rate to mode pixel - * clock rate, and reconfigure the DDC clock. - */ - inno_hdmi_i2c_init(hdmi, new_conn_state->hdmi.tmds_char_rate); - - /* Unmute video and audio output */ - hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK, - v_AUDIO_MUTE(0) | v_VIDEO_MUTE(0)); - - inno_hdmi_power_up(hdmi, new_conn_state->hdmi.tmds_char_rate); - - return 0; -} - -static enum drm_mode_status inno_hdmi_display_mode_valid(struct inno_hdmi = *hdmi, - struct drm_display_mode *mode) -{ - unsigned long mpixelclk, max_tolerance; - long rounded_refclk; - - /* No support for double-clock modes */ - if (mode->flags & DRM_MODE_FLAG_DBLCLK) - return MODE_BAD; - - mpixelclk =3D mode->clock * 1000; - - if (mpixelclk < INNO_HDMI_MIN_TMDS_CLOCK) - return MODE_CLOCK_LOW; - - if (inno_hdmi_find_phy_config(hdmi, mpixelclk) < 0) - return MODE_CLOCK_HIGH; - - if (hdmi->refclk) { - rounded_refclk =3D clk_round_rate(hdmi->refclk, mpixelclk); - if (rounded_refclk < 0) - return MODE_BAD; - - /* Vesa DMT standard mentions +/- 0.5% max tolerance */ - max_tolerance =3D mpixelclk / 200; - if (abs_diff((unsigned long)rounded_refclk, mpixelclk) > max_tolerance) - return MODE_NOCLOCK; - } - - return MODE_OK; -} - -static void inno_hdmi_encoder_enable(struct drm_encoder *encoder, - struct drm_atomic_state *state) -{ - struct inno_hdmi *hdmi =3D encoder_to_inno_hdmi(encoder); - - inno_hdmi_setup(hdmi, state); -} - -static void inno_hdmi_encoder_disable(struct drm_encoder *encoder, - struct drm_atomic_state *state) -{ - struct inno_hdmi *hdmi =3D encoder_to_inno_hdmi(encoder); - - inno_hdmi_standby(hdmi); -} - -static int -inno_hdmi_encoder_atomic_check(struct drm_encoder *encoder, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) -{ - struct rockchip_crtc_state *s =3D to_rockchip_crtc_state(crtc_state); - struct drm_display_mode *mode =3D &crtc_state->adjusted_mode; - u8 vic =3D drm_match_cea_mode(mode); - struct inno_hdmi_connector_state *inno_conn_state =3D - to_inno_hdmi_conn_state(conn_state); - - s->output_mode =3D ROCKCHIP_OUT_MODE_P888; - s->output_type =3D DRM_MODE_CONNECTOR_HDMIA; - - if (vic =3D=3D 6 || vic =3D=3D 7 || - vic =3D=3D 21 || vic =3D=3D 22 || - vic =3D=3D 2 || vic =3D=3D 3 || - vic =3D=3D 17 || vic =3D=3D 18) - inno_conn_state->colorimetry =3D HDMI_COLORIMETRY_ITU_601; - else - inno_conn_state->colorimetry =3D HDMI_COLORIMETRY_ITU_709; - - return 0; -} - -static const struct drm_encoder_helper_funcs inno_hdmi_encoder_helper_func= s =3D { - .atomic_check =3D inno_hdmi_encoder_atomic_check, - .atomic_enable =3D inno_hdmi_encoder_enable, - .atomic_disable =3D inno_hdmi_encoder_disable, -}; - -static enum drm_connector_status -inno_hdmi_connector_detect(struct drm_connector *connector, bool force) -{ - struct inno_hdmi *hdmi =3D connector_to_inno_hdmi(connector); - - return (hdmi_readb(hdmi, HDMI_STATUS) & m_HOTPLUG) ? - connector_status_connected : connector_status_disconnected; -} - -static int inno_hdmi_connector_get_modes(struct drm_connector *connector) -{ - struct inno_hdmi *hdmi =3D connector_to_inno_hdmi(connector); - const struct drm_edid *drm_edid; - int ret =3D 0; - - if (!hdmi->ddc) - return 0; - - drm_edid =3D drm_edid_read_ddc(connector, hdmi->ddc); - drm_edid_connector_update(connector, drm_edid); - ret =3D drm_edid_connector_add_modes(connector); - drm_edid_free(drm_edid); - - return ret; -} - -static enum drm_mode_status -inno_hdmi_connector_mode_valid(struct drm_connector *connector, - struct drm_display_mode *mode) -{ - struct inno_hdmi *hdmi =3D connector_to_inno_hdmi(connector); - - return inno_hdmi_display_mode_valid(hdmi, mode); -} - -static void -inno_hdmi_connector_destroy_state(struct drm_connector *connector, - struct drm_connector_state *state) -{ - struct inno_hdmi_connector_state *inno_conn_state =3D - to_inno_hdmi_conn_state(state); - - __drm_atomic_helper_connector_destroy_state(&inno_conn_state->base); - kfree(inno_conn_state); -} - -static void inno_hdmi_connector_reset(struct drm_connector *connector) -{ - struct inno_hdmi_connector_state *inno_conn_state; - - if (connector->state) { - inno_hdmi_connector_destroy_state(connector, connector->state); - connector->state =3D NULL; - } - - inno_conn_state =3D kzalloc(sizeof(*inno_conn_state), GFP_KERNEL); - if (!inno_conn_state) - return; - - __drm_atomic_helper_connector_reset(connector, &inno_conn_state->base); - __drm_atomic_helper_connector_hdmi_reset(connector, connector->state); - - inno_conn_state->colorimetry =3D HDMI_COLORIMETRY_ITU_709; -} - -static struct drm_connector_state * -inno_hdmi_connector_duplicate_state(struct drm_connector *connector) -{ - struct inno_hdmi_connector_state *inno_conn_state; - - if (WARN_ON(!connector->state)) - return NULL; - - inno_conn_state =3D kmemdup(to_inno_hdmi_conn_state(connector->state), - sizeof(*inno_conn_state), GFP_KERNEL); - - if (!inno_conn_state) - return NULL; - - __drm_atomic_helper_connector_duplicate_state(connector, - &inno_conn_state->base); - - return &inno_conn_state->base; -} - -static const struct drm_connector_funcs inno_hdmi_connector_funcs =3D { - .fill_modes =3D drm_helper_probe_single_connector_modes, - .detect =3D inno_hdmi_connector_detect, - .reset =3D inno_hdmi_connector_reset, - .atomic_duplicate_state =3D inno_hdmi_connector_duplicate_state, - .atomic_destroy_state =3D inno_hdmi_connector_destroy_state, -}; - -static struct drm_connector_helper_funcs inno_hdmi_connector_helper_funcs = =3D { - .atomic_check =3D drm_atomic_helper_connector_hdmi_check, - .get_modes =3D inno_hdmi_connector_get_modes, - .mode_valid =3D inno_hdmi_connector_mode_valid, -}; - -static int inno_hdmi_register(struct drm_device *drm, struct inno_hdmi *hd= mi) -{ - struct drm_encoder *encoder =3D &hdmi->encoder.encoder; - struct device *dev =3D hdmi->dev; - - encoder->possible_crtcs =3D drm_of_find_possible_crtcs(drm, dev->of_node); - - /* - * If we failed to find the CRTC(s) which this encoder is - * supposed to be connected to, it's because the CRTC has - * not been registered yet. Defer probing, and hope that - * the required CRTC is added later. - */ - if (encoder->possible_crtcs =3D=3D 0) - return -EPROBE_DEFER; - - drm_encoder_helper_add(encoder, &inno_hdmi_encoder_helper_funcs); - drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); - - hdmi->connector.polled =3D DRM_CONNECTOR_POLL_HPD; - - drm_connector_helper_add(&hdmi->connector, - &inno_hdmi_connector_helper_funcs); - drmm_connector_hdmi_init(drm, &hdmi->connector, - "Rockchip", "Inno HDMI", - &inno_hdmi_connector_funcs, - &inno_hdmi_hdmi_connector_funcs, - DRM_MODE_CONNECTOR_HDMIA, - hdmi->ddc, - BIT(HDMI_COLORSPACE_RGB), - 8); - - drm_connector_attach_encoder(&hdmi->connector, encoder); - - return 0; -} - -static irqreturn_t inno_hdmi_i2c_irq(struct inno_hdmi *hdmi) -{ - struct inno_hdmi_i2c *i2c =3D hdmi->i2c; - u8 stat; - - stat =3D hdmi_readb(hdmi, HDMI_INTERRUPT_STATUS1); - if (!(stat & m_INT_EDID_READY)) - return IRQ_NONE; - - /* Clear HDMI EDID interrupt flag */ - hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY); - - complete(&i2c->cmp); - - return IRQ_HANDLED; -} - -static irqreturn_t inno_hdmi_hardirq(int irq, void *dev_id) -{ - struct inno_hdmi *hdmi =3D dev_id; - irqreturn_t ret =3D IRQ_NONE; - u8 interrupt; - - if (hdmi->i2c) - ret =3D inno_hdmi_i2c_irq(hdmi); - - interrupt =3D hdmi_readb(hdmi, HDMI_STATUS); - if (interrupt & m_INT_HOTPLUG) { - hdmi_modb(hdmi, HDMI_STATUS, m_INT_HOTPLUG, m_INT_HOTPLUG); - ret =3D IRQ_WAKE_THREAD; - } - - return ret; -} - -static irqreturn_t inno_hdmi_irq(int irq, void *dev_id) -{ - struct inno_hdmi *hdmi =3D dev_id; - - drm_helper_hpd_irq_event(hdmi->connector.dev); - - return IRQ_HANDLED; -} - -static int inno_hdmi_i2c_read(struct inno_hdmi *hdmi, struct i2c_msg *msgs) -{ - int length =3D msgs->len; - u8 *buf =3D msgs->buf; - int ret; - - ret =3D wait_for_completion_timeout(&hdmi->i2c->cmp, HZ / 10); - if (!ret) - return -EAGAIN; - - while (length--) - *buf++ =3D hdmi_readb(hdmi, HDMI_EDID_FIFO_ADDR); - - return 0; -} - -static int inno_hdmi_i2c_write(struct inno_hdmi *hdmi, struct i2c_msg *msg= s) -{ - /* - * The DDC module only support read EDID message, so - * we assume that each word write to this i2c adapter - * should be the offset of EDID word address. - */ - if ((msgs->len !=3D 1) || - ((msgs->addr !=3D DDC_ADDR) && (msgs->addr !=3D DDC_SEGMENT_ADDR))) - return -EINVAL; - - reinit_completion(&hdmi->i2c->cmp); - - if (msgs->addr =3D=3D DDC_SEGMENT_ADDR) - hdmi->i2c->segment_addr =3D msgs->buf[0]; - if (msgs->addr =3D=3D DDC_ADDR) - hdmi->i2c->ddc_addr =3D msgs->buf[0]; - - /* Set edid fifo first addr */ - hdmi_writeb(hdmi, HDMI_EDID_FIFO_OFFSET, 0x00); - - /* Set edid word address 0x00/0x80 */ - hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr); - - /* Set edid segment pointer */ - hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr); - - return 0; -} - -static int inno_hdmi_i2c_xfer(struct i2c_adapter *adap, - struct i2c_msg *msgs, int num) -{ - struct inno_hdmi *hdmi =3D i2c_get_adapdata(adap); - struct inno_hdmi_i2c *i2c =3D hdmi->i2c; - int i, ret =3D 0; - - mutex_lock(&i2c->lock); - - /* Clear the EDID interrupt flag and unmute the interrupt */ - hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, m_INT_EDID_READY); - hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY); - - for (i =3D 0; i < num; i++) { - DRM_DEV_DEBUG(hdmi->dev, - "xfer: num: %d/%d, len: %d, flags: %#x\n", - i + 1, num, msgs[i].len, msgs[i].flags); - - if (msgs[i].flags & I2C_M_RD) - ret =3D inno_hdmi_i2c_read(hdmi, &msgs[i]); - else - ret =3D inno_hdmi_i2c_write(hdmi, &msgs[i]); - - if (ret < 0) - break; - } - - if (!ret) - ret =3D num; - - /* Mute HDMI EDID interrupt */ - hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0); - - mutex_unlock(&i2c->lock); - - return ret; -} - -static u32 inno_hdmi_i2c_func(struct i2c_adapter *adapter) -{ - return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; -} - -static const struct i2c_algorithm inno_hdmi_algorithm =3D { - .master_xfer =3D inno_hdmi_i2c_xfer, - .functionality =3D inno_hdmi_i2c_func, -}; - -static struct i2c_adapter *inno_hdmi_i2c_adapter(struct inno_hdmi *hdmi) -{ - struct i2c_adapter *adap; - struct inno_hdmi_i2c *i2c; - int ret; - - i2c =3D devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); - if (!i2c) - return ERR_PTR(-ENOMEM); - - mutex_init(&i2c->lock); - init_completion(&i2c->cmp); - - adap =3D &i2c->adap; - adap->owner =3D THIS_MODULE; - adap->dev.parent =3D hdmi->dev; - adap->dev.of_node =3D hdmi->dev->of_node; - adap->algo =3D &inno_hdmi_algorithm; - strscpy(adap->name, "Inno HDMI", sizeof(adap->name)); - i2c_set_adapdata(adap, hdmi); - - ret =3D i2c_add_adapter(adap); - if (ret) { - dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); - devm_kfree(hdmi->dev, i2c); - return ERR_PTR(ret); - } - - hdmi->i2c =3D i2c; - - DRM_DEV_INFO(hdmi->dev, "registered %s I2C bus driver\n", adap->name); - - return adap; -} - -static int inno_hdmi_bind(struct device *dev, struct device *master, - void *data) -{ - struct platform_device *pdev =3D to_platform_device(dev); - struct drm_device *drm =3D data; - struct inno_hdmi *hdmi; - const struct inno_hdmi_variant *variant; - int irq; - int ret; - - hdmi =3D devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); - if (!hdmi) - return -ENOMEM; - - hdmi->dev =3D dev; - - variant =3D of_device_get_match_data(hdmi->dev); - if (!variant) - return -EINVAL; - - hdmi->variant =3D variant; - - hdmi->regs =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(hdmi->regs)) - return PTR_ERR(hdmi->regs); - - hdmi->pclk =3D devm_clk_get(hdmi->dev, "pclk"); - if (IS_ERR(hdmi->pclk)) { - DRM_DEV_ERROR(hdmi->dev, "Unable to get HDMI pclk clk\n"); - return PTR_ERR(hdmi->pclk); - } - - ret =3D clk_prepare_enable(hdmi->pclk); - if (ret) { - DRM_DEV_ERROR(hdmi->dev, - "Cannot enable HDMI pclk clock: %d\n", ret); - return ret; - } - - hdmi->refclk =3D devm_clk_get_optional(hdmi->dev, "ref"); - if (IS_ERR(hdmi->refclk)) { - DRM_DEV_ERROR(hdmi->dev, "Unable to get HDMI reference clock\n"); - ret =3D PTR_ERR(hdmi->refclk); - goto err_disable_pclk; - } - - ret =3D clk_prepare_enable(hdmi->refclk); - if (ret) { - DRM_DEV_ERROR(hdmi->dev, - "Cannot enable HDMI reference clock: %d\n", ret); - goto err_disable_pclk; - } - - irq =3D platform_get_irq(pdev, 0); - if (irq < 0) { - ret =3D irq; - goto err_disable_clk; - } - - inno_hdmi_reset(hdmi); - - hdmi->ddc =3D inno_hdmi_i2c_adapter(hdmi); - if (IS_ERR(hdmi->ddc)) { - ret =3D PTR_ERR(hdmi->ddc); - hdmi->ddc =3D NULL; - goto err_disable_clk; - } - - /* - * When the controller isn't configured to an accurate - * video timing and there is no reference clock available, - * then the TMDS clock source would be switched to PCLK_HDMI, - * so we need to init the TMDS rate to PCLK rate, and - * reconfigure the DDC clock. - */ - if (hdmi->refclk) - inno_hdmi_i2c_init(hdmi, clk_get_rate(hdmi->refclk)); - else - inno_hdmi_i2c_init(hdmi, clk_get_rate(hdmi->pclk)); - - ret =3D inno_hdmi_register(drm, hdmi); - if (ret) - goto err_put_adapter; - - dev_set_drvdata(dev, hdmi); - - /* Unmute hotplug interrupt */ - hdmi_modb(hdmi, HDMI_STATUS, m_MASK_INT_HOTPLUG, v_MASK_INT_HOTPLUG(1)); - - ret =3D devm_request_threaded_irq(dev, irq, inno_hdmi_hardirq, - inno_hdmi_irq, IRQF_SHARED, - dev_name(dev), hdmi); - if (ret < 0) - goto err_cleanup_hdmi; - - return 0; -err_cleanup_hdmi: - hdmi->connector.funcs->destroy(&hdmi->connector); - hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); -err_put_adapter: - i2c_put_adapter(hdmi->ddc); -err_disable_clk: - clk_disable_unprepare(hdmi->refclk); -err_disable_pclk: - clk_disable_unprepare(hdmi->pclk); - return ret; -} - -static void inno_hdmi_unbind(struct device *dev, struct device *master, - void *data) -{ - struct inno_hdmi *hdmi =3D dev_get_drvdata(dev); - - hdmi->connector.funcs->destroy(&hdmi->connector); - hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); - - i2c_put_adapter(hdmi->ddc); - clk_disable_unprepare(hdmi->refclk); - clk_disable_unprepare(hdmi->pclk); -} - -static const struct component_ops inno_hdmi_ops =3D { - .bind =3D inno_hdmi_bind, - .unbind =3D inno_hdmi_unbind, -}; - -static int inno_hdmi_probe(struct platform_device *pdev) -{ - return component_add(&pdev->dev, &inno_hdmi_ops); -} - -static void inno_hdmi_remove(struct platform_device *pdev) -{ - component_del(&pdev->dev, &inno_hdmi_ops); -} - -static const struct inno_hdmi_variant rk3036_inno_hdmi_variant =3D { - .phy_configs =3D rk3036_hdmi_phy_configs, - .default_phy_config =3D &rk3036_hdmi_phy_configs[1], -}; - -static const struct inno_hdmi_variant rk3128_inno_hdmi_variant =3D { - .phy_configs =3D rk3128_hdmi_phy_configs, - .default_phy_config =3D &rk3128_hdmi_phy_configs[1], -}; - -static const struct of_device_id inno_hdmi_dt_ids[] =3D { - { .compatible =3D "rockchip,rk3036-inno-hdmi", - .data =3D &rk3036_inno_hdmi_variant, - }, - { .compatible =3D "rockchip,rk3128-inno-hdmi", - .data =3D &rk3128_inno_hdmi_variant, - }, - {}, -}; -MODULE_DEVICE_TABLE(of, inno_hdmi_dt_ids); - -struct platform_driver inno_hdmi_driver =3D { - .probe =3D inno_hdmi_probe, - .remove_new =3D inno_hdmi_remove, - .driver =3D { - .name =3D "innohdmi-rockchip", - .of_match_table =3D inno_hdmi_dt_ids, - }, -}; diff --git a/include/drm/bridge/inno_hdmi.h b/include/drm/bridge/inno_hdmi.h new file mode 100644 index 000000000000..bfd22f180153 --- /dev/null +++ b/include/drm/bridge/inno_hdmi.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) StarFive Technology Co., Ltd. + */ + +#ifndef __INNO_COMMON_HDMI__ +#define __INNO_COMMON_HDMI__ + +#include +#include +#include +#include + +struct inno_hdmi; + +struct inno_hdmi_i2c { + u8 ddc_addr; + u8 segment_addr; + + struct i2c_adapter adap; + struct mutex lock; /* For i2c operation. */ + struct completion cmp; +}; + +struct inno_hdmi_plat_data { + const char *vendor; + const char *product; + + /* Platform-specific mode validation*/ + enum drm_mode_status (*mode_valid)(struct inno_hdmi *hdmi, + const struct drm_display_mode *mode); + int (*hdmi_clear_infoframe)(struct inno_hdmi *hdmi, enum hdmi_infoframe_t= ype type); + int (*hdmi_write_infoframe)(struct inno_hdmi *hdmi, enum hdmi_infoframe_t= ype type, + const u8 *buffer, size_t len); +}; + +struct inno_hdmi { + struct device *dev; + void __iomem *regs; + + struct i2c_adapter *ddc; + struct drm_bridge bridge; + struct drm_bridge *next_bridge; + struct inno_hdmi_i2c *i2c; + + const struct inno_hdmi_plat_data *plat_data; +}; + +u8 hdmi_readb(struct inno_hdmi *hdmi, u16 offset); +void hdmi_writeb(struct inno_hdmi *hdmi, u16 offset, u32 val); +void hdmi_modb(struct inno_hdmi *hdmi, u16 offset, u32 msk, u32 val); + +void inno_hdmi_i2c_init(struct inno_hdmi *hdmi, unsigned long long rate); +int inno_hdmi_bind(struct drm_device *drm, struct inno_hdmi *hdmi, struct = drm_encoder *encoder); + +#endif /* __INNO_COMMON_HDMI__ */ --=20 2.34.1