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Wed, 20 Nov 2024 06:20:21 +0000 From: keith zhao To: devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org Cc: andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, hjc@rock-chips.com, heiko@sntech.de, andy.yan@rock-chips.com, william.qiu@starfivetech.com, xingyu.wu@starfivetech.com, kernel@esmil.dk, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, p.zabel@pengutronix.de, changhuang.liang@starfivetech.com, keith.zhao@starfivetech.com, jack.zhu@starfivetech.com, linux-kernel@vger.kernel.org Subject: [PATCH v5 2/9] riscv: dts: Add display property Date: Wed, 20 Nov 2024 14:18:41 +0800 Message-Id: <20241120061848.196754-3-keith.zhao@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241120061848.196754-1-keith.zhao@starfivetech.com> References: <20241120061848.196754-1-keith.zhao@starfivetech.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BJXPR01CA0059.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:12::26) To NTZPR01MB1050.CHNPR01.prod.partner.outlook.cn (2406:e500:c510:1::6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: NTZPR01MB1050:EE_|NTZPR01MB1100:EE_ X-MS-Office365-Filtering-Correlation-Id: 3800ae5a-c81e-4662-4921-08dd092b6925 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|52116014|1800799024|41320700013|366016|38350700014; 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charset="utf-8" Add the display DT nodes in Starfive JH7110 soc-specific DT file. Signed-off-by: keith zhao --- .../boot/dts/starfive/jh7110-common.dtsi | 125 ++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 41 ++++++ 2 files changed, 166 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/b= oot/dts/starfive/jh7110-common.dtsi index 9d77713f5361..301b56f2ef0c 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -30,6 +30,25 @@ memory@40000000 { reg =3D <0x0 0x40000000 0x1 0x0>; }; =20 + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* vout applies for space from this CMA + * Without this CMA reservation, + * vout may not work properly. + */ + linux,cma { + compatible =3D "shared-dma-pool"; + reusable; + size =3D <0x0 0x20000000>; + alignment =3D <0x0 0x1000>; + alloc-ranges =3D <0x0 0x70000000 0x0 0x20000000>; + linux,cma-default; + }; + }; + gpio-restart { compatible =3D "gpio-restart"; gpios =3D <&sysgpio 35 GPIO_ACTIVE_HIGH>; @@ -62,12 +81,55 @@ codec { }; }; }; + + hdmi_con: hdmi-con { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint =3D <&hdmi_out_con>; + }; + }; + }; }; =20 &cpus { timebase-frequency =3D <4000000>; }; =20 +&dc8200 { + status =3D "okay"; + crtc_out: ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + dc_out0: port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + dc_out_dpi0: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&hdmi_enc>; + }; + + }; + + dc_out1: port@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + dc_out_dpi1: endpoint@1 { + reg =3D <1>; + //remote-endpoint =3D <&dsi_enc>; + }; + + }; + }; +}; + &dvp_clk { clock-frequency =3D <74250000>; }; @@ -88,6 +150,31 @@ &gmac1_rmii_refin { clock-frequency =3D <50000000>; }; =20 +&hdmi { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hdmi_pins>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + hdmi_in: port@0 { + reg =3D <0>; + hdmi_enc: endpoint { + remote-endpoint =3D <&dc_out_dpi0>; + }; + }; + + hdmi_out: port@1 { + reg =3D <1>; + hdmi_out_con: endpoint { + remote-endpoint =3D <&hdmi_con_in>; + }; + }; + }; +}; + &hdmitx0_pixelclk { clock-frequency =3D <297000000>; }; @@ -366,6 +453,40 @@ &syscrg { }; =20 &sysgpio { + hdmi_pins: hdmi-0 { + hdmi-cec-pins { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + + hdmi-hpd-pins { + pinmux =3D ; + input-enable; + bias-disable; /* external pull-up */ + }; + + hdmi-scl-pins { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + + hdmi-sda-pins { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + }; + i2c0_pins: i2c0-0 { i2c-pins { pinmux =3D ; }; + +&voutcrg { + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts= /starfive/jh7110.dtsi index 0d8339357bad..d48825822017 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -1203,6 +1203,47 @@ camss: isp@19840000 { status =3D "disabled"; }; =20 + dc8200: lcd-controller@29400000 { + compatible =3D "starfive,jh7110-dc8200"; + reg =3D <0x0 0x29400000 0x0 0x100>, + <0x0 0x29400800 0x0 0x2000>; + + interrupts =3D <95>; + clocks =3D <&syscrg JH7110_SYSCLK_NOC_BUS_DISP_AXI>, + <&voutcrg JH7110_VOUTCLK_DC8200_CORE>, + <&voutcrg JH7110_VOUTCLK_DC8200_AXI>, + <&voutcrg JH7110_VOUTCLK_DC8200_AHB>, + <&voutcrg JH7110_VOUTCLK_DC8200_PIX0>, + <&voutcrg JH7110_VOUTCLK_DC8200_PIX1>, + <&hdmitx0_pixelclk>, + <&voutcrg JH7110_VOUTCLK_DC8200_PIX>; + clock-names =3D "noc_bus", "dc_core", "axi_core", "ahb", + "channel0", "channel1", "hdmi_tx", "dc_parent"; + resets =3D <&voutcrg JH7110_VOUTRST_DC8200_AXI>, + <&voutcrg JH7110_VOUTRST_DC8200_AHB>, + <&voutcrg JH7110_VOUTRST_DC8200_CORE>; + reset-names =3D "axi","ahb", "core"; + + starfive,syscon =3D <&vout_syscon>; + }; + + hdmi: hdmi@29590000 { + compatible =3D "starfive,jh7110-inno-hdmi"; + reg =3D <0x0 0x29590000 0x0 0x4000>; + interrupts =3D <99>; + + clocks =3D <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>; + clock-names =3D "sysclk", "mclk", "bclk"; + resets =3D <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>; + }; + + vout_syscon: syscon@295b0000 { + compatible =3D "starfive,jh7110-vout-syscon", "syscon"; + reg =3D <0 0x295b0000 0 0x90>; + }; + voutcrg: clock-controller@295c0000 { compatible =3D "starfive,jh7110-voutcrg"; reg =3D <0x0 0x295c0000 0x0 0x10000>; --=20 2.34.1