From nobody Wed Dec 4 19:15:21 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29926156F20; Wed, 20 Nov 2024 07:01:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732086076; cv=none; b=q6h6tGQudBtMYUXXNhghs4FQnJM4W7BPYHTLxmJxaeLrlLGQA87v5PbPx+YZgtG3gNFgbgkJ+2tkZubakquKSgSkUSJYtm4gmm3OqjN6YJWE3qUK+zIwmqT/+DRL1Mtne7wzDxQ7T403s/0dt+sAUik4B+SB0uVP6yGalCV/P0o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732086076; c=relaxed/simple; bh=iJJVStmC73qOMZH80srXkqKSgQ6R0Sd6J9uZ5c1xxxQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EDn5zwG8RZavlt3LiKabHG51vK4cxn8Pmq2O4CKOt3Mco26kzmHBNButngxZnDoZEDoRkciVsMZZN9VxmXRWOnpQhXpJvzJf79bOvFnZOZz0TMQTD2gkvyyymW/6dzxOclsx5/JGyCu+Ii5i3MHejB2H5dMtEf+aPmxAbqV1FP0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=EfKY5cm1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="EfKY5cm1" Received: by smtp.kernel.org (Postfix) with ESMTPS id A59F2C4CED6; Wed, 20 Nov 2024 07:01:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732086075; bh=iJJVStmC73qOMZH80srXkqKSgQ6R0Sd6J9uZ5c1xxxQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=EfKY5cm1xHqfO4DYFhTqhad6kJP9uWD6ePtsSAZBW2SuHIekpHKRT1etqW8w0NJut RStIN3kFw3jlTO5uM47CsH2ep5XdSlwwLL5VpZyo3ORqtJf6TScLGOG9NH+BswsMLV 9CgrlsAxTkqa9qbO923pvNopZhGGBeDGGvkBc7wcSCs3YdZZdhAQNsn6lXLeD7O1jS k3wdYXrAylstiGbrrc/wLpl3+LQ9tdIIJ7RMQu+XNGYqEXl82r0RGbViNobUJconUx d2imL838bIxPjTtXDKvYzetveOM1avA1N4MpCHSr8lKHjZ3vXCIw0RsQbeb4KoHvml OGjsxW29PtF+A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95E29D6E2C9; Wed, 20 Nov 2024 07:01:15 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Wed, 20 Nov 2024 15:01:13 +0800 Subject: [PATCH v2 1/5] dt-bindings: clock: add Amlogic A5 PLL clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241120-a5-clk-v2-1-1208621e961d@amlogic.com> References: <20241120-a5-clk-v2-0-1208621e961d@amlogic.com> In-Reply-To: <20241120-a5-clk-v2-0-1208621e961d@amlogic.com> To: Neil Armstrong , Jerome Brunet , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chuan Liu , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Xianwei Zhao X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1732086073; l=3184; i=xianwei.zhao@amlogic.com; s=20231208; h=from:subject:message-id; bh=J3WtxjJVuoEkk9jMbN9N2KL1pm5NRc4KprmWxygPJ+A=; b=9k62n1G5A+M+Q98nHjFJjhNADSfJwM9Fh7kMQfj4eAhDqTxG05J42WueZCVnyUgkNYh2Yc8lG dM1nM+IkTGpA2laqxPRNudQlmUYj10GEgrkrlo2t+ZDVLYTt1HeJSFo X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=o4fDH8ZXL6xQg5h17eNzRljf6pwZHWWjqcOSsj3dW24= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20231208 with auth_id=107 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Chuan Liu Add the PLL clock controller dt-bindings for Amlogic A5 SoC family. Signed-off-by: Chuan Liu Reviewed-by: Rob Herring (Arm) Signed-off-by: Xianwei Zhao --- .../bindings/clock/amlogic,a5-pll-clkc.yaml | 62 ++++++++++++++++++= ++++ include/dt-bindings/clock/amlogic,a5-pll-clkc.h | 24 +++++++++ 2 files changed, 86 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/amlogic,a5-pll-clkc.ya= ml b/Documentation/devicetree/bindings/clock/amlogic,a5-pll-clkc.yaml new file mode 100644 index 000000000000..ef9e40193a1c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,a5-pll-clkc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2024 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,a5-pll-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic A5 series PLL Clock Controller + +maintainers: + - Chuan Liu + - Xianwei Zhao + +properties: + compatible: + const: amlogic,a5-pll-clkc + + reg: + maxItems: 1 + + clocks: + items: + - description: input oscillator (usually at 24MHz) + - description: input fix pll dco + - description: input fix pll + + clock-names: + items: + - const: xtal_24m + - const: fix_dco + - const: fix + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + apb { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@8000 { + compatible =3D "amlogic,a5-pll-clkc"; + reg =3D <0x0 0x8000 0x0 0x1a4>; + clocks =3D <&xtal_24m>, + <&scmi_clk 6>, + <&scmi_clk 7>; + clock-names =3D "xtal_24m", + "fix_dco", + "fix"; + #clock-cells =3D <1>; + }; + }; diff --git a/include/dt-bindings/clock/amlogic,a5-pll-clkc.h b/include/dt-b= indings/clock/amlogic,a5-pll-clkc.h new file mode 100644 index 000000000000..a74c448a8d8a --- /dev/null +++ b/include/dt-bindings/clock/amlogic,a5-pll-clkc.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + * Author: Chuan Liu + */ + +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_A5_PLL_CLKC_H +#define _DT_BINDINGS_CLOCK_AMLOGIC_A5_PLL_CLKC_H + +#define CLKID_MPLL_PREDIV 0 +#define CLKID_MPLL0_DIV 1 +#define CLKID_MPLL0 2 +#define CLKID_MPLL1_DIV 3 +#define CLKID_MPLL1 4 +#define CLKID_MPLL2_DIV 5 +#define CLKID_MPLL2 6 +#define CLKID_MPLL3_DIV 7 +#define CLKID_MPLL3 8 +#define CLKID_GP0_PLL_DCO 9 +#define CLKID_GP0_PLL 10 +#define CLKID_HIFI_PLL_DCO 11 +#define CLKID_HIFI_PLL 12 + +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_A5_PLL_CLKC_H */ --=20 2.37.1