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Tue, 19 Nov 2024 13:12:21 -0800 From: Chris Babroski To: , , CC: , , , Subject: [PATCH v2] i2c-mlxbf: Add repeated start condition support Date: Tue, 19 Nov 2024 21:12:15 +0000 Message-ID: <20241119211215.352797-1-cbabroski@nvidia.com> X-Mailer: git-send-email 2.47.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0002992B:EE_|CH3PR12MB7572:EE_ X-MS-Office365-Filtering-Correlation-Id: 308e04c2-7557-4919-1a69-08dd08dee595 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?OEXxa06Z5sDF7mMi+0k8/Z9909FsrQhBHua05U2mnmqJvqmZqxRYN9gHQs94?= =?us-ascii?Q?itPoWGK+Zl9NV5uxf8pEbX6jLlFIqAZQpjKK+zDhbsT6vmbsxw9102reB8Nr?= =?us-ascii?Q?186VekJ7ToKWsq8p3GRTcBQ5Xr6WNEaReCB2ewNyXKZlOaDAACsF9dcZ5je3?= =?us-ascii?Q?oU0Vsv1qg+/CoWQm/Kt8pYiXVpLuqyB6p9JpgswU6Fz/Y70QMUwjBK6p3y8w?= =?us-ascii?Q?fSJUMxvY8c3PDSJPx9lRm/xx5Ky35HUW4sBTRLqL1lKBYXF6YD58c8E1lMdU?= =?us-ascii?Q?UAo/F8za1UHzeVuypjtNUMRHm4d+0+CLFM76vmF+0m9ATVo9GKi61yo4xBqk?= =?us-ascii?Q?5XoMJmpvL4Hb4BwUjB4oyVA1XcnYB/vtwkVd7SSCZywiQYTxenTxjWQgYFLj?= =?us-ascii?Q?mjmp3stLqMpqb9rNy+oK50xRN77AS+ElrEpals9jaHy6mEjmzEGpnw2NW2od?= =?us-ascii?Q?Y1BwK4Wa081VjXf+MppPcdBpvXFqIbw71t8yHvHJXDUvCcufIWoka0WR+2S7?= =?us-ascii?Q?P5G0W7VxF26fB13rniCcWhtDvf5fCNDHyIOWMJDKCL01wISyEMJXPCTrY2kf?= =?us-ascii?Q?g4M5vQQLFvcWLHajV9F1FiSuyBEsEDE0OuNmO0WBEiMCdtl8GCdOpxkpv1er?= =?us-ascii?Q?8iZ5ajbsDvvwsaTN7+Jzkp7J3aESzzi5vf8S35MHpUtu7SLBx/yTKyHLZnN0?= =?us-ascii?Q?XXe/LzFLETkXOAY7Kc1K2tvuv6R7tVTjC/i2FjB1WHuWDiZHzFYs0/PNcg0F?= =?us-ascii?Q?G2rNi5pNqBPyNw6AOp2AiltmPDSOgdbO6ivtdEwbnL1aVbFbtpMoBFnyZ578?= =?us-ascii?Q?msg/2O+/1ZvtoxUgEuobcb/ANO2LUiNkqsQRoE5QZbZU6ptH1O8/l8joI9/n?= =?us-ascii?Q?TmvmMGxBIYXEAyrfFZfL+g/p343bNAgZJOWe7AB8VOJspj0GdzVcbVLrS0S3?= =?us-ascii?Q?AfZIuAbLVCslmjJ4ZU2ZmbEMlE6Lu7GVHXuCOzeigqgfAKCD1buAcuQCbuaJ?= =?us-ascii?Q?xv/MZna3jhkLBXByneedjX32odceBvtX4IFWAol+AlksNfnHgYLI+iuOSVlS?= =?us-ascii?Q?AS00vC+Vs5tsXaMRZ1tPmAiByIcCVvzDZ3cD59EAUXq/QFGeHlSxyBaLNoLT?= =?us-ascii?Q?kH9YfQz1LjnLr60FF97VnBeF/8/C0kIcwmjIsULFgu+Lms+hixQ/rktI0/xc?= =?us-ascii?Q?lhuTym2jjo/FP9Yjkgp4IHsuGjRQ6Ook1gjkcfGJbl3+roGeMUwITVK+Bjls?= =?us-ascii?Q?lDWy5PP3ybYNKP560a673R/jlo7P6JiLRWVr7mRep/3BpYYxkvfnJrX+Ze92?= =?us-ascii?Q?2Pt3K0cvbBKCMxx83WXQVJ7e5WpIUJ3sLDEgn6dCzj2EMaBfGDrDo5U9V4Mp?= =?us-ascii?Q?GRnrvA/bK1VnvkIso89CEf6/mre427hcscYD0C7KBtyF/2eUBQ=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Nov 2024 21:12:38.2119 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 308e04c2-7557-4919-1a69-08dd08dee595 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0002992B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7572 Content-Type: text/plain; charset="utf-8" Add support for SMBus repeated start conditions to the Mellanox I2C driver. This support is specifically enabled for the I2C_FUNC_SMBUS_WRITE_I2C_BLOCK implementation which is required for communication with various I2C devices on Bluefield 3. The I2C bus timing configuration values have also been updated based on latest HW testing results and found to be necessary to support repeated start transactions. Signed-off-by: Chris Babroski --- V1 -> V2: Removed default "Reviewed-by:" tags drivers/i2c/busses/i2c-mlxbf.c | 69 +++++++++++++++++++++------------- 1 file changed, 42 insertions(+), 27 deletions(-) diff --git a/drivers/i2c/busses/i2c-mlxbf.c b/drivers/i2c/busses/i2c-mlxbf.c index b3a73921ab69..8926dafa0270 100644 --- a/drivers/i2c/busses/i2c-mlxbf.c +++ b/drivers/i2c/busses/i2c-mlxbf.c @@ -196,6 +196,7 @@ =20 #define MLXBF_I2C_MASK_8 GENMASK(7, 0) #define MLXBF_I2C_MASK_16 GENMASK(15, 0) +#define MLXBF_I2C_MASK_32 GENMASK(31, 0) =20 #define MLXBF_I2C_MST_ADDR_OFFSET 0x200 =20 @@ -221,8 +222,7 @@ #define MLXBF_I2C_MASTER_STOP_BIT BIT(3) /* Control stop. */ =20 #define MLXBF_I2C_MASTER_ENABLE \ - (MLXBF_I2C_MASTER_LOCK_BIT | MLXBF_I2C_MASTER_BUSY_BIT | \ - MLXBF_I2C_MASTER_START_BIT | MLXBF_I2C_MASTER_STOP_BIT) + (MLXBF_I2C_MASTER_LOCK_BIT | MLXBF_I2C_MASTER_BUSY_BIT | MLXBF_I2C_MASTER= _START_BIT) =20 #define MLXBF_I2C_MASTER_ENABLE_WRITE \ (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_WRITE_BIT) @@ -336,6 +336,7 @@ enum { MLXBF_I2C_F_SMBUS_BLOCK =3D BIT(5), MLXBF_I2C_F_SMBUS_PEC =3D BIT(6), MLXBF_I2C_F_SMBUS_PROCESS_CALL =3D BIT(7), + MLXBF_I2C_F_WRITE_WITHOUT_STOP =3D BIT(8), }; =20 /* Mellanox BlueField chip type. */ @@ -694,16 +695,19 @@ static void mlxbf_i2c_smbus_read_data(struct mlxbf_i2= c_priv *priv, } =20 static int mlxbf_i2c_smbus_enable(struct mlxbf_i2c_priv *priv, u8 slave, - u8 len, u8 block_en, u8 pec_en, bool read) + u8 len, u8 block_en, u8 pec_en, bool read, bool no_stop) { - u32 command; + u32 command =3D 0; =20 /* Set Master GW control word. */ + if (!no_stop) + command |=3D MLXBF_I2C_MASTER_STOP_BIT; + if (read) { - command =3D MLXBF_I2C_MASTER_ENABLE_READ; + command |=3D MLXBF_I2C_MASTER_ENABLE_READ; command |=3D rol32(len, MLXBF_I2C_MASTER_READ_SHIFT); } else { - command =3D MLXBF_I2C_MASTER_ENABLE_WRITE; + command |=3D MLXBF_I2C_MASTER_ENABLE_WRITE; command |=3D rol32(len, MLXBF_I2C_MASTER_WRITE_SHIFT); } command |=3D rol32(slave, MLXBF_I2C_MASTER_SLV_ADDR_SHIFT); @@ -738,9 +742,11 @@ mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_pri= v *priv, u8 op_idx, data_idx, data_len, write_len, read_len; struct mlxbf_i2c_smbus_operation *operation; u8 read_en, write_en, block_en, pec_en; - u8 slave, flags, addr; + bool write_wo_stop =3D false; + u8 slave, addr; u8 *read_buf; int ret =3D 0; + u32 flags; =20 if (request->operation_cnt > MLXBF_I2C_SMBUS_MAX_OP_CNT) return -EINVAL; @@ -799,7 +805,16 @@ mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_pri= v *priv, memcpy(data_desc + data_idx, operation->buffer, operation->length); data_idx +=3D operation->length; + + /* + * The stop condition can be skipped when writing on the bus + * to implement a repeated start condition on the next read + * as required for several SMBus and I2C operations. + */ + if (flags & MLXBF_I2C_F_WRITE_WITHOUT_STOP) + write_wo_stop =3D true; } + /* * We assume that read operations are performed only once per * SMBus transaction. *TBD* protect this statement so it won't @@ -825,7 +840,7 @@ mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv= *priv, =20 if (write_en) { ret =3D mlxbf_i2c_smbus_enable(priv, slave, write_len, block_en, - pec_en, 0); + pec_en, 0, write_wo_stop); if (ret) goto out_unlock; } @@ -835,7 +850,7 @@ mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv= *priv, mlxbf_i2c_smbus_write_data(priv, (const u8 *)&addr, 1, MLXBF_I2C_MASTER_DATA_DESC_ADDR, true); ret =3D mlxbf_i2c_smbus_enable(priv, slave, read_len, block_en, - pec_en, 1); + pec_en, 1, false); if (!ret) { /* Get Master GW data descriptor. */ mlxbf_i2c_smbus_read_data(priv, data_desc, read_len + 1, @@ -940,6 +955,9 @@ mlxbf_i2c_smbus_i2c_block_func(struct mlxbf_i2c_smbus_r= equest *request, request->operation[0].flags |=3D pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; request->operation[0].buffer =3D command; =20 + if (read) + request->operation[0].flags |=3D MLXBF_I2C_F_WRITE_WITHOUT_STOP; + /* * As specified in the standard, the max number of bytes to read/write * per block operation is 32 bytes. In Golan code, the controller can @@ -1174,7 +1192,8 @@ static void mlxbf_i2c_set_timings(struct mlxbf_i2c_pr= iv *priv, MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_THIGH_MAX_TBUF); =20 - timer =3D timings->timeout; + timer =3D mlxbf_i2c_set_timer(priv, timings->timeout, false, + MLXBF_I2C_MASK_32, MLXBF_I2C_SHIFT_0); writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT); } =20 @@ -1184,11 +1203,7 @@ enum mlxbf_i2c_timings_config { MLXBF_I2C_TIMING_CONFIG_1000KHZ, }; =20 -/* - * Note that the mlxbf_i2c_timings->timeout value is not related to the - * bus frequency, it is impacted by the time it takes the driver to - * complete data transmission before transaction abort. - */ +/* Timing values are in nanoseconds */ static const struct mlxbf_i2c_timings mlxbf_i2c_timings[] =3D { [MLXBF_I2C_TIMING_CONFIG_100KHZ] =3D { .scl_high =3D 4810, @@ -1203,8 +1218,8 @@ static const struct mlxbf_i2c_timings mlxbf_i2c_timin= gs[] =3D { .scl_fall =3D 50, .hold_data =3D 300, .buf =3D 20000, - .thigh_max =3D 5000, - .timeout =3D 106500 + .thigh_max =3D 50000, + .timeout =3D 35000000 }, [MLXBF_I2C_TIMING_CONFIG_400KHZ] =3D { .scl_high =3D 1011, @@ -1219,24 +1234,24 @@ static const struct mlxbf_i2c_timings mlxbf_i2c_tim= ings[] =3D { .scl_fall =3D 50, .hold_data =3D 300, .buf =3D 20000, - .thigh_max =3D 5000, - .timeout =3D 106500 + .thigh_max =3D 50000, + .timeout =3D 35000000 }, [MLXBF_I2C_TIMING_CONFIG_1000KHZ] =3D { - .scl_high =3D 600, - .scl_low =3D 1300, + .scl_high =3D 383, + .scl_low =3D 460, .hold_start =3D 600, - .setup_start =3D 600, - .setup_stop =3D 600, - .setup_data =3D 100, + .setup_start =3D 260, + .setup_stop =3D 260, + .setup_data =3D 50, .sda_rise =3D 50, .sda_fall =3D 50, .scl_rise =3D 50, .scl_fall =3D 50, .hold_data =3D 300, - .buf =3D 20000, - .thigh_max =3D 5000, - .timeout =3D 106500 + .buf =3D 500, + .thigh_max =3D 50000, + .timeout =3D 35000000 } }; =20 base-commit: 0a9b9d17f3a781dea03baca01c835deaa07f7cc3 --=20 2.47.0