From nobody Sun Nov 24 06:49:50 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21FC51D043F for ; Tue, 19 Nov 2024 14:13:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732025608; cv=none; b=TH/Nhmi4iYApNl78c+WQMhXmY0n1J6IMUcLo2UKJXNYhDL8pYkXq+T3oCqdkSIcdgcRIOHF69u0SrGlSf6/BZEc/VDFSRkHlhTnW03v34fLc6en6vB+PG9Th7ZZENXc5Y3fyY4/8HDtAvla8BJYtKtHG0ZdSh2dSlfOEDmPb7uE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732025608; c=relaxed/simple; bh=bShgjmtC1riPo8REPGS9BSR/77kkLutmUEVL3JP0QBk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LlQD7RJjA+nvYVUpTwIfxPAdovEWXdYS01QWuDW04SNxPSk67sgIeEKbNH2Wdxg+RviOECqw6bXLXsVpeUOvHd1TYbOSLZs1AM5JbVDh2CeE8jH7yOxQohsH3NPWVgIKAw4Y9/8xlj6iheI+M9dZDidYcWaxl9o7twu45GiHVSE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ZAfgRnfE; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ZAfgRnfE" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1732025608; x=1763561608; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bShgjmtC1riPo8REPGS9BSR/77kkLutmUEVL3JP0QBk=; b=ZAfgRnfEg+ImKhiN7IXXrG/EKMET2P7TNErn3Fo+WBMf2s2NreGhc1O5 u+c6HamqGbOIqkdx6wZLFcLqTvm5kW6uwN2782h2+XGeLG1MBChh/XTCb CM4MJaFujXwro3tch6s4elkg2y9eIXwQD2yk4ho9dPFtLzDyG7bJ9o6+S f3lUCCkYWUcB9WfwzZeMtMR6H8ZxPsayBvoj7JOhhYyRS3JxbvkEKnAqh sTI4UT4sqK8g0dVki91pExUd1VGh9JRf7RUdOHI4neswmtGSp/m5wz7+f BuQkr0PkHLhlZdP5IpOp2BEQga/pj3QrEBTln5ZbkPHJn+088v9PyFxPG A==; X-CSE-ConnectionGUID: wcP7k9uLSJeS8f4UvqVAbw== X-CSE-MsgGUID: 4phWEJ1mTa+PktP2CxKsEw== X-IronPort-AV: E=McAfee;i="6700,10204,11261"; a="54526854" X-IronPort-AV: E=Sophos;i="6.12,166,1728975600"; d="scan'208";a="54526854" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Nov 2024 06:13:27 -0800 X-CSE-ConnectionGUID: 8FEGEV/PRruNvLc6y4m38Q== X-CSE-MsgGUID: TyZ/Ru18TROflQUq5vAWiA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,166,1728975600"; d="scan'208";a="94398691" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Nov 2024 06:13:22 -0800 From: Alexander Usyskin To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Rodrigo Vivi , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jani Nikula , Joonas Lahtinen , Tvrtko Ursulin Cc: Oren Weil , linux-mtd@lists.infradead.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Alexander Usyskin Subject: [PATCH v3 09/10] drm/xe/nvm: add on-die non-volatile memory device Date: Tue, 19 Nov 2024 16:01:11 +0200 Message-ID: <20241119140112.790720-10-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241119140112.790720-1-alexander.usyskin@intel.com> References: <20241119140112.790720-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable access to internal non-volatile memory on DGFX with GSC/CSC devices via a child device. The nvm child device is exposed via auxiliary bus. Reviewed-by: Rodrigo Vivi Signed-off-by: Alexander Usyskin --- drivers/gpu/drm/xe/Makefile | 1 + drivers/gpu/drm/xe/xe_device.c | 3 + drivers/gpu/drm/xe/xe_device_types.h | 7 ++ drivers/gpu/drm/xe/xe_nvm.c | 100 +++++++++++++++++++++++++++ drivers/gpu/drm/xe/xe_nvm.h | 15 ++++ drivers/gpu/drm/xe/xe_pci.c | 6 ++ 6 files changed, 132 insertions(+) create mode 100644 drivers/gpu/drm/xe/xe_nvm.c create mode 100644 drivers/gpu/drm/xe/xe_nvm.h diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index 95aabbb74a28..0fe5e0755e3f 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -94,6 +94,7 @@ xe-y +=3D xe_bb.o \ xe_ring_ops.o \ xe_sa.o \ xe_sched_job.o \ + xe_nvm.o \ xe_step.o \ xe_sync.o \ xe_tile.o \ diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c index 930bb2750e2e..9de2395efef5 100644 --- a/drivers/gpu/drm/xe/xe_device.c +++ b/drivers/gpu/drm/xe/xe_device.c @@ -50,6 +50,7 @@ #include "xe_pcode.h" #include "xe_pm.h" #include "xe_query.h" +#include "xe_nvm.h" #include "xe_sriov.h" #include "xe_tile.h" #include "xe_ttm_stolen_mgr.h" @@ -736,6 +737,7 @@ int xe_device_probe(struct xe_device *xe) goto err_fini_gt; } =20 + xe_nvm_init(xe); xe_heci_gsc_init(xe); =20 err =3D xe_oa_init(xe); @@ -804,6 +806,7 @@ void xe_device_remove(struct xe_device *xe) xe_oa_fini(xe); =20 xe_heci_gsc_fini(xe); + xe_nvm_fini(xe); =20 for_each_gt(gt, xe, id) xe_gt_remove(gt); diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_d= evice_types.h index 8592f1b02db1..c439e305fd6a 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -35,6 +35,8 @@ struct xe_ggtt; struct xe_pat_ops; =20 +struct intel_dg_nvm_dev; + #define XE_BO_INVALID_OFFSET LONG_MAX =20 #define GRAPHICS_VER(xe) ((xe)->info.graphics_verx100 / 100) @@ -329,6 +331,8 @@ struct xe_device { u8 has_heci_gscfi:1; /** @info.has_heci_cscfi: device has heci cscfi */ u8 has_heci_cscfi:1; + /** @info.has_gsc_nvm: device has gsc non-volatile memory */ + u8 has_gsc_nvm:1; /** @info.skip_guc_pc: Skip GuC based PM feature init */ u8 skip_guc_pc:1; /** @info.has_atomic_enable_pte_bit: Device has atomic enable PTE bit */ @@ -493,6 +497,9 @@ struct xe_device { /** @heci_gsc: graphics security controller */ struct xe_heci_gsc heci_gsc; =20 + /** @nvm: discrete graphics non-volatile memory */ + struct intel_dg_nvm_dev *nvm; + /** @oa: oa observation subsystem */ struct xe_oa oa; =20 diff --git a/drivers/gpu/drm/xe/xe_nvm.c b/drivers/gpu/drm/xe/xe_nvm.c new file mode 100644 index 000000000000..16383cbc9e1d --- /dev/null +++ b/drivers/gpu/drm/xe/xe_nvm.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2019-2024, Intel Corporation. All rights reserved. + */ + +#include +#include +#include "xe_device_types.h" +#include "xe_nvm.h" +#include "xe_sriov.h" + +#define GEN12_GUNIT_NVM_BASE 0x00102040 +#define GEN12_GUNIT_NVM_SIZE 0x80 +#define HECI_FW_STATUS_2_NVM_ACCESS_MODE BIT(3) + +static const struct intel_dg_nvm_region regions[INTEL_DG_NVM_REGIONS] =3D { + [0] =3D { .name =3D "DESCRIPTOR", }, + [2] =3D { .name =3D "GSC", }, + [11] =3D { .name =3D "OptionROM", }, + [12] =3D { .name =3D "DAM", }, +}; + +static void xe_nvm_release_dev(struct device *dev) +{ +} + +void xe_nvm_init(struct xe_device *xe) +{ + struct pci_dev *pdev =3D to_pci_dev(xe->drm.dev); + struct intel_dg_nvm_dev *nvm; + struct auxiliary_device *aux_dev; + int ret; + + if (!xe->info.has_gsc_nvm) + return; + + /* No access to internal NVM from VFs */ + if (IS_SRIOV_VF(xe)) + return; + + /* Nvm pointer should be NULL here */ + if (WARN_ON(xe->nvm)) + return; + + xe->nvm =3D kzalloc(sizeof(*nvm), GFP_KERNEL); + if (!xe->nvm) + return; + + nvm =3D xe->nvm; + + nvm->writeable_override =3D false; + nvm->bar.parent =3D &pdev->resource[0]; + nvm->bar.start =3D GEN12_GUNIT_NVM_BASE + pdev->resource[0].start; + nvm->bar.end =3D nvm->bar.start + GEN12_GUNIT_NVM_SIZE - 1; + nvm->bar.flags =3D IORESOURCE_MEM; + nvm->bar.desc =3D IORES_DESC_NONE; + nvm->regions =3D regions; + + aux_dev =3D &nvm->aux_dev; + + aux_dev->name =3D "nvm"; + aux_dev->id =3D (pci_domain_nr(pdev->bus) << 16) | + PCI_DEVID(pdev->bus->number, pdev->devfn); + aux_dev->dev.parent =3D &pdev->dev; + aux_dev->dev.release =3D xe_nvm_release_dev; + + ret =3D auxiliary_device_init(aux_dev); + if (ret) { + drm_err(&xe->drm, "xe-nvm aux init failed %d\n", ret); + return; + } + + ret =3D auxiliary_device_add(aux_dev); + if (ret) { + drm_err(&xe->drm, "xe-nvm aux add failed %d\n", ret); + auxiliary_device_uninit(aux_dev); + return; + } +} + +void xe_nvm_fini(struct xe_device *xe) +{ + struct intel_dg_nvm_dev *nvm =3D xe->nvm; + + if (!xe->info.has_gsc_nvm) + return; + + /* No access to internal NVM from VFs */ + if (IS_SRIOV_VF(xe)) + return; + + /* Nvm pointer should not be NULL here */ + if (WARN_ON(!nvm)) + return; + + auxiliary_device_delete(&nvm->aux_dev); + auxiliary_device_uninit(&nvm->aux_dev); + kfree(nvm); + xe->nvm =3D NULL; +} diff --git a/drivers/gpu/drm/xe/xe_nvm.h b/drivers/gpu/drm/xe/xe_nvm.h new file mode 100644 index 000000000000..068695447913 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_nvm.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2019-2024 Intel Corporation. All rights reserved. + */ + +#ifndef __XE_NVM_H__ +#define __XE_NVM_H__ + +struct xe_device; + +void xe_nvm_init(struct xe_device *xe); + +void xe_nvm_fini(struct xe_device *xe); + +#endif /* __XE_NVM_H__ */ diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index 64a8336ca437..dad9f10cf05b 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -60,6 +60,7 @@ struct xe_device_desc { u8 has_display:1; u8 has_heci_gscfi:1; u8 has_heci_cscfi:1; + u8 has_gsc_nvm:1; u8 has_llc:1; u8 has_mmio_ext:1; u8 has_sriov:1; @@ -282,6 +283,7 @@ static const struct xe_device_desc dg1_desc =3D { PLATFORM(DG1), .has_display =3D true, .has_heci_gscfi =3D 1, + .has_gsc_nvm =3D 1, .require_force_probe =3D true, }; =20 @@ -293,6 +295,7 @@ static const u16 dg2_g12_ids[] =3D { XE_DG2_G12_IDS(NOP= ), 0 }; DGFX_FEATURES, \ PLATFORM(DG2), \ .has_heci_gscfi =3D 1, \ + .has_gsc_nvm =3D 1, \ .subplatforms =3D (const struct xe_subplatform_desc[]) { \ { XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \ { XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \ @@ -324,6 +327,7 @@ static const __maybe_unused struct xe_device_desc pvc_d= esc =3D { PLATFORM(PVC), .has_display =3D false, .has_heci_gscfi =3D 1, + .has_gsc_nvm =3D 1, .require_force_probe =3D true, }; =20 @@ -344,6 +348,7 @@ static const struct xe_device_desc bmg_desc =3D { PLATFORM(BATTLEMAGE), .has_display =3D true, .has_heci_cscfi =3D 1, + .has_gsc_nvm =3D 1, }; =20 static const struct xe_device_desc ptl_desc =3D { @@ -623,6 +628,7 @@ static int xe_info_init_early(struct xe_device *xe, xe->info.is_dgfx =3D desc->is_dgfx; xe->info.has_heci_gscfi =3D desc->has_heci_gscfi; xe->info.has_heci_cscfi =3D desc->has_heci_cscfi; + xe->info.has_gsc_nvm =3D desc->has_gsc_nvm; xe->info.has_llc =3D desc->has_llc; xe->info.has_mmio_ext =3D desc->has_mmio_ext; xe->info.has_sriov =3D desc->has_sriov; --=20 2.43.0