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The 'broadcast' register space is present only in chipsets that have multiple instances of LLCC IP. Since IPQ5424 has only one instance, both the LLCC and LLCC_BROADCAST points to the same register space. Hence, allow only '1' reg & reg-names entry for IPQ5424. Reviewed-by: Rob Herring (Arm) Signed-off-by: Varadarajan Narayanan --- v3: Rebase to ToT v2: Add Reviewed-by --- .../devicetree/bindings/cache/qcom,llcc.yaml | 20 +++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Docum= entation/devicetree/bindings/cache/qcom,llcc.yaml index 03b1941eaa33..612de26b7064 100644 --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml @@ -23,6 +23,7 @@ properties: - qcom,qcs615-llcc - qcom,qcs8300-llcc - qcom,qdu1000-llcc + - qcom,ipq5424-llcc - qcom,sa8775p-llcc - qcom,sar1130p-llcc - qcom,sar2130p-llcc @@ -42,11 +43,11 @@ properties: - qcom,x1e80100-llcc =20 reg: - minItems: 2 + minItems: 1 maxItems: 10 =20 reg-names: - minItems: 2 + minItems: 1 maxItems: 10 =20 interrupts: @@ -66,6 +67,21 @@ required: - reg-names =20 allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5424-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + reg-names: + items: + - const: llcc0_base + - if: properties: compatible: --=20 2.34.1 From nobody Sat Nov 23 14:26:37 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA29A150981; 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charset="utf-8" The 'broadcast' register space is present only in chipsets that have multiple instances of LLCC IP. Since IPQ5424 has only one instance, both the LLCC and LLCC_BROADCAST points to the same register space. Signed-off-by: Varadarajan Narayanan --- v3: Rebase to ToT Remove 'need_llcc_cfg =3D true' v2: Use 'true/false' instead of '1/0' for boolean variables. Add 'no_broadcast_register' to qcom_llcc_config structure to identify SoC without LLCC_BROADCAST register space instead of using 'num_banks'. --- drivers/soc/qcom/llcc-qcom.c | 57 ++++++++++++++++++++++++++++++++++-- 1 file changed, 55 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 32c3bc887cef..106f2619277a 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -142,6 +142,7 @@ struct qcom_llcc_config { bool skip_llcc_cfg; bool no_edac; bool irq_configured; + bool no_broadcast_register; }; =20 struct qcom_sct_config { @@ -154,6 +155,38 @@ enum llcc_reg_offset { LLCC_COMMON_STATUS0, }; =20 +static const struct llcc_slice_config ipq5424_data[] =3D { + { + .usecase_id =3D LLCC_CPUSS, + .slice_id =3D 1, + .max_cap =3D 768, + .priority =3D 1, + .bonus_ways =3D 0xFFFF, + .retain_on_pc =3D true, + .activate_on_init =3D true, + .write_scid_cacheable_en =3D true, + .stale_en =3D true, + .stale_cap_en =3D true, + .alloc_oneway_en =3D true, + .ovcap_en =3D true, + .ovcap_prio =3D true, + .vict_prio =3D true, + }, + { + .usecase_id =3D LLCC_VIDSC0, + .slice_id =3D 2, + .max_cap =3D 256, + .priority =3D 2, + .fixed_size =3D true, + .bonus_ways =3D 0xF000, + .retain_on_pc =3D true, + .activate_on_init =3D true, + .write_scid_cacheable_en =3D true, + .stale_en =3D true, + .stale_cap_en =3D true, + }, +}; + static const struct llcc_slice_config sa8775p_data[] =3D { { .usecase_id =3D LLCC_CPUSS, @@ -3185,6 +3218,16 @@ static const struct qcom_llcc_config qdu1000_cfg[] = =3D { }, }; =20 +static const struct qcom_llcc_config ipq5424_cfg[] =3D { + { + .sct_data =3D ipq5424_data, + .size =3D ARRAY_SIZE(ipq5424_data), + .reg_offset =3D llcc_v2_1_reg_offset, + .edac_reg_offset =3D &llcc_v2_1_edac_reg_offset, + .no_broadcast_register =3D true, + }, +}; + static const struct qcom_llcc_config sa8775p_cfg[] =3D { { .sct_data =3D sa8775p_data, @@ -3360,6 +3403,11 @@ static const struct qcom_sct_config qdu1000_cfgs =3D= { .num_config =3D ARRAY_SIZE(qdu1000_cfg), }; =20 +static const struct qcom_sct_config ipq5424_cfgs =3D { + .llcc_config =3D ipq5424_cfg, + .num_config =3D ARRAY_SIZE(ipq5424_cfg), +}; + static const struct qcom_sct_config sa8775p_cfgs =3D { .llcc_config =3D sa8775p_cfg, .num_config =3D ARRAY_SIZE(sa8775p_cfg), @@ -3957,8 +4005,12 @@ static int qcom_llcc_probe(struct platform_device *p= dev) =20 drv_data->bcast_regmap =3D qcom_llcc_init_mmio(pdev, i, "llcc_broadcast_b= ase"); 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charset="utf-8" Add a DT node for Last level cache (aka. system cache) controller which provides control over the last level cache present on IPQ5424 SoCs. Reviewed-by: Konrad Dybcio Signed-off-by: Varadarajan Narayanan --- v3: Rebase to ToT v2: Add Reviewed-by --- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qc= om/ipq5424.dtsi index 5e219f900412..bdb73f8c09f9 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -145,6 +145,13 @@ soc@0 { #size-cells =3D <2>; ranges =3D <0 0 0 0 0x10 0>; =20 + system-cache-controller@800000 { + compatible =3D "qcom,ipq5424-llcc"; + reg =3D <0 0x00800000 0 0x200000>; + reg-names =3D "llcc0_base"; + interrupts =3D ; + }; + tlmm: pinctrl@1000000 { compatible =3D "qcom,ipq5424-tlmm"; reg =3D <0 0x01000000 0 0x300000>; --=20 2.34.1