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Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 110 +++++++++++++++++++++++++++ 1 file changed, 110 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qco= m/qcs615.dtsi index 590beb37f441..e676e76a337e 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -397,6 +397,11 @@ qfprom: efuse@780000 { reg =3D <0x0 0x00780000 0x0 0x7000>; #address-cells =3D <1>; #size-cells =3D <1>; + + qusb2_hstx_trim: hstx-trim@1f8 { + reg =3D <0x1fb 0x1>; + bits =3D <1 4>; + }; }; =20 qupv3_id_0: geniqup@8c0000 { @@ -758,6 +763,111 @@ rpmhpd_opp_turbo_l1: opp-9 { }; }; }; + + usb_1_hsphy: phy@88e2000 { + compatible =3D "qcom,qcs615-qusb2-phy"; + reg =3D <0x0 0x88e2000 0x0 0x180>; + + clocks =3D <&gcc GCC_AHB2PHY_WEST_CLK>, <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "cfg_ahb", "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_PRIM_BCR>; + nvmem-cells =3D <&qusb2_hstx_trim>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_qmpphy: phy@88e6000 { + compatible =3D "qcom,qcs615-qmp-usb3-phy"; + reg =3D <0x0 0x88e6000 0x0 0x1000>; + + clocks =3D <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_AHB2PHY_WEST_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names =3D "aux", + "ref", + "cfg_ahb", + "pipe"; + + resets =3D <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; + reset-names =3D "phy", "phy_phy"; + + qcom,tcsr-reg =3D <&tcsr 0xb244>; + + clock-output-names =3D "usb3_phy_pipe_clk_src"; + #clock-cells =3D <0>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_1: usb@a6f8800 { + compatible =3D "qcom,qcs615-dwc3", "qcom,dwc3"; + reg =3D <0 0x0a6f8800 0 0x400>; + + clocks =3D <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks =3D <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates =3D <19200000>, <200000000>; + + interrupts-extended =3D <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 9 IRQ_TYPE_EDGE_BOTH>, + <&pdc 8 IRQ_TYPE_EDGE_BOTH>, + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains =3D <&gcc USB30_PRIM_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + resets =3D <&gcc GCC_USB30_PRIM_BCR>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + usb_1_dwc3: usb@a600000 { + compatible =3D "snps,dwc3"; + reg =3D <0 0x0a600000 0 0xcd00>; + + iommus =3D <&apps_smmu 0x140 0x0>; + interrupts =3D ; + + phys =3D <&usb_1_hsphy>, <&usb_qmpphy>; + phy-names =3D "usb2-phy", "usb3-phy"; + + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold =3D /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + }; + }; }; =20 arch_timer: timer { --=20 2.34.1 From nobody Sat Nov 23 15:00:44 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EBCBC15535A; Tue, 19 Nov 2024 05:29:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731994164; cv=none; b=RR89GFSPA41tK7xYAIp+Sajbw07xq7f1p5VFw5JYHpZDbr4ZD0pWb1hqF6grBbsvmqnhZTXk0cDftVzCUbcaLd/+KWoIKXkf+WPXO6p7Zg4rM3YSALNZdoqELQKHbN3Fr0v9KN8yXBhujQKhbxa8tq+J9aAdUUTDd+2jjiudSs8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731994164; c=relaxed/simple; bh=iGEhnrk1IEyRY3tpKrXKDgHoMmapZ/Hr9mlnQeY4lAc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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charset="utf-8" Enable primary USB controller on QCS615 Ride platform. The primary USB controller is made "peripheral", as this is intended to be connected to a host for debugging use cases. For using the controller in host mode, changing the dr_mode and adding appropriate pinctrl nodes to provide vbus would be sufficient. Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts= /qcom/qcs615-ride.dts index ee6cab3924a6..b647c87b030b 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -214,6 +214,29 @@ &uart0 { status =3D "okay"; }; =20 +&usb_1_hsphy { + vdd-supply =3D <&vreg_l5a>; + vdda-pll-supply =3D <&vreg_l2a>; + vdda-phy-dpdm-supply =3D <&vreg_l13a>; + + status =3D "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply =3D <&vreg_l5a>; + vdda-pll-supply =3D <&vreg_l12a>; + + status =3D "okay"; +}; + +&usb_1 { + status =3D "okay"; +}; + +&usb_1_dwc3 { + dr_mode =3D "peripheral"; +}; + &watchdog { clocks =3D <&sleep_clk>; }; --=20 2.34.1