From nobody Sat Nov 23 17:42:02 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3621513D244; Tue, 19 Nov 2024 02:22:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731982926; cv=none; b=gjBaatzrZIu0Kr3g9tDtaRn+nRmtJJ1bL0+IInrEmXtUvXv3zt4PfjtLvQ0cvWM05HqTWi6vm0uQGImbSxiJQAb3oAyIj3KmjvV4QPiEiMMxb8XOcvtPeHnXigQlFi/2l5VtH1UwuOFhYakZCijBmvTieubn38VSvCv1yj/58bE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731982926; c=relaxed/simple; bh=w/pdutY/FIZTPO+uhXTgtw1SXA4nMfeUSr72HMftunU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mWE7XlzlxC1Sp19Ckb6i3FlrbDXVVidm7/c2BQwQSpQGlOpTsRtLce4ME85XdhGZKkWosDaTB7P1j3cK4WWFRyUEVTy0r5Qb4HGBSFfu+QKpJ2q+TyuhOBSAsv+v6HvR0nqEQzTZWxOYSSGVOrbNO6HQhh/rVv8andbbBz6QSHI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Bdd4pRNh; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Bdd4pRNh" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4AIGGkV3009961; Tue, 19 Nov 2024 02:21:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= lyrr/brkOmB2Om5Xl4Mis0tEgeQJVQ3MBvdgLOTQlks=; b=Bdd4pRNhMJDy4bjo slmXaZCuHguDgBYFoVQQ3MLhg/kKWa5CjnC4IE/VSylc09I+MyIn8QFAPmP/MdzV dFtxytnDusPRcUE4rf3pc59fhGtbb4IvD70FX+rHu5gHWhcq9JJM0S9/I7d9LQAg ebu7xPmPa3GfK6+g/DB4d9ulLah+tLKi/NqhToZzZ1VUHKAZ5rfsI5+gZ5RAXcEl BxYgzhJyb25jl4hCyJCR8ZVsmt7f0RVgyccFdtkujckFdsiZMTogLXVEU255W1Nl jY46Qa/lB9gi5rpikOk+joJbgL5ZsvUU5RjYgPV/S+RL7qSc+Edh9tw8eC0Ki0Cs n3WzCQ== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4308y9157f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Nov 2024 02:21:41 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AJ2LeAp016740 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Nov 2024 02:21:40 GMT Received: from liuxin-gv.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 18 Nov 2024 18:21:34 -0800 From: Xin Liu To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Bjorn Andersson , Konrad Dybcio CC: Vinod Koul , Kishon Vijay Abraham I , Alim Akhtar , Avri Altman , Bart Van Assche , Andy Gross , , , , , , , , , Subject: [PATCH v2 2/3] arm64: dts: qcom: qcs615: add UFS node Date: Tue, 19 Nov 2024 10:20:49 +0800 Message-ID: <20241119022050.2995511-3-quic_liuxin@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241119022050.2995511-1-quic_liuxin@quicinc.com> References: <20241119022050.2995511-1-quic_liuxin@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 6HpaF34wxmhWupo3uFRdpWj3ItxYWvbs X-Proofpoint-GUID: 6HpaF34wxmhWupo3uFRdpWj3ItxYWvbs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 mlxlogscore=999 clxscore=1015 suspectscore=0 malwarescore=0 priorityscore=1501 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411190019 Content-Type: text/plain; charset="utf-8" From: Sayali Lokhande Add the UFS Host Controller node and its PHY for QCS615 SoC. Signed-off-by: Sayali Lokhande Co-developed-by: Xin Liu Signed-off-by: Xin Liu --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 112 +++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qco= m/qcs615.dtsi index 590beb37f441..ceceafb2e71f 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -458,6 +458,118 @@ mmss_noc: interconnect@1740000 { qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + ufs_mem_hc: ufshc@1d84000 { + compatible =3D "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; + reg =3D <0x0 0x01d84000 0x0 0x3000>, <0x0 0x01d90000 0x0 0x8000>; + reg-names =3D "std", "ice"; + + interrupts =3D ; + + clocks =3D <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; + clock-names =3D "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + + resets =3D <&gcc GCC_UFS_PHY_BCR>; + reset-names =3D "rst"; + + operating-points-v2 =3D <&ufs_opp_table>; + interconnects =3D <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "ufs-ddr", + "cpu-ufs"; + + power-domains =3D <&gcc UFS_PHY_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + iommus =3D <&apps_smmu 0x300 0x0>; + dma-coherent; + + lanes-per-direction =3D <1>; + + phys =3D <&ufs_mem_phy>; + phy-names =3D "ufsphy"; + + #reset-cells =3D <1>; + + status =3D "disabled"; + + ufs_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-50000000 { + opp-hz =3D /bits/ 64 <50000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <37500000>, + /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <75000000>, + /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <150000000>, + /bits/ 64 <300000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + ufs_mem_phy: phy@1d87000 { + compatible =3D "qcom,qcs615-qmp-ufs-phy", "qcom,sm6115-qmp-ufs-phy"; + reg =3D <0x0 0x01d87000 0x0 0xe00>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>; + clock-names =3D "ref", + "ref_aux", + "qref"; + + power-domains =3D <&gcc UFS_PHY_GDSC>; + + resets =3D <&ufs_mem_hc 0>; + reset-names =3D "ufsphy"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible =3D "qcom,tcsr-mutex"; reg =3D <0x0 0x01f40000 0x0 0x20000>; --=20 2.34.1