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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Nov 2024 00:39:26.6902 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 23c2dff0-7c5d-4006-934d-08dd08329f24 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.12];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709B.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9103 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rename the protocol error struct from struct cper_sec_prot_err to struct cxl_cper_sec_prot_err and cper_print_prot_err() to cxl_cper_print_prot_err() to maintain naming consistency. No functional changes. Signed-off-by: Smita Koralahalli --- drivers/firmware/efi/cper.c | 4 ++-- drivers/firmware/efi/cper_cxl.c | 3 ++- drivers/firmware/efi/cper_cxl.h | 5 +++-- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/firmware/efi/cper.c b/drivers/firmware/efi/cper.c index b69e68ef3f02..8e5762f7ef2e 100644 --- a/drivers/firmware/efi/cper.c +++ b/drivers/firmware/efi/cper.c @@ -624,11 +624,11 @@ cper_estatus_print_section(const char *pfx, struct ac= pi_hest_generic_data *gdata else goto err_section_too_small; } else if (guid_equal(sec_type, &CPER_SEC_CXL_PROT_ERR)) { - struct cper_sec_prot_err *prot_err =3D acpi_hest_get_payload(gdata); + struct cxl_cper_sec_prot_err *prot_err =3D acpi_hest_get_payload(gdata); =20 printk("%ssection_type: CXL Protocol Error\n", newpfx); if (gdata->error_data_length >=3D sizeof(*prot_err)) - cper_print_prot_err(newpfx, prot_err); + cxl_cper_print_prot_err(newpfx, prot_err); else goto err_section_too_small; } else { diff --git a/drivers/firmware/efi/cper_cxl.c b/drivers/firmware/efi/cper_cx= l.c index a55771b99a97..cbaabcb7382d 100644 --- a/drivers/firmware/efi/cper_cxl.c +++ b/drivers/firmware/efi/cper_cxl.c @@ -55,7 +55,8 @@ enum { USP, /* CXL Upstream Switch Port */ }; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Nov 2024 00:39:27.5808 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 35124d49-8458-4d66-db29-08dd08329fae X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.12];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709B.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8977 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation to add tracepoint support, move protocol error UUID definition to a common location, Also, make struct CXL RAS capability, cxl_cper_sec_prot_err and CPER validation flags global for use across different modules. Signed-off-by: Smita Koralahalli --- drivers/firmware/efi/cper.c | 1 + drivers/firmware/efi/cper_cxl.c | 35 +-------------- drivers/firmware/efi/cper_cxl.h | 51 --------------------- include/cxl/event.h | 80 +++++++++++++++++++++++++++++++++ include/linux/cper.h | 4 ++ 5 files changed, 86 insertions(+), 85 deletions(-) diff --git a/drivers/firmware/efi/cper.c b/drivers/firmware/efi/cper.c index 8e5762f7ef2e..ae1953e2b214 100644 --- a/drivers/firmware/efi/cper.c +++ b/drivers/firmware/efi/cper.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "cper_cxl.h" =20 /* diff --git a/drivers/firmware/efi/cper_cxl.c b/drivers/firmware/efi/cper_cx= l.c index cbaabcb7382d..64c0dd27be6e 100644 --- a/drivers/firmware/efi/cper_cxl.c +++ b/drivers/firmware/efi/cper_cxl.c @@ -8,27 +8,9 @@ */ =20 #include +#include #include "cper_cxl.h" =20 -#define PROT_ERR_VALID_AGENT_TYPE BIT_ULL(0) -#define PROT_ERR_VALID_AGENT_ADDRESS BIT_ULL(1) -#define PROT_ERR_VALID_DEVICE_ID BIT_ULL(2) -#define PROT_ERR_VALID_SERIAL_NUMBER BIT_ULL(3) -#define PROT_ERR_VALID_CAPABILITY BIT_ULL(4) -#define PROT_ERR_VALID_DVSEC BIT_ULL(5) -#define PROT_ERR_VALID_ERROR_LOG BIT_ULL(6) - -/* CXL RAS Capability Structure, CXL v3.0 sec 8.2.4.16 */ -struct cxl_ras_capability_regs { - u32 uncor_status; - u32 uncor_mask; - u32 uncor_severity; - u32 cor_status; - u32 cor_mask; - u32 cap_control; - u32 header_log[16]; -}; - static const char * const prot_err_agent_type_strs[] =3D { "Restricted CXL Device", "Restricted CXL Host Downstream Port", @@ -40,21 +22,6 @@ static const char * const prot_err_agent_type_strs[] =3D= { "CXL Upstream Switch Port", }; =20 -/* - * The layout of the enumeration and the values matches CXL Agent Type - * field in the UEFI 2.10 Section N.2.13, - */ -enum { - RCD, /* Restricted CXL Device */ - RCH_DP, /* Restricted CXL Host Downstream Port */ - DEVICE, /* CXL Device */ - LD, /* CXL Logical Device */ - FMLD, /* CXL Fabric Manager managed Logical Device */ - RP, /* CXL Root Port */ - DSP, /* CXL Downstream Switch Port */ - USP, /* CXL Upstream Switch Port */ -}; - void cxl_cper_print_prot_err(const char *pfx, const struct cxl_cper_sec_prot_err *prot_err) { diff --git a/drivers/firmware/efi/cper_cxl.h b/drivers/firmware/efi/cper_cx= l.h index 0e3ab0ba17c3..5ce1401ee17a 100644 --- a/drivers/firmware/efi/cper_cxl.h +++ b/drivers/firmware/efi/cper_cxl.h @@ -10,57 +10,6 @@ #ifndef LINUX_CPER_CXL_H #define LINUX_CPER_CXL_H =20 -/* CXL Protocol Error Section */ -#define CPER_SEC_CXL_PROT_ERR \ - GUID_INIT(0x80B9EFB4, 0x52B5, 0x4DE3, 0xA7, 0x77, 0x68, 0x78, \ - 0x4B, 0x77, 0x10, 0x48) - -#pragma pack(1) - -/* Compute Express Link Protocol Error Section, UEFI v2.10 sec N.2.13 */ -struct cxl_cper_sec_prot_err { - u64 valid_bits; - u8 agent_type; - u8 reserved[7]; - - /* - * Except for RCH Downstream Port, all the remaining CXL Agent - * types are uniquely identified by the PCIe compatible SBDF number. - */ - union { - u64 rcrb_base_addr; - struct { - u8 function; - u8 device; - u8 bus; - u16 segment; - u8 reserved_1[3]; - }; - } agent_addr; - - struct { - u16 vendor_id; - u16 device_id; - u16 subsystem_vendor_id; - u16 subsystem_id; - u8 class_code[2]; - u16 slot; - u8 reserved_1[4]; - } device_id; - - struct { - u32 lower_dw; - u32 upper_dw; - } dev_serial_num; - - u8 capability[60]; - u16 dvsec_len; - u16 err_len; - u8 reserved_2[4]; -}; - -#pragma pack() - void cxl_cper_print_prot_err(const char *pfx, const struct cxl_cper_sec_prot_err *prot_err); =20 diff --git a/include/cxl/event.h b/include/cxl/event.h index 0bea1afbd747..66d85fc87701 100644 --- a/include/cxl/event.h +++ b/include/cxl/event.h @@ -152,6 +152,86 @@ struct cxl_cper_work_data { struct cxl_cper_event_rec rec; }; =20 +#define PROT_ERR_VALID_AGENT_TYPE BIT_ULL(0) +#define PROT_ERR_VALID_AGENT_ADDRESS BIT_ULL(1) +#define PROT_ERR_VALID_DEVICE_ID BIT_ULL(2) +#define PROT_ERR_VALID_SERIAL_NUMBER BIT_ULL(3) +#define PROT_ERR_VALID_CAPABILITY BIT_ULL(4) +#define PROT_ERR_VALID_DVSEC BIT_ULL(5) +#define PROT_ERR_VALID_ERROR_LOG BIT_ULL(6) + +/* + * The layout of the enumeration and the values matches CXL Agent Type + * field in the UEFI 2.10 Section N.2.13, + */ +enum { + RCD, /* Restricted CXL Device */ + RCH_DP, /* Restricted CXL Host Downstream Port */ + DEVICE, /* CXL Device */ + LD, /* CXL Logical Device */ + FMLD, /* CXL Fabric Manager managed Logical Device */ + RP, /* CXL Root Port */ + DSP, /* CXL Downstream Switch Port */ + USP, /* CXL Upstream Switch Port */ +}; + +#pragma pack(1) + +/* Compute Express Link Protocol Error Section, UEFI v2.10 sec N.2.13 */ +struct cxl_cper_sec_prot_err { + u64 valid_bits; + u8 agent_type; + u8 reserved[7]; + + /* + * Except for RCH Downstream Port, all the remaining CXL Agent + * types are uniquely identified by the PCIe compatible SBDF number. + */ + union { + u64 rcrb_base_addr; + struct { + u8 function; + u8 device; + u8 bus; + u16 segment; + u8 reserved_1[3]; + }; + } agent_addr; + + struct { + u16 vendor_id; + u16 device_id; + u16 subsystem_vendor_id; + u16 subsystem_id; + u8 class_code[2]; + u16 slot; + u8 reserved_1[4]; + } device_id; + + struct { + u32 lower_dw; + u32 upper_dw; + } dev_serial_num; + + u8 capability[60]; + u16 dvsec_len; + u16 err_len; + u8 reserved_2[4]; +}; + +#pragma pack() + +/* CXL RAS Capability Structure, CXL v3.0 sec 8.2.4.16 */ +struct cxl_ras_capability_regs { + u32 uncor_status; + u32 uncor_mask; + u32 uncor_severity; + u32 cor_status; + u32 cor_mask; + u32 cap_control; + u32 header_log[16]; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Nov 2024 00:39:28.4089 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5f2c1f74-866e-4b8d-d4f3-08dd0832a02a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.12];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709B.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8763 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move the declaration of cxl_cper_print_prot_err() to include/linux/cper.h to avoid maintaining a separate header file just for this function declaration. Remove drivers/firmware/efi/cper_cxl.h as its contents have been reorganized. Eliminate its corresponding #include directives from source files that previously included it, since the header file has been removed. No functional changes. Signed-off-by: Smita Koralahalli --- drivers/firmware/efi/cper.c | 1 - drivers/firmware/efi/cper_cxl.c | 1 - drivers/firmware/efi/cper_cxl.h | 16 ---------------- include/linux/cper.h | 4 ++++ 4 files changed, 4 insertions(+), 18 deletions(-) delete mode 100644 drivers/firmware/efi/cper_cxl.h diff --git a/drivers/firmware/efi/cper.c b/drivers/firmware/efi/cper.c index ae1953e2b214..928409199a1a 100644 --- a/drivers/firmware/efi/cper.c +++ b/drivers/firmware/efi/cper.c @@ -25,7 +25,6 @@ #include #include #include -#include "cper_cxl.h" =20 /* * CPER record ID need to be unique even after reboot, because record diff --git a/drivers/firmware/efi/cper_cxl.c b/drivers/firmware/efi/cper_cx= l.c index 64c0dd27be6e..8a7667faf953 100644 --- a/drivers/firmware/efi/cper_cxl.c +++ b/drivers/firmware/efi/cper_cxl.c @@ -9,7 +9,6 @@ =20 #include #include -#include "cper_cxl.h" =20 static const char * const prot_err_agent_type_strs[] =3D { "Restricted CXL Device", diff --git a/drivers/firmware/efi/cper_cxl.h b/drivers/firmware/efi/cper_cx= l.h deleted file mode 100644 index 5ce1401ee17a..000000000000 --- a/drivers/firmware/efi/cper_cxl.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * UEFI Common Platform Error Record (CPER) support for CXL Section. - * - * Copyright (C) 2022 Advanced Micro Devices, Inc. - * - * Author: Smita Koralahalli - */ - -#ifndef LINUX_CPER_CXL_H -#define LINUX_CPER_CXL_H - -void cxl_cper_print_prot_err(const char *pfx, - const struct cxl_cper_sec_prot_err *prot_err); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Nov 2024 00:39:28.9558 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 07205ac9-2fe9-48f0-a968-08dd0832a080 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.12];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709B.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8877 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rename cxl_cper_register_work() to cxl_cper_register_event_work() to better reflect its purpose of registering CXL Component Events based work within the CXL subsystem. This rename prepares the codebase to support future patches where cxl_cper_register_work() will accept generic pointers for Protocol Error workqueue integration. Signed-off-by: Smita Koralahalli --- drivers/acpi/apei/ghes.c | 8 ++++---- drivers/cxl/pci.c | 4 ++-- include/cxl/event.h | 8 ++++---- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index ada93cfde9ba..082c409707ba 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -717,7 +717,7 @@ static void cxl_cper_post_event(enum cxl_event_type eve= nt_type, schedule_work(cxl_cper_work); } =20 -int cxl_cper_register_work(struct work_struct *work) +int cxl_cper_register_event_work(struct work_struct *work) { if (cxl_cper_work) return -EINVAL; @@ -726,9 +726,9 @@ int cxl_cper_register_work(struct work_struct *work) cxl_cper_work =3D work; return 0; } -EXPORT_SYMBOL_NS_GPL(cxl_cper_register_work, CXL); +EXPORT_SYMBOL_NS_GPL(cxl_cper_register_event_work, CXL); =20 -int cxl_cper_unregister_work(struct work_struct *work) +int cxl_cper_unregister_event_work(struct work_struct *work) { if (cxl_cper_work !=3D work) return -EINVAL; @@ -737,7 +737,7 @@ int cxl_cper_unregister_work(struct work_struct *work) cxl_cper_work =3D NULL; return 0; } -EXPORT_SYMBOL_NS_GPL(cxl_cper_unregister_work, CXL); +EXPORT_SYMBOL_NS_GPL(cxl_cper_unregister_event_work, CXL); =20 int cxl_cper_kfifo_get(struct cxl_cper_work_data *wd) { diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 188412d45e0d..88a14d7baa65 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -1075,7 +1075,7 @@ static int __init cxl_pci_driver_init(void) if (rc) return rc; =20 - rc =3D cxl_cper_register_work(&cxl_cper_work); + rc =3D cxl_cper_register_event_work(&cxl_cper_work); if (rc) pci_unregister_driver(&cxl_pci_driver); =20 @@ -1084,7 +1084,7 @@ static int __init cxl_pci_driver_init(void) =20 static void __exit cxl_pci_driver_exit(void) { - cxl_cper_unregister_work(&cxl_cper_work); + cxl_cper_unregister_event_work(&cxl_cper_work); cancel_work_sync(&cxl_cper_work); pci_unregister_driver(&cxl_pci_driver); } diff --git a/include/cxl/event.h b/include/cxl/event.h index 66d85fc87701..992568b35455 100644 --- a/include/cxl/event.h +++ b/include/cxl/event.h @@ -233,16 +233,16 @@ struct cxl_ras_capability_regs { }; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Nov 2024 00:39:29.4089 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8bd0046d-6f5c-46de-6b25-08dd0832a0c3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.12];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709B.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5769 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refactor the work registration and unregistration functions in GHES to enable reuse across different workqueues. This update lays the foundation for integrating additional workqueues in the CXL subsystem for better modularity and code reuse. Signed-off-by: Smita Koralahalli --- drivers/acpi/apei/ghes.c | 34 +++++++++++++++++++++++++--------- 1 file changed, 25 insertions(+), 9 deletions(-) diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index 082c409707ba..62ffe6eb5503 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -717,26 +717,42 @@ static void cxl_cper_post_event(enum cxl_event_type e= vent_type, schedule_work(cxl_cper_work); } =20 -int cxl_cper_register_event_work(struct work_struct *work) +static int cxl_cper_register_work(struct work_struct **work_ptr, + spinlock_t *lock, + struct work_struct *work) { - if (cxl_cper_work) + if (*work_ptr) return -EINVAL; =20 - guard(spinlock)(&cxl_cper_work_lock); - cxl_cper_work =3D work; + guard(spinlock)(lock); + *work_ptr =3D work; return 0; } -EXPORT_SYMBOL_NS_GPL(cxl_cper_register_event_work, CXL); =20 -int cxl_cper_unregister_event_work(struct work_struct *work) +static int cxl_cper_unregister_work(struct work_struct **work_ptr, + spinlock_t *lock, + struct work_struct *work) { - if (cxl_cper_work !=3D work) + if (*work_ptr !=3D work) return -EINVAL; =20 - guard(spinlock)(&cxl_cper_work_lock); - cxl_cper_work =3D NULL; + guard(spinlock)(lock); + *work_ptr =3D NULL; return 0; } + +int cxl_cper_register_event_work(struct work_struct *work) +{ + return cxl_cper_register_work(&cxl_cper_work, &cxl_cper_work_lock, + work); +} +EXPORT_SYMBOL_NS_GPL(cxl_cper_register_event_work, CXL); + +int cxl_cper_unregister_event_work(struct work_struct *work) +{ + return cxl_cper_unregister_work(&cxl_cper_work, &cxl_cper_work_lock, + work); +} EXPORT_SYMBOL_NS_GPL(cxl_cper_unregister_event_work, CXL); =20 int cxl_cper_kfifo_get(struct cxl_cper_work_data *wd) --=20 2.17.1 From nobody Sun Nov 24 02:49:35 2024 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2053.outbound.protection.outlook.com [40.107.93.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF1C4137750; Tue, 19 Nov 2024 00:39:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Nov 2024 00:39:30.6901 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4501131e-541e-4fe5-4da3-08dd0832a189 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.12];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709B.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8652 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support in GHES to detect and process CXL CPER Protocol errors, as defined in UEFI v2.10, section N.2.13. Define struct cxl_cper_prot_err_work_data to cache CXL protocol error information, including RAS capabilities and severity, for further handling. These cached CXL CPER records will later be processed by workqueues within the CXL subsystem. Signed-off-by: Smita Koralahalli --- drivers/acpi/apei/ghes.c | 52 ++++++++++++++++++++++++++++++++++++++++ include/cxl/event.h | 6 +++++ 2 files changed, 58 insertions(+) diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index 62ffe6eb5503..6cd9d5375d7c 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -676,6 +676,54 @@ static void ghes_defer_non_standard_event(struct acpi_= hest_generic_data *gdata, schedule_work(&entry->work); } =20 +static void cxl_cper_post_prot_err(struct cxl_cper_sec_prot_err *prot_err, + int severity) +{ + struct cxl_cper_prot_err_work_data wd; + u8 *dvsec_start, *cap_start; + + if (!(prot_err->valid_bits & PROT_ERR_VALID_AGENT_ADDRESS)) { + pr_err_ratelimited("CXL CPER invalid agent type\n"); + return; + } + + if (!(prot_err->valid_bits & PROT_ERR_VALID_ERROR_LOG)) { + pr_err_ratelimited("CXL CPER invalid protocol error log\n"); + return; + } + + if (prot_err->err_len !=3D sizeof(struct cxl_ras_capability_regs)) { + pr_err_ratelimited("CXL CPER invalid RAS Cap size (%u)\n", + prot_err->err_len); + return; + } + + if (!(prot_err->valid_bits & PROT_ERR_VALID_SERIAL_NUMBER)) + pr_warn(FW_WARN "CXL CPER no device serial number\n"); + + switch (prot_err->agent_type) { + case RCD: + case DEVICE: + case LD: + case FMLD: + case RP: + case DSP: + case USP: + memcpy(&wd.prot_err, prot_err, sizeof(wd.prot_err)); + + dvsec_start =3D (u8 *)(prot_err + 1); + cap_start =3D dvsec_start + prot_err->dvsec_len; + + wd.ras_cap =3D *(struct cxl_ras_capability_regs *)cap_start; + wd.severity =3D cper_severity_to_aer(severity); + break; + default: + pr_err_ratelimited("CXL CPER invalid agent type: %d\n", + prot_err->agent_type); + return; + } +} + /* Room for 8 entries for each of the 4 event log queues */ #define CXL_CPER_FIFO_DEPTH 32 DEFINE_KFIFO(cxl_cper_fifo, struct cxl_cper_work_data, CXL_CPER_FIFO_DEPTH= ); @@ -795,6 +843,10 @@ static bool ghes_do_proc(struct ghes *ghes, } else if (guid_equal(sec_type, &CPER_SEC_PROC_ARM)) { queued =3D ghes_handle_arm_hw_error(gdata, sev, sync); + } else if (guid_equal(sec_type, &CPER_SEC_CXL_PROT_ERR)) { + struct cxl_cper_sec_prot_err *prot_err =3D acpi_hest_get_payload(gdata); + + cxl_cper_post_prot_err(prot_err, gdata->error_severity); } else if (guid_equal(sec_type, &CPER_SEC_CXL_GEN_MEDIA_GUID)) { struct cxl_cper_event_rec *rec =3D acpi_hest_get_payload(gdata); =20 diff --git a/include/cxl/event.h b/include/cxl/event.h index 992568b35455..c9a38ebaf207 100644 --- a/include/cxl/event.h +++ b/include/cxl/event.h @@ -232,6 +232,12 @@ struct cxl_ras_capability_regs { u32 header_log[16]; }; =20 +struct cxl_cper_prot_err_work_data { + struct cxl_cper_sec_prot_err prot_err; + struct cxl_ras_capability_regs ras_cap; + int severity; +}; + #ifdef CONFIG_ACPI_APEI_GHES int cxl_cper_register_event_work(struct work_struct *work); int cxl_cper_unregister_event_work(struct work_struct *work); --=20 2.17.1 From nobody Sun Nov 24 02:49:35 2024 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2072.outbound.protection.outlook.com [40.107.220.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB62112F375; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Nov 2024 00:39:34.0651 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 447822bd-3f13-40ef-e5e2-08dd0832a389 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.12];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709B.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6784 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When PCIe AER is in FW-First, OS should process CXL Protocol errors from CPER records. Introduce support for handling and logging CXL Protocol errors. The defined trace events cxl_aer_uncorrectable_error and cxl_aer_correctable_error trace native CXL AER endpoint errors, while cxl_cper_trace_corr_prot_err and cxl_cper_trace_uncorr_prot_err trace native CXL AER port errors. Reuse both sets to trace FW-First protocol errors. Since the CXL code is required to be called from process context and GHES is in interrupt context, use workqueues for processing. Similar to CXL CPER event handling, use kfifo to handle errors as it simplifies queue processing by providing lock free fifo operations. Add the ability for the CXL sub-system to register a workqueue to process CXL CPER protocol errors. Signed-off-by: Smita Koralahalli --- drivers/acpi/apei/ghes.c | 41 ++++++++++++++++++++++++++++++ drivers/cxl/core/pci.c | 50 ++++++++++++++++++++++++++++++++++++ drivers/cxl/cxlpci.h | 6 +++++ drivers/cxl/pci.c | 55 ++++++++++++++++++++++++++++++++++++++++ include/cxl/event.h | 15 +++++++++++ 5 files changed, 167 insertions(+) diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index 6cd9d5375d7c..32062b6a9985 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -676,6 +676,15 @@ static void ghes_defer_non_standard_event(struct acpi_= hest_generic_data *gdata, schedule_work(&entry->work); } =20 +/* Room for 8 entries */ +#define CXL_CPER_PROT_ERR_FIFO_DEPTH 8 +static DEFINE_KFIFO(cxl_cper_prot_err_fifo, struct cxl_cper_prot_err_work_= data, + CXL_CPER_PROT_ERR_FIFO_DEPTH); + +/* Synchronize schedule_work() with cxl_cper_prot_err_work changes */ +static DEFINE_SPINLOCK(cxl_cper_prot_err_work_lock); +struct work_struct *cxl_cper_prot_err_work; + static void cxl_cper_post_prot_err(struct cxl_cper_sec_prot_err *prot_err, int severity) { @@ -701,6 +710,11 @@ static void cxl_cper_post_prot_err(struct cxl_cper_sec= _prot_err *prot_err, if (!(prot_err->valid_bits & PROT_ERR_VALID_SERIAL_NUMBER)) pr_warn(FW_WARN "CXL CPER no device serial number\n"); =20 + guard(spinlock_irqsave)(&cxl_cper_prot_err_work_lock); + + if (!cxl_cper_prot_err_work) + return; + switch (prot_err->agent_type) { case RCD: case DEVICE: @@ -722,6 +736,13 @@ static void cxl_cper_post_prot_err(struct cxl_cper_sec= _prot_err *prot_err, prot_err->agent_type); return; } + + if (!kfifo_put(&cxl_cper_prot_err_fifo, wd)) { + pr_err_ratelimited("CXL CPER kfifo overflow\n"); + return; + } + + schedule_work(cxl_cper_prot_err_work); } =20 /* Room for 8 entries for each of the 4 event log queues */ @@ -809,6 +830,26 @@ int cxl_cper_kfifo_get(struct cxl_cper_work_data *wd) } EXPORT_SYMBOL_NS_GPL(cxl_cper_kfifo_get, CXL); =20 +int cxl_cper_register_prot_err_work(struct work_struct *work) +{ + return cxl_cper_register_work(&cxl_cper_prot_err_work, + &cxl_cper_prot_err_work_lock, work); +} +EXPORT_SYMBOL_NS_GPL(cxl_cper_register_prot_err_work, CXL); + +int cxl_cper_unregister_prot_err_work(struct work_struct *work) +{ + return cxl_cper_unregister_work(&cxl_cper_prot_err_work, + &cxl_cper_prot_err_work_lock, work); +} +EXPORT_SYMBOL_NS_GPL(cxl_cper_unregister_prot_err_work, CXL); + +int cxl_cper_prot_err_kfifo_get(struct cxl_cper_prot_err_work_data *wd) +{ + return kfifo_get(&cxl_cper_prot_err_fifo, wd); +} +EXPORT_SYMBOL_NS_GPL(cxl_cper_prot_err_kfifo_get, CXL); + static bool ghes_do_proc(struct ghes *ghes, const struct acpi_hest_generic_status *estatus) { diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 4ede038a7148..c992b34c290b 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -650,6 +650,56 @@ void read_cdat_data(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(read_cdat_data, CXL); =20 +void cxl_cper_trace_corr_prot_err(struct pci_dev *pdev, bool flag, + struct cxl_ras_capability_regs ras_cap) +{ + struct cxl_dev_state *cxlds; + u32 status; + + status =3D ras_cap.cor_status & ~ras_cap.cor_mask; + + if (!flag) { + trace_cxl_port_aer_correctable_error(&pdev->dev, status); + return; + } + + cxlds =3D pci_get_drvdata(pdev); + if (!cxlds) + return; + + trace_cxl_aer_correctable_error(cxlds->cxlmd, status); +} +EXPORT_SYMBOL_NS_GPL(cxl_cper_trace_corr_prot_err, CXL); + +void cxl_cper_trace_uncorr_prot_err(struct pci_dev *pdev, bool flag, + struct cxl_ras_capability_regs ras_cap) +{ + struct cxl_dev_state *cxlds; + u32 status, fe; + + status =3D ras_cap.uncor_status & ~ras_cap.uncor_mask; + + if (hweight32(status) > 1) + fe =3D BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK, + ras_cap.cap_control)); + else + fe =3D status; + + if (!flag) { + trace_cxl_port_aer_uncorrectable_error(&pdev->dev, status, fe, + ras_cap.header_log); + return; + } + + cxlds =3D pci_get_drvdata(pdev); + if (!cxlds) + return; + + trace_cxl_aer_uncorrectable_error(cxlds->cxlmd, status, fe, + ras_cap.header_log); +} +EXPORT_SYMBOL_NS_GPL(cxl_cper_trace_uncorr_prot_err, CXL); + static void __cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) { diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 4da07727ab9c..5e4aa8681937 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -129,4 +129,10 @@ void read_cdat_data(struct cxl_port *port); void cxl_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state); + +struct cxl_ras_capability_regs; +void cxl_cper_trace_corr_prot_err(struct pci_dev *pdev, bool flag, + struct cxl_ras_capability_regs ras_cap); +void cxl_cper_trace_uncorr_prot_err(struct pci_dev *pdev, bool flag, + struct cxl_ras_capability_regs ras_cap); #endif /* __CXL_PCI_H__ */ diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 88a14d7baa65..e261abe60e90 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -1067,6 +1067,53 @@ static void cxl_cper_work_fn(struct work_struct *wor= k) } static DECLARE_WORK(cxl_cper_work, cxl_cper_work_fn); =20 +static void cxl_cper_handle_prot_err(struct cxl_cper_prot_err_work_data *d= ata) +{ + unsigned int devfn =3D PCI_DEVFN(data->prot_err.agent_addr.device, + data->prot_err.agent_addr.function); + struct pci_dev *pdev __free(pci_dev_put) =3D + pci_get_domain_bus_and_slot( + data->prot_err.agent_addr.segment, + data->prot_err.agent_addr.bus, + devfn + ); + int port_type; + + if (!pdev) + return; + + guard(device)(&pdev->dev); + if (pdev->driver !=3D &cxl_pci_driver) + return; + + port_type =3D pci_pcie_type(pdev); + if (port_type =3D=3D PCI_EXP_TYPE_ROOT_PORT || + port_type =3D=3D PCI_EXP_TYPE_DOWNSTREAM || + port_type =3D=3D PCI_EXP_TYPE_UPSTREAM) { + if (data->severity =3D=3D AER_CORRECTABLE) + cxl_cper_trace_corr_prot_err(pdev, false, data->ras_cap); + else + cxl_cper_trace_uncorr_prot_err(pdev, false, data->ras_cap); + + return; + } + + if (data->severity =3D=3D AER_CORRECTABLE) + cxl_cper_trace_corr_prot_err(pdev, true, data->ras_cap); + else + cxl_cper_trace_uncorr_prot_err(pdev, true, data->ras_cap); + +} + +static void cxl_cper_prot_err_work_fn(struct work_struct *work) +{ + struct cxl_cper_prot_err_work_data wd; + + while (cxl_cper_prot_err_kfifo_get(&wd)) + cxl_cper_handle_prot_err(&wd); +} +static DECLARE_WORK(cxl_cper_prot_err_work, cxl_cper_prot_err_work_fn); + static int __init cxl_pci_driver_init(void) { int rc; @@ -1079,13 +1126,21 @@ static int __init cxl_pci_driver_init(void) if (rc) pci_unregister_driver(&cxl_pci_driver); =20 + rc =3D cxl_cper_register_prot_err_work(&cxl_cper_prot_err_work); + if (rc) { + cxl_cper_unregister_event_work(&cxl_cper_work); + pci_unregister_driver(&cxl_pci_driver); + } + return rc; } =20 static void __exit cxl_pci_driver_exit(void) { cxl_cper_unregister_event_work(&cxl_cper_work); + cxl_cper_unregister_prot_err_work(&cxl_cper_prot_err_work); cancel_work_sync(&cxl_cper_work); + cancel_work_sync(&cxl_cper_prot_err_work); pci_unregister_driver(&cxl_pci_driver); } =20 diff --git a/include/cxl/event.h b/include/cxl/event.h index c9a38ebaf207..5f83c3bfc813 100644 --- a/include/cxl/event.h +++ b/include/cxl/event.h @@ -242,6 +242,9 @@ struct cxl_cper_prot_err_work_data { int cxl_cper_register_event_work(struct work_struct *work); int cxl_cper_unregister_event_work(struct work_struct *work); int cxl_cper_kfifo_get(struct cxl_cper_work_data *wd); +int cxl_cper_register_prot_err_work(struct work_struct *work); +int cxl_cper_unregister_prot_err_work(struct work_struct *work); +int cxl_cper_prot_err_kfifo_get(struct cxl_cper_prot_err_work_data *wd); #else static inline int cxl_cper_register_event_work(struct work_struct *work) { @@ -256,6 +259,18 @@ static inline int cxl_cper_kfifo_get(struct cxl_cper_w= ork_data *wd) { return 0; } +static inline int cxl_cper_register_prot_err_work(struct work_struct *work) +{ + return 0; +} +static inline int cxl_cper_unregister_prot_err_work(struct work_struct *wo= rk) +{ + return 0; +} +static inline int cxl_cper_prot_err_kfifo_get(struct cxl_cper_prot_err_wor= k_data *wd) +{ + return 0; +} #endif =20 #endif /* _LINUX_CXL_EVENT_H */ --=20 2.17.1