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Wysocki" , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Connor Abbott , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10146; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=I07ngYL9Ra1f9h+CP4yA7pd1FaT3h7r+nDReMCfjPD8=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnPNFXvsfG19CuOcSshzsLLrl9P5JiCVdB6NQYWhe+ leGk+k2JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZzzRVwAKCRB33NvayMhJ0aqAD/ 9BdW9LZzIoIYl35jeVi9cqCgNGXipLp/slLxcES64BRqOg55WgP8C+mC9AQY0K2p40Vh9Km2z9+QXA FonK8lkCmQXlP8i+4UWolxNN5NeQ0TXbzWqovX6t3o26ubGTzeciItmtaR99LfzgRTNVp6EmpUUFME BYXQRayCUWbyjQfpS62gs+vxwc0AdTaBe18Eh/rfbowEmWxH25J9Btc/LrVIubMwDHtqAz+REGSKui bQG7Gv4+Z2w7m8v35UYqWAqJ7bTl8tFTKYZvo0tGCW7lKu1CZji0ZrIAyzTBhrsZljUUzRpCaAqxCA tSGA3yTLPI8U2MdzektRPFBSEfQU/TlTwSNdFhxdNTAacs1HCHpXnSXATf38I2HsT4OR8f9zynEg/n PZqJ67Lv+iOnZx3ESzZ6ublhomHwSM3zL/Nua3WhLwh7S8jABMdjsAJueh7DuQu1ngJPkiqvBZPDUk aVwH27cPcNRTGmDdMefC5vJGwmcI39uedMVCyJ2TeO3ZA7tENg1xvJgn2anAM5rCSzQx2gKlMNGpnI gFqPqxsD5SzgmFhy397X7jvBeEGSTxdQqGrxyQDGa+YfhDY0OwsvX3dvvGIf8zaLTPPvYf3RgV1NfY rKhaYudkqE+JEI+cQm8DQ5SvLjRBeJWr7QeNLTowDyOSKUUOpJLrSGER9tew== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Half of the current "Quirks" are in fact features, so rename the defines with FEAT instead of QUIRK. They will be moved in a separate bitfield in a second time. No functional changes. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 62 +++++++++++++++-----------= ---- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 +- drivers/gpu/drm/msm/adreno/adreno_device.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 ++-- 4 files changed, 38 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a6xx_catalog.c index 0c560e84ad5a53bb4e8a49ba4e153ce9cf33f7ae..825c820def315968d508973c8ae= 40c7c7b646569 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -743,7 +743,7 @@ static const struct adreno_info a6xx_gpus[] =3D { }, .gmem =3D SZ_512K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT, + .quirks =3D ADRENO_FEAT_HAS_CACHED_COHERENT, .init =3D a6xx_gpu_init, .zapfw =3D "a615_zap.mbn", .a6xx =3D &(const struct a6xx_info) { @@ -769,7 +769,7 @@ static const struct adreno_info a6xx_gpus[] =3D { }, .gmem =3D SZ_512K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT, + .quirks =3D ADRENO_FEAT_HAS_CACHED_COHERENT, .init =3D a6xx_gpu_init, .a6xx =3D &(const struct a6xx_info) { .protect =3D &a630_protect, @@ -839,7 +839,7 @@ static const struct adreno_info a6xx_gpus[] =3D { }, .gmem =3D SZ_512K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT, + .quirks =3D ADRENO_FEAT_HAS_CACHED_COHERENT, .init =3D a6xx_gpu_init, .zapfw =3D "a615_zap.mdt", .a6xx =3D &(const struct a6xx_info) { @@ -864,8 +864,8 @@ static const struct adreno_info a6xx_gpus[] =3D { }, .gmem =3D SZ_512K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + .quirks =3D ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV, .init =3D a6xx_gpu_init, .zapfw =3D "a620_zap.mbn", .a6xx =3D &(const struct a6xx_info) { @@ -892,7 +892,7 @@ static const struct adreno_info a6xx_gpus[] =3D { }, .gmem =3D SZ_1M, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT, + .quirks =3D ADRENO_FEAT_HAS_CACHED_COHERENT, .init =3D a6xx_gpu_init, .zapfw =3D "a630_zap.mdt", .a6xx =3D &(const struct a6xx_info) { @@ -911,7 +911,7 @@ static const struct adreno_info a6xx_gpus[] =3D { }, .gmem =3D SZ_1M, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT, + .quirks =3D ADRENO_FEAT_HAS_CACHED_COHERENT, .init =3D a6xx_gpu_init, .zapfw =3D "a640_zap.mdt", .a6xx =3D &(const struct a6xx_info) { @@ -934,8 +934,8 @@ static const struct adreno_info a6xx_gpus[] =3D { }, .gmem =3D SZ_1M + SZ_128K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + .quirks =3D ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV, .init =3D a6xx_gpu_init, .zapfw =3D "a650_zap.mdt", .a6xx =3D &(const struct a6xx_info) { @@ -961,8 +961,8 @@ static const struct adreno_info a6xx_gpus[] =3D { }, .gmem =3D SZ_1M + SZ_512K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + .quirks =3D ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV, .init =3D a6xx_gpu_init, .zapfw =3D "a660_zap.mdt", .a6xx =3D &(const struct a6xx_info) { @@ -981,8 +981,8 @@ static const struct adreno_info a6xx_gpus[] =3D { }, .gmem =3D SZ_1M + SZ_512K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + .quirks =3D ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV, .init =3D a6xx_gpu_init, .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a690_hwcg, @@ -1000,8 +1000,8 @@ static const struct adreno_info a6xx_gpus[] =3D { }, .gmem =3D SZ_512K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + .quirks =3D ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV, .init =3D a6xx_gpu_init, .zapfw =3D "a660_zap.mbn", .a6xx =3D &(const struct a6xx_info) { @@ -1028,7 +1028,7 @@ static const struct adreno_info a6xx_gpus[] =3D { }, .gmem =3D SZ_2M, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT, + .quirks =3D ADRENO_FEAT_HAS_CACHED_COHERENT, .init =3D a6xx_gpu_init, .zapfw =3D "a640_zap.mdt", .a6xx =3D &(const struct a6xx_info) { @@ -1046,8 +1046,8 @@ static const struct adreno_info a6xx_gpus[] =3D { }, .gmem =3D SZ_4M, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + .quirks =3D ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV, .init =3D a6xx_gpu_init, .zapfw =3D "a690_zap.mdt", .a6xx =3D &(const struct a6xx_info) { @@ -1331,7 +1331,7 @@ static const struct adreno_info a7xx_gpus[] =3D { }, .gmem =3D SZ_128K, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .quirks =3D ADRENO_QUIRK_HAS_HW_APRIV, + .quirks =3D ADRENO_FEAT_HAS_HW_APRIV, .init =3D a6xx_gpu_init, .zapfw =3D "a702_zap.mbn", .a6xx =3D &(const struct a6xx_info) { @@ -1355,9 +1355,9 @@ static const struct adreno_info a7xx_gpus[] =3D { }, .gmem =3D SZ_2M, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV | - ADRENO_QUIRK_PREEMPTION, + .quirks =3D ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV | + ADRENO_FEAT_PREEMPTION, .init =3D a6xx_gpu_init, .zapfw =3D "a730_zap.mdt", .a6xx =3D &(const struct a6xx_info) { @@ -1377,9 +1377,9 @@ static const struct adreno_info a7xx_gpus[] =3D { }, .gmem =3D 3 * SZ_1M, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV | - ADRENO_QUIRK_PREEMPTION, + .quirks =3D ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV | + ADRENO_FEAT_PREEMPTION, .init =3D a6xx_gpu_init, .zapfw =3D "a740_zap.mdt", .a6xx =3D &(const struct a6xx_info) { @@ -1400,9 +1400,9 @@ static const struct adreno_info a7xx_gpus[] =3D { }, .gmem =3D 3 * SZ_1M, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV | - ADRENO_QUIRK_PREEMPTION, + .quirks =3D ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV | + ADRENO_FEAT_PREEMPTION, .init =3D a6xx_gpu_init, .a6xx =3D &(const struct a6xx_info) { .hwcg =3D a740_hwcg, @@ -1422,9 +1422,9 @@ static const struct adreno_info a7xx_gpus[] =3D { }, .gmem =3D 3 * SZ_1M, .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, - .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV | - ADRENO_QUIRK_PREEMPTION, + .quirks =3D ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV | + ADRENO_FEAT_PREEMPTION, .init =3D a6xx_gpu_init, .zapfw =3D "gen70900_zap.mbn", .a6xx =3D &(const struct a6xx_info) { diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 019610341df1506c89f44e86b8d1deeb27d61857..2ebd3fac212576a1507e0b6afe2= 560cd0408dd89 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2478,7 +2478,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) adreno_gpu->gmu_is_wrapper =3D of_device_is_compatible(node, "qcom,adreno= -gmu-wrapper"); =20 adreno_gpu->base.hw_apriv =3D - !!(config->info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); + !!(config->info->quirks & ADRENO_FEAT_HAS_HW_APRIV); =20 /* gpu->info only gets assigned in adreno_gpu_init() */ is_a7xx =3D config->info->family =3D=3D ADRENO_7XX_GEN1 || @@ -2495,7 +2495,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) } =20 if ((enable_preemption =3D=3D 1) || (enable_preemption =3D=3D -1 && - (config->info->quirks & ADRENO_QUIRK_PREEMPTION))) + (config->info->quirks & ADRENO_FEAT_PREEMPTION))) ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 4); else if (is_a7xx) ret =3D adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/m= sm/adreno/adreno_device.c index 9ffe91920fbfb4841b28aabec9fbde94539fdd83..09d4569f77528c2a20cabc81466= 8c4c930dd07f1 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -207,7 +207,7 @@ static int adreno_bind(struct device *dev, struct devic= e *master, void *data) =20 priv->is_a2xx =3D info->family < ADRENO_3XX; priv->has_cached_coherent =3D - !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT); + !!(info->quirks & ADRENO_FEAT_HAS_CACHED_COHERENT); =20 gpu =3D info->init(drm); if (IS_ERR(gpu)) { diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index e71f420f8b3a8e6cfc52dd1c4d5a63ef3704a07f..8782c25e8a393ec7d9dc23ad450= 908d039bd08c5 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -54,9 +54,10 @@ enum adreno_family { #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1) #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) -#define ADRENO_QUIRK_HAS_HW_APRIV BIT(3) -#define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4) -#define ADRENO_QUIRK_PREEMPTION BIT(5) + +#define ADRENO_FEAT_HAS_HW_APRIV BIT(3) +#define ADRENO_FEAT_HAS_CACHED_COHERENT BIT(4) +#define ADRENO_FEAT_PREEMPTION BIT(5) =20 /* Helper for formating the chip_id in the way that userspace tools like * crashdec expect. --=20 2.34.1