From nobody Mon Feb 9 17:27:03 2026 Received: from mail-pg1-f179.google.com (mail-pg1-f179.google.com [209.85.215.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40B5614B06E for ; Tue, 19 Nov 2024 20:30:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732048253; cv=none; b=NSml/B1O3RJTFT+HxxvEoBac2kPuOTRGF3J/NAgm2EfvapXRjGFr8B/EmQMsCzpal43ojgCodq4L1WrOpiWhqmSxKmim10yVYvaOsY5Pk9Iia3VD1mEXPxGHEADPwSglF+sKizjQ2YStW7Ki4APqPi+d+soJrZ1SNiAmdFrFHRA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732048253; c=relaxed/simple; bh=9a3a2dykXm+Z1VuOIzXUUFPIUB4KYnT3BbloIfBYDqg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YZnY5ZMO94FznogXice5/UWFYZvhN8utdSMGRwwakT21S2H4lT/raTjHBJcBlWys60eIAok/JYR9T1w3wHeUNg3xoz7CqvKMAIwhhv8Z29DTAk/Zp0teB3pS/aEmrgwU6OFc4jZGB9Pe7Mt8cc91Z9sd+o5Mw6WyPidEFUCwOmg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=o0xsLxbk; arc=none smtp.client-ip=209.85.215.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="o0xsLxbk" Received: by mail-pg1-f179.google.com with SMTP id 41be03b00d2f7-7ede82dbb63so2189568a12.2 for ; Tue, 19 Nov 2024 12:30:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1732048250; x=1732653050; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=2qPwdXgi93D1Fj1M3CTUmRPQX23R+cN6bIgDXtW8EzY=; b=o0xsLxbkhLJ21l87Ve0dLhopPiU/2eKj5rUKGEmqAsKjm7Mklrfr3qPEAJ8B7zjOl5 f3t0oJdnWna2iun7jK8a+iVMfFzLROCO+Gpq2c1aFOEWtf6xIMViwMoYystcsNSy3B7w 5OVyohRwrKCXkAcSjCeEmFw/TNuAWGzZ5bJ6fz88salWfutHIM6GwYIoC8cN32WtVYr6 B+FyKLIHS0cmylE1ND4Ruso8YkixxR0SP4GAwl2XUpEjyofzmqrVlzx7A2CK8KNtxjw0 7AKuQMLuC/VpDm3gWz23i5llqaA3wngwXusqimS5KDHnQIDzWaSWDbQqK4WbDPTZtvu3 PTAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732048250; x=1732653050; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2qPwdXgi93D1Fj1M3CTUmRPQX23R+cN6bIgDXtW8EzY=; b=OunuBN+XBiAIGCsLjvatwR3KCUlch4UPUMFlNsUZUcMjjAMds8rw314SN8HCCxKRsd 3UiHYuqzbzvgSudd3PILfQtCWEXwb1FOLdKoQrM6sq93P6paLyO3izh8NuZweQhgsx9h jfU1Hfv3QQb2wTVmLCl84RmOp2mDVUmyTF7vUePQZNbyzB377nlDMpiGsUsXqz7zFl4v GXW3W1x7S1RP0e0edtd9d9JrGA27evov0v7Q/wH2vwANHNChfkVkQPWiCf/oQgnSOM7I Cnp3uHAokCuTeCJoEHq5x2nT12806SWkADT1WUSg49HNAcJxRngdh9EstY2ReolVLDk/ N3Hg== X-Forwarded-Encrypted: i=1; AJvYcCUS9L8mszGmSYWt3+hUz6LLEE7NTLqZbFhydBT3hR1gd+lvplVfJty9T+RYMq7oGTB1tHubWyym5a9ZrlU=@vger.kernel.org X-Gm-Message-State: AOJu0YxcvRly/meL9ppADyPfMEmaP6VFqp0QnA4ZFXYbcKzQ0Uod0zaH DtpMAnFm7AETdtHuvm4HPsNoLU0Ej3wINuemNu0R6xQiADx80yFD0bjMfjmFXEY= X-Google-Smtp-Source: AGHT+IHGbLa6SegMg+6UWCLGuDz+AC9C3f5G3GHUQKuYncIbocwbfU1Y52MRciljHs7ffGD0KEce3w== X-Received: by 2002:a17:90b:288e:b0:2ea:37b4:5373 with SMTP id 98e67ed59e1d1-2eaca70abedmr135913a91.10.1732048250306; Tue, 19 Nov 2024 12:30:50 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-211d0f34f2fsm79001315ad.159.2024.11.19.12.30.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2024 12:30:50 -0800 (PST) From: Atish Patra Date: Tue, 19 Nov 2024 12:29:49 -0800 Subject: [PATCH 1/8] drivers/perf: riscv: Add SBI v3.0 flag Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241119-pmu_event_info-v1-1-a4f9691421f8@rivosinc.com> References: <20241119-pmu_event_info-v1-0-a4f9691421f8@rivosinc.com> In-Reply-To: <20241119-pmu_event_info-v1-0-a4f9691421f8@rivosinc.com> To: Anup Patel , Will Deacon , Mark Rutland , Paul Walmsley , Palmer Dabbelt , Mayuresh Chitale Cc: linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Atish Patra X-Mailer: b4 0.15-dev-13183 There are new PMU related features introduced in SBI v3.0. 1. Raw Event v2 which allows mhpmeventX value to be 56 bit wide. 2. Get Event info function to do a bulk query at one shot. Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 391ca1422cae..cb98efa9b106 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -63,6 +63,7 @@ PMU_FORMAT_ATTR(event, "config:0-47"); PMU_FORMAT_ATTR(firmware, "config:62-63"); =20 static bool sbi_v2_available; +static bool sbi_v3_available; static DEFINE_STATIC_KEY_FALSE(sbi_pmu_snapshot_available); #define sbi_pmu_snapshot_available() \ static_branch_unlikely(&sbi_pmu_snapshot_available) @@ -1450,6 +1451,9 @@ static int __init pmu_sbi_devinit(void) if (sbi_spec_version >=3D sbi_mk_version(2, 0)) sbi_v2_available =3D true; =20 + if (sbi_spec_version >=3D sbi_mk_version(3, 0)) + sbi_v3_available =3D true; + ret =3D cpuhp_setup_state_multi(CPUHP_AP_PERF_RISCV_STARTING, "perf/riscv/pmu:starting", pmu_sbi_starting_cpu, pmu_sbi_dying_cpu); --=20 2.34.1 From nobody Mon Feb 9 17:27:03 2026 Received: from mail-pg1-f175.google.com (mail-pg1-f175.google.com [209.85.215.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AAACF1D31B6 for ; Tue, 19 Nov 2024 20:30:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732048255; cv=none; b=UqiWc88hctt52ogc0pzhY7BOPV1p5wt44nLqi00EZ2lPkCIKJLaJWWYCgK2uTpeunUDU8PBohMB0qp2Y0g8yWHXii4ItJKgzQuMTy1u3QAT4yytIFrek46FAh+aELJYXL9pS/YRj4sTlaXKPU2R77/uDhWRttx6/RbNHhlKC6YQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732048255; c=relaxed/simple; bh=d2OWDcgMWNTgpuTUqhaseMx00dJ1C9AXSYm/wfcfCPo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pjFBd8K/jusU5u0J2OXNnjHv+FRwmG8fD/nQz8vwi5ugPAhbYlRRVPDvYttnbpvRg+r2Bfwx+XqOR1gcy/M9zE3Nk2kJw07LyWlII+fHC9ZeiTIrD9gGenlW5QYYDgcZ8OEB93ciKINlbvQKvnsMhuLxToVt7tCbHwDGyx816WA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=szgdI7d1; arc=none smtp.client-ip=209.85.215.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="szgdI7d1" Received: by mail-pg1-f175.google.com with SMTP id 41be03b00d2f7-7eab7622b61so1005752a12.1 for ; Tue, 19 Nov 2024 12:30:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1732048253; x=1732653053; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=FB/tddqfX+5D+NwPYtCZBvpcbtznximYassXddDySaI=; b=szgdI7d1MF+HBQFcrcrbz1J3B3biwR9HJnw0k2Y6oV3Uj+pIDW6AYkRyZdHFm3hGAY W/WfQ5obz8cYmJ5U3k/1axsYPvXa61VOyp633kj0xGDpA03cuvP4XO48jkH0Wl4bk3O3 KPq8dohzNoWE/cYQDwizzAPXqAEbraOWUKkbObY8KNapPu+7Wa5d0bcAnHP0LdWh3FG4 /fDgNBQ593gcBVsvloQW6oBU2HORVocS+EVoj9L60xX/yplQZ2gZhthZZtgOD9vuKowM TrpiE2aGQlPVuXwu3Stjg9X+9y0mnLj1Ei6SbdS1AJJgSeZ196xBk+Z8gnBpJQF6/wai 43cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732048253; x=1732653053; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FB/tddqfX+5D+NwPYtCZBvpcbtznximYassXddDySaI=; b=mivi8U9TfEH3umhebRGlxwIkyMyX9hDsBn37qmcb9CcjLUFDz9AwA7dA1FooeUODiU TWGl78/NOAgclRz5VgaduUYC9AyOtLEXItl/pLIW2EIZd+4erfbxWhlRwcYO588BEE4A GkyneZxSSKbcoMglf0xq78xzPiQK5Lun1Ef7Nfrv/PY8zSAIv3FoBXKoHEG/VBHnvDZx qJRfXnaL9soR8JyCEdSfEYXiTUT7I/tG5Plt/hUAz7/2JJ9rd2JDGPDqnODe8bv0XOlp w4MZHriU86GXf+lFb/6UJCUC4GYBhWG8tgIKVhhCOm5FtCya7ZNoDtP0VPY+30DyWGt7 6ObQ== X-Forwarded-Encrypted: i=1; AJvYcCUc3V08BXknFyCJuHBVzdGIKdHR5MZuUQTdqbCjK/ETm3qK+XRyUUhcpaYTuv5Wk5HLzM5cisEizUIwTqA=@vger.kernel.org X-Gm-Message-State: AOJu0YzpWZZSCue0IKao1w04/Dhjt4k3wkmxU5+z1KGeXAly6QWWLXB8 mATZDQnH/oJxjX2C3lziiEwsW2XcGmRmu/xbzefBv1u5yjnBb3ZAD0jq6IEkcJg= X-Google-Smtp-Source: AGHT+IGG3BOEKBQHByHPNxLGRscpaUzNEj7RMHYMCOiguADUgT/ZA6zCcmpHgOYphyvS5L29CLFFRQ== X-Received: by 2002:a05:6a21:3287:b0:1d8:a29b:8f6f with SMTP id adf61e73a8af0-1ddae4e24bbmr613518637.16.1732048251371; Tue, 19 Nov 2024 12:30:51 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-211d0f34f2fsm79001315ad.159.2024.11.19.12.30.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2024 12:30:51 -0800 (PST) From: Atish Patra Date: Tue, 19 Nov 2024 12:29:50 -0800 Subject: [PATCH 2/8] drivers/perf: riscv: Fix Platform firmware event data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241119-pmu_event_info-v1-2-a4f9691421f8@rivosinc.com> References: <20241119-pmu_event_info-v1-0-a4f9691421f8@rivosinc.com> In-Reply-To: <20241119-pmu_event_info-v1-0-a4f9691421f8@rivosinc.com> To: Anup Patel , Will Deacon , Mark Rutland , Paul Walmsley , Palmer Dabbelt , Mayuresh Chitale Cc: linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Atish Patra X-Mailer: b4 0.15-dev-13183 Platform firmware event data field is allowed to be 62 bits for Linux as uppper most two bits are reserved to indicate SBI fw or platform specific firmware events. However, the event data field is masked as per the hardware raw event mask which is not correct. Fix the platform firmware event data field with proper mask. Fixes: f0c9363db2dd ("perf/riscv-sbi: Add platform specific firmware event = handling") Signed-off-by: Atish Patra --- arch/riscv/include/asm/sbi.h | 1 + drivers/perf/riscv_pmu_sbi.c | 12 +++++------- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 98f631b051db..9be38b05f4ad 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -158,6 +158,7 @@ struct riscv_pmu_snapshot_data { }; =20 #define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0) +#define RISCV_PMU_PLAT_FW_EVENT_MASK GENMASK_ULL(61, 0) #define RISCV_PMU_RAW_EVENT_IDX 0x20000 #define RISCV_PLAT_FW_EVENT 0xFFFF =20 diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index cb98efa9b106..50cbdbf66bb7 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -508,7 +508,6 @@ static int pmu_sbi_event_map(struct perf_event *event, = u64 *econfig) { u32 type =3D event->attr.type; u64 config =3D event->attr.config; - u64 raw_config_val; int ret; =20 /* @@ -529,21 +528,20 @@ static int pmu_sbi_event_map(struct perf_event *event= , u64 *econfig) case PERF_TYPE_RAW: /* * As per SBI specification, the upper 16 bits must be unused - * for a raw event. + * for a hardware raw event. * Bits 63:62 are used to distinguish between raw events * 00 - Hardware raw event * 10 - SBI firmware events * 11 - Risc-V platform specific firmware event */ - raw_config_val =3D config & RISCV_PMU_RAW_EVENT_MASK; + switch (config >> 62) { case 0: ret =3D RISCV_PMU_RAW_EVENT_IDX; - *econfig =3D raw_config_val; + *econfig =3D config & RISCV_PMU_RAW_EVENT_MASK; break; case 2: - ret =3D (raw_config_val & 0xFFFF) | - (SBI_PMU_EVENT_TYPE_FW << 16); + ret =3D (config & 0xFFFF) | (SBI_PMU_EVENT_TYPE_FW << 16); break; case 3: /* @@ -552,7 +550,7 @@ static int pmu_sbi_event_map(struct perf_event *event, = u64 *econfig) * Event data - raw event encoding */ ret =3D SBI_PMU_EVENT_TYPE_FW << 16 | RISCV_PLAT_FW_EVENT; - *econfig =3D raw_config_val; + *econfig =3D config & RISCV_PMU_PLAT_FW_EVENT_MASK; break; } break; --=20 2.34.1 From nobody Mon Feb 9 17:27:03 2026 Received: from mail-pj1-f47.google.com (mail-pj1-f47.google.com [209.85.216.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 363C11D3648 for ; Tue, 19 Nov 2024 20:30:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732048254; cv=none; b=ff9J3w44/M1exUD+Z34dirxo/IV9RsSHQTwlKdceMkr4xproBDCzd6aiG0E/e0fbaDbSsOmRpej75vqgW+XBQMJGJ9EHH7SMLk00+YFD/ULLygAGweP4hRF/Pb1hY+PQSbI+GSd8e+marY8+yJJQU8/lFFsTDHs9vn8SGpLLp2g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732048254; c=relaxed/simple; bh=SADvMhA7/Ukb2OMwQcY0BoWNEsNhkhKslaT1ZVi9WWw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jPwV7+ew5LIy6xwhhxhl//8aq+3wHi6B+BeS9o/f9NtBt+iZl+nxhzZnUYAiaHG/kGMxKy9uto7SrbckXPzwLDlyoB5AX/b4jtsDl66HOyuBGq3x315xapwGYIVYf1mkK5z4Qz8CdvTgKoict7tIWiN7LaBoQnV5SkCrPPhSpXA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=yVB661SF; arc=none smtp.client-ip=209.85.216.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="yVB661SF" Received: by mail-pj1-f47.google.com with SMTP id 98e67ed59e1d1-2e9b55b83d2so3748683a91.3 for ; Tue, 19 Nov 2024 12:30:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1732048252; x=1732653052; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=vRmKVkktJnfpekqs0vaEt2UdODXxii8BcnwHInLLVOw=; b=yVB661SF1mYVKlk0W8aEtptxaOukJtg5bcwEqgL/ka+MiQCvXkURjPs2PxEn0pCGrP scIOtROYNSzEQ3vEBqf2wFbXarl/ej/rr30JfN9mRYQcYL/oIFU5fzpjgeScypMbUtPI Mjfko/JwhcDKoXRDRTk//I0IcN9y/7WVTGeHemw8qEdx8OACeEdRaEle3191byr/EjL+ ncBYwqMjX3g89S3sc3iqzxdnUoqUlXcse2VvesXMFFPn56UuujbBmr6sXCpxBjAcZ5Gz WPGqWP99okCARr+sH97y6Nr8YXQypqyAXtWZ+qd9XIsIalYs/1wXguTaI9Psfc1UIBDt i9Lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732048252; x=1732653052; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vRmKVkktJnfpekqs0vaEt2UdODXxii8BcnwHInLLVOw=; b=srttkNjCnDi7r7VzMpx7JfO+eaG+M1FxgYkdlcMCNJcSXTIrex9qmxgSXKlv5QVKdz dMBHPg7POHdklBZAQVDYcMlEBrHwwE5hTZir5YxRvtGNQ5haKAMtXfen5fSijrvMPQYn yoPY1KqeHGyeoSZ4l8lO54JwN7iY3aXybq8tNv1jnW/5IsD79fRfhq5ooJ5ijzvScWQg Iy5o/uLuTqlY25V3m1rw6WO5gsHZfJ75ZZcpyS4069B+1hXgp6J9xTMk7e2+rZshWvHp NBqZKLg3RGnYitTYpWf/8dJ6NSEM3d+uBHKVJZTUk96SYI0F7ah/SxvqztKp4/aG0ppf nG/w== X-Forwarded-Encrypted: i=1; AJvYcCU+mN1cmd0iN0kilq01sEqLXyY6KCyYG+ydDpe8t4NXSz4FlU5UxkMvSj00EA0JRtkm3w9+KamzLTXxnNw=@vger.kernel.org X-Gm-Message-State: AOJu0YyQOj14Xc/o70eZJdrPp0ShhTtzBzAI3ZdKB2u7omQb2/fm2Wru ASGoQ4hsAwpvs/jMvPqmQVQXyvQ2/okyYLyFpicy/BQHIAiihgQXlEX/Q1UEQi8= X-Google-Smtp-Source: AGHT+IH6B0MvWBP/cFrV+iSzChrNQ92fntZ29A1EV2WF6+w0INOIuuldt7jmoJ2f0P0WCEdUpH78Ag== X-Received: by 2002:a17:90b:3c8e:b0:2ea:61de:38ed with SMTP id 98e67ed59e1d1-2eaca7c9f36mr107313a91.26.1732048252407; Tue, 19 Nov 2024 12:30:52 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-211d0f34f2fsm79001315ad.159.2024.11.19.12.30.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2024 12:30:52 -0800 (PST) From: Atish Patra Date: Tue, 19 Nov 2024 12:29:51 -0800 Subject: [PATCH 3/8] drivers/perf: riscv: Add raw event v2 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241119-pmu_event_info-v1-3-a4f9691421f8@rivosinc.com> References: <20241119-pmu_event_info-v1-0-a4f9691421f8@rivosinc.com> In-Reply-To: <20241119-pmu_event_info-v1-0-a4f9691421f8@rivosinc.com> To: Anup Patel , Will Deacon , Mark Rutland , Paul Walmsley , Palmer Dabbelt , Mayuresh Chitale Cc: linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Atish Patra X-Mailer: b4 0.15-dev-13183 SBI v3.0 introduced a new raw event type that allows wider mhpmeventX width to be programmed via CFG_MATCH. Use the raw event v2 if SBI v3.0 is available. Signed-off-by: Atish Patra --- arch/riscv/include/asm/sbi.h | 4 ++++ drivers/perf/riscv_pmu_sbi.c | 18 ++++++++++++------ 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 9be38b05f4ad..3ee9bfa5e77c 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -159,7 +159,10 @@ struct riscv_pmu_snapshot_data { =20 #define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0) #define RISCV_PMU_PLAT_FW_EVENT_MASK GENMASK_ULL(61, 0) +/* SBI v3.0 allows extended hpmeventX width value */ +#define RISCV_PMU_RAW_EVENT_V2_MASK GENMASK_ULL(55, 0) #define RISCV_PMU_RAW_EVENT_IDX 0x20000 +#define RISCV_PMU_RAW_EVENT_V2_IDX 0x30000 #define RISCV_PLAT_FW_EVENT 0xFFFF =20 /** General pmu event codes specified in SBI PMU extension */ @@ -217,6 +220,7 @@ enum sbi_pmu_event_type { SBI_PMU_EVENT_TYPE_HW =3D 0x0, SBI_PMU_EVENT_TYPE_CACHE =3D 0x1, SBI_PMU_EVENT_TYPE_RAW =3D 0x2, + SBI_PMU_EVENT_TYPE_RAW_V2 =3D 0x3, SBI_PMU_EVENT_TYPE_FW =3D 0xf, }; =20 diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 50cbdbf66bb7..f0e845ff6b79 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -59,7 +59,7 @@ asm volatile(ALTERNATIVE( \ #define PERF_EVENT_FLAG_USER_ACCESS BIT(SYSCTL_USER_ACCESS) #define PERF_EVENT_FLAG_LEGACY BIT(SYSCTL_LEGACY) =20 -PMU_FORMAT_ATTR(event, "config:0-47"); +PMU_FORMAT_ATTR(event, "config:0-55"); PMU_FORMAT_ATTR(firmware, "config:62-63"); =20 static bool sbi_v2_available; @@ -527,18 +527,24 @@ static int pmu_sbi_event_map(struct perf_event *event= , u64 *econfig) break; case PERF_TYPE_RAW: /* - * As per SBI specification, the upper 16 bits must be unused - * for a hardware raw event. + * As per SBI v0.3 specification, + * -- the upper 16 bits must be unused for a hardware raw event. + * As per SBI v3.0 specification, + * -- the upper 8 bits must be unused for a hardware raw event. * Bits 63:62 are used to distinguish between raw events * 00 - Hardware raw event * 10 - SBI firmware events * 11 - Risc-V platform specific firmware event */ - switch (config >> 62) { case 0: - ret =3D RISCV_PMU_RAW_EVENT_IDX; - *econfig =3D config & RISCV_PMU_RAW_EVENT_MASK; + if (sbi_v3_available) { + *econfig =3D config & RISCV_PMU_RAW_EVENT_V2_MASK; + ret =3D RISCV_PMU_RAW_EVENT_V2_IDX; + } else { + *econfig =3D config & RISCV_PMU_RAW_EVENT_MASK; + ret =3D RISCV_PMU_RAW_EVENT_IDX; + } break; case 2: ret =3D (config & 0xFFFF) | (SBI_PMU_EVENT_TYPE_FW << 16); --=20 2.34.1 From nobody Mon Feb 9 17:27:03 2026 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3208516A956 for ; Tue, 19 Nov 2024 20:30:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732048256; cv=none; b=smAcn1Lq2UXfvE3fft+uOJb/KcZ5vfDOJRElXMwZuereyrLDV9pyo6Hj6+/FrVrv3a2tAiPUaomlubCEsuAFVOV6wehCaVSApouONXsmPndMtR9gq1mN1ZM/Nu8cO0Vf1PUgJWR2pXGWF9ooWnuBciUvs//7Z+TNcdNLPAl7pQY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732048256; c=relaxed/simple; bh=rkpDrsA/PVcggHd7+EAEFge1PhxYTYtvQjpCCjdH2MQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FfgvLowwG7zehHJxJ+CdG6xiBWDVMPlPHCP0LY6OM10PRTZ3Oo133EMXAGKBNOf+BvBIqI8LSpP31AwvhqM3/aHtX3RmOR0t8TB8bAahEyvxZbn0ad5bNgGl+jUhjkaaLPBye+CTfpwXZXkWfy08p5Ce3IyEg4RhwIfqD22DY2U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=b4KgB1ok; arc=none smtp.client-ip=209.85.214.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="b4KgB1ok" Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-2124a86f4cbso13654185ad.3 for ; Tue, 19 Nov 2024 12:30:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1732048253; x=1732653053; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=hCeV16Tw9Ue2BbFuxP2Jm0elvtAXwe5u9EmpHjH7wzE=; b=b4KgB1oklVUhjKk1dZMrSuSg+6IsBMa/TBmqo+HzHkgZ9Q4CqdC/d0/LFLNaNyED/x A2igfBBLHuVmVS5PVg9dxqdrYCirnHwoFSnfOFMQbwFrgVuCssHYvJ7rzxO92cpzxtxS tsbCnwcb0V/eQkXb8/XSWeXBmRvPwFqyiMlJRmWGAzeomfsKEzGKylBm77/fo4ilpQpr yViY2ChqgD8nXEIK1xkvu+HmV16jypC2JIY6jhQJLJD0/VmKh60HxGInbqhl49VTVCuh 9z3p3cHrgXzqDP+Szu3kBNrWrpzoDmG4xgDX/1gc9ZNRIx7PbaCxs25iUrsKycCe6ukk jg8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732048253; x=1732653053; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hCeV16Tw9Ue2BbFuxP2Jm0elvtAXwe5u9EmpHjH7wzE=; b=bAn5L9DvMXMhjWBzGi966icgDD+47qMmKuMXobjo61CoUhSNpI/cSmhPryN8bNmv/i Cwq684tHvlWfDUY4s9crVeghgHgAUxzGJ9AjPf9q41NYO+lrZU/k39Ikq7/7F151wB/a tkNOOtsRWbQ6WXgPt9yo6rMaodG+afcGaJ2Oi7xj9yn/yKSHz60jUGwvH6aCFX4yIz6U kqalktkcjxayCgqQVp0ClBOCjYiE2jNoQcCFR9/jiGPZzMA+AP0gLGeS91G6sDKbO5zu CoXPccmHv8JGL1veW58gIZkQ8XzpqVZjDsehju3gUb76uJb2ZdDEwBwrLzD2r381TMcG PMUA== X-Forwarded-Encrypted: i=1; AJvYcCUeGqlXbHpV9eOmS49iSv82fpdix9qhrj2Q5LSi6QytMbKLDJTQWXEdGHMRz4hg2ZRD1kNRplYNrXqfebI=@vger.kernel.org X-Gm-Message-State: AOJu0Yw4215zvscKsgUM41iODZjCIj2qU2y4p2vs2uvGlDCfqtG3w8Zl ZKvDrlxg9dhG9jDyt0LzuBrmDg09cews9qDc+1K3XUkhEhzeEmMSxSQFnezZXZI= X-Google-Smtp-Source: AGHT+IEafgQoRfTXfxDGUyFBcxI9JgtU3iA1K006RwHi5mhUuXe4EdyQsqlE+qS4Y+FQs5c25dBVLA== X-Received: by 2002:a17:902:dac8:b0:211:e812:3948 with SMTP id d9443c01a7336-2126a259979mr4712555ad.0.1732048253488; Tue, 19 Nov 2024 12:30:53 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-211d0f34f2fsm79001315ad.159.2024.11.19.12.30.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2024 12:30:53 -0800 (PST) From: Atish Patra Date: Tue, 19 Nov 2024 12:29:52 -0800 Subject: [PATCH 4/8] RISC-V: KVM: Add support for Raw event v2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241119-pmu_event_info-v1-4-a4f9691421f8@rivosinc.com> References: <20241119-pmu_event_info-v1-0-a4f9691421f8@rivosinc.com> In-Reply-To: <20241119-pmu_event_info-v1-0-a4f9691421f8@rivosinc.com> To: Anup Patel , Will Deacon , Mark Rutland , Paul Walmsley , Palmer Dabbelt , Mayuresh Chitale Cc: linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Atish Patra X-Mailer: b4 0.15-dev-13183 SBI v3.0 introuced a new raw event type v2 for wider mhpmeventX programming. Add the support in kvm for that. Signed-off-by: Atish Patra --- arch/riscv/kvm/vcpu_pmu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index 2707a51b082c..efd66835c2b8 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -60,6 +60,7 @@ static u32 kvm_pmu_get_perf_event_type(unsigned long eidx) type =3D PERF_TYPE_HW_CACHE; break; case SBI_PMU_EVENT_TYPE_RAW: + case SBI_PMU_EVENT_TYPE_RAW_V2: case SBI_PMU_EVENT_TYPE_FW: type =3D PERF_TYPE_RAW; break; @@ -128,6 +129,9 @@ static u64 kvm_pmu_get_perf_event_config(unsigned long = eidx, uint64_t evt_data) case SBI_PMU_EVENT_TYPE_RAW: config =3D evt_data & RISCV_PMU_RAW_EVENT_MASK; break; + case SBI_PMU_EVENT_TYPE_RAW_V2: + config =3D evt_data & RISCV_PMU_RAW_EVENT_V2_MASK; + break; case SBI_PMU_EVENT_TYPE_FW: if (ecode < SBI_PMU_FW_MAX) config =3D (1ULL << 63) | ecode; --=20 2.34.1 From nobody Mon Feb 9 17:27:03 2026 Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A9051D1F6B for ; Tue, 19 Nov 2024 20:30:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732048257; cv=none; b=hIossIHWdEHvZrvIvfqlXWQWRtrjNdFwZhQUmU/JMkGPr9R2PQi0yHdOw8BTgMsEmVq9UA20DGaf/vtnO09HePKwxeXyPM8YsbdZJwCgMTlMBVeoK0ctX54ZyPqDbOxuAzRinqIvC/+9ZLPWlVf7AQ+KBTQb9aGyHtqdxEseTBU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732048257; c=relaxed/simple; bh=5onDZuiSnkP2aXc6vh2wdwjeSxZ8XhBViklh3y0fpJo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WqNCMGbTNJwjGaPNRJVfoezmWuQyKlPkCPlNENnmmsZFJRH5/qhALtl0ZgeSQK+ASbDGXNz4pde4f7gUO8TGs0NMcRBe9uK6Yd9aB7zkOsbheoONxoD2S7O9yljE4ACGCJ3UBhseL4M6jcUtP1Db5of899d5qSqQxCI7HOqL4jA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=OIXZdX4r; arc=none smtp.client-ip=209.85.214.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="OIXZdX4r" Received: by mail-pl1-f170.google.com with SMTP id d9443c01a7336-20cdbe608b3so58945115ad.1 for ; Tue, 19 Nov 2024 12:30:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1732048254; x=1732653054; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=40lt9LB/BTg/O24BZtpczZbDrdTkukX/GA7UpRzp0pg=; b=OIXZdX4rg/67XB2uYoxo+BdiMcIIImmGS3IqXzVpnA02peEDqOaUF4RBSOEXmlkp04 LDZ+uIVlmu0OOf8EaxvdReIksX2jT4014V4Etk4ZCh2L6FM7dwV6HYD2k9LTB/lajm7A wn2IC3BFMqUAMSENK/Y/4m3DL6hlMqrPQ0L8TuOLdaEnwNMYUQhAC85JjNjzTcK+5ioD EZkZrZuNAsNOxLEMrNyXtjyHwZrSbbC5EoYjeAwsCDSKtZOWYw/Btm9cYa9SHzMpPJjg ufRrd3Ctnlb2xcFXu0McPjTFbdlQgenEI9sBAI2sVqKMS65XdxUyAIoOFfH2PYtagJUu yI3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732048254; x=1732653054; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=40lt9LB/BTg/O24BZtpczZbDrdTkukX/GA7UpRzp0pg=; b=pfKRGrAlwjiXKciryrIaENpy8E6TAGlvMGLTLhri3AUgjDwy1z3qngnasoQ9g/DcJ7 8iTzWcoYDO0tdzma8MOHasd1nV9lZ5j9cMUPBe4UOnrn6c9tZ0NGsiJPpMpm5zEDOTDz Zw7zJC0hQ4JD4Kvhzik6jgyKCKaLn9FQVi+uEMmToEm4dbm7fvdJdgrfBtfnMbqmGOzX g/fHGe55qb7SuYtaXDy1PBI3koBIgBJ4yDLy0cL72bvSxmNqnWgzYK8XQUr8ljFWhY1W JFe0ACNg2cArYmu2vxwR1q7x+yQvAtWsV+HXneGat91T+UP500G7Y8d/x7SuwQqOfXEM WonA== X-Forwarded-Encrypted: i=1; AJvYcCVMLutmSwdatvnFDSPGXwrlDsjRT+pHGhYCo7DvCgaMX31mJGW+vzQJw3slAqe0UiZhGVm4/AOrQHT0+Q8=@vger.kernel.org X-Gm-Message-State: AOJu0YySIFzVtKRv3pzKCd0nSQ9vjfRcJ+DmiBlU7vP4sYu7TLPn1Fka jAGNcXRf+G89wpGVOQkkASpXBjPNqH+hQhA75q5Zp+UkQs1A/eeZF73M/mg2qh4= X-Google-Smtp-Source: AGHT+IHsJO0hcJESjwh6eQu7qwaEvcwUlwaSmtArcLLxZHqVuVRuaI9OsGKiZZ86BxWZYDPkCaGZqQ== X-Received: by 2002:a17:902:d2d2:b0:20c:5533:36da with SMTP id d9443c01a7336-2126b381b65mr257415ad.42.1732048254555; Tue, 19 Nov 2024 12:30:54 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-211d0f34f2fsm79001315ad.159.2024.11.19.12.30.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2024 12:30:54 -0800 (PST) From: Atish Patra Date: Tue, 19 Nov 2024 12:29:53 -0800 Subject: [PATCH 5/8] drivers/perf: riscv: Implement PMU event info function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241119-pmu_event_info-v1-5-a4f9691421f8@rivosinc.com> References: <20241119-pmu_event_info-v1-0-a4f9691421f8@rivosinc.com> In-Reply-To: <20241119-pmu_event_info-v1-0-a4f9691421f8@rivosinc.com> To: Anup Patel , Will Deacon , Mark Rutland , Paul Walmsley , Palmer Dabbelt , Mayuresh Chitale Cc: linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Atish Patra X-Mailer: b4 0.15-dev-13183 With the new SBI PMU event info function, we can query the availability of the all standard SBI PMU events at boot time with a single ecall. This improves the bootime by avoiding making an SBI call for each standard PMU event. Since this function is defined only in SBI v3.0, invoke this only if the underlying SBI implementation is v3.0 or higher. Signed-off-by: Atish Patra --- arch/riscv/include/asm/sbi.h | 7 +++++ drivers/perf/riscv_pmu_sbi.c | 71 ++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 78 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 3ee9bfa5e77c..c04f64fbc01d 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -134,6 +134,7 @@ enum sbi_ext_pmu_fid { SBI_EXT_PMU_COUNTER_FW_READ, SBI_EXT_PMU_COUNTER_FW_READ_HI, SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, + SBI_EXT_PMU_EVENT_GET_INFO, }; =20 union sbi_pmu_ctr_info { @@ -157,6 +158,12 @@ struct riscv_pmu_snapshot_data { u64 reserved[447]; }; =20 +struct riscv_pmu_event_info { + u32 event_idx; + u32 output; + u64 event_data; +}; + #define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0) #define RISCV_PMU_PLAT_FW_EVENT_MASK GENMASK_ULL(61, 0) /* SBI v3.0 allows extended hpmeventX width value */ diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index f0e845ff6b79..2a6527cc9d97 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -100,6 +100,7 @@ static unsigned int riscv_pmu_irq; /* Cache the available counters in a bitmask */ static unsigned long cmask; =20 +static int pmu_event_find_cache(u64 config); struct sbi_pmu_event_data { union { union { @@ -299,6 +300,68 @@ static struct sbi_pmu_event_data pmu_cache_event_map[P= ERF_COUNT_HW_CACHE_MAX] }, }; =20 +static int pmu_sbi_check_event_info(void) +{ + int num_events =3D ARRAY_SIZE(pmu_hw_event_map) + PERF_COUNT_HW_CACHE_MAX= * + PERF_COUNT_HW_CACHE_OP_MAX * PERF_COUNT_HW_CACHE_RESULT_MAX; + struct riscv_pmu_event_info *event_info_shmem; + phys_addr_t base_addr; + int i, j, k, result =3D 0, count =3D 0; + struct sbiret ret; + + event_info_shmem =3D (struct riscv_pmu_event_info *) + kcalloc(num_events, sizeof(*event_info_shmem), GFP_KERNEL); + if (!event_info_shmem) { + pr_err("Can not allocate memory for event info query\n"); + return -ENOMEM; + } + + for (i =3D 0; i < ARRAY_SIZE(pmu_hw_event_map); i++) + event_info_shmem[count++].event_idx =3D pmu_hw_event_map[i].event_idx; + + for (i =3D 0; i < ARRAY_SIZE(pmu_cache_event_map); i++) { + for (int j =3D 0; j < ARRAY_SIZE(pmu_cache_event_map[i]); j++) { + for (int k =3D 0; k < ARRAY_SIZE(pmu_cache_event_map[i][j]); k++) + event_info_shmem[count++].event_idx =3D + pmu_cache_event_map[i][j][k].event_idx; + } + } + + base_addr =3D __pa(event_info_shmem); + if (IS_ENABLED(CONFIG_32BIT)) + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_EVENT_GET_INFO, lower_32_bits= (base_addr), + upper_32_bits(base_addr), count, 0, 0, 0); + else + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_EVENT_GET_INFO, base_addr, 0, + count, 0, 0, 0); + if (ret.error) { + result =3D -EOPNOTSUPP; + goto free_mem; + } + /* Do we need some barriers here or priv mode transition will ensure that= */ + for (i =3D 0; i < ARRAY_SIZE(pmu_hw_event_map); i++) { + if (!(event_info_shmem[i].output & 0x01)) + pmu_hw_event_map[i].event_idx =3D -ENOENT; + } + + count =3D ARRAY_SIZE(pmu_hw_event_map); + + for (i =3D 0; i < ARRAY_SIZE(pmu_cache_event_map); i++) { + for (j =3D 0; j < ARRAY_SIZE(pmu_cache_event_map[i]); j++) { + for (k =3D 0; k < ARRAY_SIZE(pmu_cache_event_map[i][j]); k++) { + if (!(event_info_shmem[count].output & 0x01)) + pmu_cache_event_map[i][j][k].event_idx =3D -ENOENT; + count++; + } + } + } + +free_mem: + kfree(event_info_shmem); + + return result; +} + static void pmu_sbi_check_event(struct sbi_pmu_event_data *edata) { struct sbiret ret; @@ -316,6 +379,14 @@ static void pmu_sbi_check_event(struct sbi_pmu_event_d= ata *edata) =20 static void pmu_sbi_check_std_events(struct work_struct *work) { + int ret; + + if (sbi_v3_available) { + ret =3D pmu_sbi_check_event_info(); + if (!ret) + return; + } + for (int i =3D 0; i < ARRAY_SIZE(pmu_hw_event_map); i++) pmu_sbi_check_event(&pmu_hw_event_map[i]); =20 --=20 2.34.1 From nobody Mon Feb 9 17:27:03 2026 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F9511D5CF9 for ; Tue, 19 Nov 2024 20:30:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732048258; cv=none; b=dLE8qd+WJFSxXdfWOJENsdx8ipdnNKPdPYuSfvl+FvR9TMVrGX2ksZpPFRlsx+MGGewZVgmhNpTk0nHcmkFcl8yK7g1Sx1REg3cdfrAt2ZkbAdZwikpkn3MxiFpES2CJRgQ3CnHJtPAVq7IBKCx/4TP73zwNSxEU/GlSv5eiUoA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732048258; c=relaxed/simple; bh=d19CQgPNvBcsQ2Thiefa99k9qqPTIyWGn7bjCj3eHBA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JYLUXSaUwq83QyGnc2bkOE9kZiTyq1kUxCFTSbpySVf7YD66LWykaSzgN4e08NwXCHTpC88jIOksLr+v2hNa4jxq4uKESjeOu2dVRokMHP1fNZo/l0y4JIt0o3+y4kdL4521e/5bKlYtQhZYGMwouRLFdnik1QC/Y+xmX+t/CD4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=MqBkJpn5; arc=none smtp.client-ip=209.85.214.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="MqBkJpn5" Received: by mail-pl1-f169.google.com with SMTP id d9443c01a7336-20c805a0753so13919695ad.0 for ; Tue, 19 Nov 2024 12:30:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1732048255; x=1732653055; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=EvI6ELyRBC+Fyndrrci/LAt1a0lV7o2VMX1QjdFEcW8=; b=MqBkJpn5QNDHy+wljOqirYIG88ONCqUBdaWFNubLra3+LX9NGJ3BFxDhCLNBHYiYNC dKCxhzr6K8ZPP27rg4Zp+ufOqjZ1GspmJZpBbXAeH/8Vm8CVB8KZ/W2h9MZF0fwPEtBt wn5jQ2h8U83akh4LbkKVLmXgmG3A5cP8M+UdO12HOH0+vws8Q/2FiO4LqefcOfL3l4mw kprpnuutUb3ZHdzxRt3utuyjvpsAU7jrYfH4VWp5EFfHQpPG/E2GWpHTqDulqoLiKLDc DrtMOmL+KEo0xvVdJteoGLGoTSsM5b1z2dtoYtGGjZDs3SBooH6bfQSp6ABVBwcdbSwv 0E5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732048255; x=1732653055; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EvI6ELyRBC+Fyndrrci/LAt1a0lV7o2VMX1QjdFEcW8=; b=qPDR6xmd89N4RSUpgw8PM99mPgoqwOkXB6BMem7/NIEeODMJP+gpfA01zy8ThH0ECP V7qu/lGVq8eT8TFOQFFAAM7jjEYjiyApKOug/Fd+wFa1BygXvUl5SN3+vtqloVqT7/D7 hM+QiHeIkRf4TbgYX2Mq2zCNfoTEnS6GHqn6NFrFpvtNR8CjGxDTBnurJGveRsFT11hV ub4evuQbawgRjVVsWjJGubceK/D6etbHVl2uphKV2SNfxnNkXMlc1nRm3sjAzYuWiM8f YVGTtKkneGG8PkrnE85l/7IiLXngAga5VzRNWSMxtvdx0YtzIrUZa0yLluOzTqfK10WG zG6A== X-Forwarded-Encrypted: i=1; AJvYcCWhCgAy7Ez77jZfZIIHv8XtnxVlz3o58HsefzxxrmdIqGeg/Kg63QgAW2iCnw65fk2ACFPj4PVRzm3eBRs=@vger.kernel.org X-Gm-Message-State: AOJu0Ywl/NiOJ4J7zZpDCAJNK0C+jhuc6Q1DkWKKlAmoq764qcQPErhO n4E4CKKgFFm/9tbE60Vla0v/2PHM+Tb0JEKNkDnZ7lLbjJMUvvHlRhyHNWE9YI8= X-Google-Smtp-Source: AGHT+IE8OiqtfXItkGe53z5hjcs0b0CjneyIZkfN6utXnoNwtgLN2RoemxkaTVHNqe744fxPZ0nP9g== X-Received: by 2002:a17:902:d509:b0:212:40e0:9562 with SMTP id d9443c01a7336-2126a3b4478mr2002835ad.25.1732048255602; Tue, 19 Nov 2024 12:30:55 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-211d0f34f2fsm79001315ad.159.2024.11.19.12.30.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2024 12:30:55 -0800 (PST) From: Atish Patra Date: Tue, 19 Nov 2024 12:29:54 -0800 Subject: [PATCH 6/8] drivers/perf: riscv: Export PMU event info function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241119-pmu_event_info-v1-6-a4f9691421f8@rivosinc.com> References: <20241119-pmu_event_info-v1-0-a4f9691421f8@rivosinc.com> In-Reply-To: <20241119-pmu_event_info-v1-0-a4f9691421f8@rivosinc.com> To: Anup Patel , Will Deacon , Mark Rutland , Paul Walmsley , Palmer Dabbelt , Mayuresh Chitale Cc: linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Atish Patra X-Mailer: b4 0.15-dev-13183 The event mapping function can be used in event info function to find out the corresponding SBI PMU event encoding during the get_event_info function as well. Refactor and export it so that it can be invoked from kvm and internal driver. Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 111 ++++++++++++++++++++++---------------= ---- include/linux/perf/riscv_pmu.h | 2 + 2 files changed, 62 insertions(+), 51 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 2a6527cc9d97..8ddd094c82ad 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -414,6 +414,65 @@ static bool pmu_sbi_ctr_is_fw(int cidx) return (info->type =3D=3D SBI_PMU_CTR_TYPE_FW) ? true : false; } =20 +int riscv_pmu_get_event_info(u32 type, u64 config, u64 *econfig) +{ + int ret =3D -ENOENT; + + switch (type) { + case PERF_TYPE_HARDWARE: + if (config >=3D PERF_COUNT_HW_MAX) + return -EINVAL; + ret =3D pmu_hw_event_map[config].event_idx; + break; + case PERF_TYPE_HW_CACHE: + ret =3D pmu_event_find_cache(config); + break; + case PERF_TYPE_RAW: + /* + * As per SBI v0.3 specification, + * -- the upper 16 bits must be unused for a hardware raw event. + * As per SBI v3.0 specification, + * -- the upper 8 bits must be unused for a hardware raw event. + * Bits 63:62 are used to distinguish between raw events + * 00 - Hardware raw event + * 10 - SBI firmware events + * 11 - Risc-V platform specific firmware event + */ + switch (config >> 62) { + case 0: + if (sbi_v3_available) { + if (econfig) + *econfig =3D config & RISCV_PMU_RAW_EVENT_V2_MASK; + ret =3D RISCV_PMU_RAW_EVENT_V2_IDX; + } else { + if (econfig) + *econfig =3D config & RISCV_PMU_RAW_EVENT_MASK; + ret =3D RISCV_PMU_RAW_EVENT_IDX; + } + break; + case 2: + ret =3D (config & 0xFFFF) | (SBI_PMU_EVENT_TYPE_FW << 16); + break; + case 3: + /* + * For Risc-V platform specific firmware events + * Event code - 0xFFFF + * Event data - raw event encoding + */ + ret =3D SBI_PMU_EVENT_TYPE_FW << 16 | RISCV_PLAT_FW_EVENT; + if (econfig) + *econfig =3D config & RISCV_PMU_PLAT_FW_EVENT_MASK; + break; + } + break; + default: + break; + } + + return ret; +} +EXPORT_SYMBOL(riscv_pmu_get_event_info); + /* * Returns the counter width of a programmable counter and number of hardw= are * counters. As we don't support heterogeneous CPUs yet, it is okay to just @@ -579,7 +638,6 @@ static int pmu_sbi_event_map(struct perf_event *event, = u64 *econfig) { u32 type =3D event->attr.type; u64 config =3D event->attr.config; - int ret; =20 /* * Ensure we are finished checking standard hardware events for @@ -587,56 +645,7 @@ static int pmu_sbi_event_map(struct perf_event *event,= u64 *econfig) */ flush_work(&check_std_events_work); =20 - switch (type) { - case PERF_TYPE_HARDWARE: - if (config >=3D PERF_COUNT_HW_MAX) - return -EINVAL; - ret =3D pmu_hw_event_map[event->attr.config].event_idx; - break; - case PERF_TYPE_HW_CACHE: - ret =3D pmu_event_find_cache(config); - break; - case PERF_TYPE_RAW: - /* - * As per SBI v0.3 specification, - * -- the upper 16 bits must be unused for a hardware raw event. - * As per SBI v3.0 specification, - * -- the upper 8 bits must be unused for a hardware raw event. - * Bits 63:62 are used to distinguish between raw events - * 00 - Hardware raw event - * 10 - SBI firmware events - * 11 - Risc-V platform specific firmware event - */ - switch (config >> 62) { - case 0: - if (sbi_v3_available) { - *econfig =3D config & RISCV_PMU_RAW_EVENT_V2_MASK; - ret =3D RISCV_PMU_RAW_EVENT_V2_IDX; - } else { - *econfig =3D config & RISCV_PMU_RAW_EVENT_MASK; - ret =3D RISCV_PMU_RAW_EVENT_IDX; - } - break; - case 2: - ret =3D (config & 0xFFFF) | (SBI_PMU_EVENT_TYPE_FW << 16); - break; - case 3: - /* - * For Risc-V platform specific firmware events - * Event code - 0xFFFF - * Event data - raw event encoding - */ - ret =3D SBI_PMU_EVENT_TYPE_FW << 16 | RISCV_PLAT_FW_EVENT; - *econfig =3D config & RISCV_PMU_PLAT_FW_EVENT_MASK; - break; - } - break; - default: - ret =3D -ENOENT; - break; - } - - return ret; + return riscv_pmu_get_event_info(type, config, econfig); } =20 static void pmu_sbi_snapshot_free(struct riscv_pmu *pmu) diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h index 701974639ff2..4a5e3209c473 100644 --- a/include/linux/perf/riscv_pmu.h +++ b/include/linux/perf/riscv_pmu.h @@ -91,6 +91,8 @@ struct riscv_pmu *riscv_pmu_alloc(void); int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num_hw_ctr); #endif =20 +int riscv_pmu_get_event_info(u32 type, u64 config, u64 *econfig); + #endif /* CONFIG_RISCV_PMU */ =20 #endif /* _RISCV_PMU_H */ --=20 2.34.1 From nobody Mon Feb 9 17:27:03 2026 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF44A1D79B3 for ; Tue, 19 Nov 2024 20:30:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732048260; cv=none; b=n0HS+NAvHHVZVIbXtLDrmsJtzCNiQOImcOoAVXrP0EhaAVBPbzdCxzKVcSDWcmKYXuvGYYij6AvjIfizYlV2Js5sL4STHpgHkx/qjiCn0U3sa0QGoxAuUcyOlYedgH5lb65B2FeLecDs2wTqC4GdNQcC7Iv1fXLOlK/svz/pLkQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732048260; c=relaxed/simple; bh=G5yi3iNf9DP3MtmXZ7tHjmD2q1hrql1veCYCyXy2ahA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aTULBJCC9fWu3uzp2JvyRfnnEQp6yfLCwSl9RT6wQkIcV6G8RIZEVu17yMguvVkfcG/hq8CYAjPB6+kmN94R29maFLo1CfHfI/5d+ffABgRQH/TvJt4Z4LrDJBN9p2TIh1rYsUTaOnK+PNrNzyxZ4eDql+ODNN7IoG0biC+39vQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=G2r91jeA; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="G2r91jeA" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-20cf3e36a76so49725375ad.0 for ; Tue, 19 Nov 2024 12:30:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1732048257; x=1732653057; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=bs99zjzT6d12gvM6MWyIJ6XWCfETAhHft1AvWE2UFvk=; b=G2r91jeA/OQC4RS6mdOaVl+FkMzCE7fuHinMYOjECeEFdAA/Slrc1w2HTsBwxnEx/f 7oCSCbXZNdCkAxUw74tpzD797/7mToCg1MR7XyucGFUtJSbdlV35FE551Dr291pBWFdO hKyIFq7woZ87Cf6uBDWgwCgKuBX1n5tuE7AwuvBuxxx36QeGPDQ1BDY44TFxvl+gSgq2 2V5raGVquJNsNyGDfU/Es8DtUMUtnk/zf30gA5kzM8pLi1vLzSTgzY4EnYtbsrYpi3C3 OrssxWFN/YQS3GrXnUkiAcynEDz4Yx3xX4H3s7WysJoL2Rw7JNEVgQfs6qOTm7+yS9D9 IKQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732048257; x=1732653057; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bs99zjzT6d12gvM6MWyIJ6XWCfETAhHft1AvWE2UFvk=; b=WKQQDTKquzfYXbdm0hS/RMTcIAEuK0+nj9oI73DDfHXPEHoZnYhcoqUdjFUauJM8qu Zs2ON/PfDjO+uP8O53vhkHCmFszYjQMaQvZemWgH+PefrwW0A5F44TipzhEUil2RZt6U 38dIYjQNcyOKLKz4N6yvqj5oMjxyCQdhOqoBakm0ykhEOJrSCzXMYnrpzijcCkDDQUw/ hNxAXntJD9NkQWTle53D0H7T0yx/sIg3/ksXZ/THlrMvVZb5PIHGvaNCOxrSskIH2cel UHVoeuH8q9zcZytHBYkAqbOSQLY9HQDVi7kYQmfanaE1UAC9YbJeIiWQM4eRYqqfkuDC Z55A== X-Forwarded-Encrypted: i=1; AJvYcCWAoMbMaA80yeitfE7tf5rSHWZv4jnE7Z7wV2aBySOJB030Lo+yGjwNjLLw+s1cHI8ASE3YP03tybkpUXk=@vger.kernel.org X-Gm-Message-State: AOJu0Yy3aqZkRZaeGwtD09+jSnIDJ6bGZyvcqe7SSLkKMuBGmaDBxrn1 JdXXKFgwv3qiT8Wtfi2I7uauBPhAVxBNiOkGlYpcK/ZbhvmlAyGKXPj8hnEMYd4sVBB6QfifZ4e i X-Google-Smtp-Source: AGHT+IESHBYfIB+Rw/ycY/laHoMRI9Uw6Iu8jOPbVMITks5jvKXyAK0AlmSBcZiVndbkDkPBOO2Y/A== X-Received: by 2002:a17:903:230d:b0:211:ee35:830c with SMTP id d9443c01a7336-2126a34d311mr3124645ad.15.1732048256798; Tue, 19 Nov 2024 12:30:56 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-211d0f34f2fsm79001315ad.159.2024.11.19.12.30.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2024 12:30:56 -0800 (PST) From: Atish Patra Date: Tue, 19 Nov 2024 12:29:55 -0800 Subject: [PATCH 7/8] RISC-V: KVM: Implement get event info function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241119-pmu_event_info-v1-7-a4f9691421f8@rivosinc.com> References: <20241119-pmu_event_info-v1-0-a4f9691421f8@rivosinc.com> In-Reply-To: <20241119-pmu_event_info-v1-0-a4f9691421f8@rivosinc.com> To: Anup Patel , Will Deacon , Mark Rutland , Paul Walmsley , Palmer Dabbelt , Mayuresh Chitale Cc: linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Atish Patra X-Mailer: b4 0.15-dev-13183 The new get_event_info funciton allows the guest to query the presence of multiple events with single SBI call. Currently, the perf driver in linux guest invokes it for all the standard SBI PMU events. Support the SBI function implementation in KVM as well. Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_vcpu_pmu.h | 3 ++ arch/riscv/kvm/vcpu_pmu.c | 67 +++++++++++++++++++++++++++++++= ++++ arch/riscv/kvm/vcpu_sbi_pmu.c | 3 ++ 3 files changed, 73 insertions(+) diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm= /kvm_vcpu_pmu.h index 1d85b6617508..9a930afc8f57 100644 --- a/arch/riscv/include/asm/kvm_vcpu_pmu.h +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h @@ -98,6 +98,9 @@ void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu); int kvm_riscv_vcpu_pmu_snapshot_set_shmem(struct kvm_vcpu *vcpu, unsigned = long saddr_low, unsigned long saddr_high, unsigned long flags, struct kvm_vcpu_sbi_return *retdata); +int kvm_riscv_vcpu_pmu_event_info(struct kvm_vcpu *vcpu, unsigned long sad= dr_low, + unsigned long saddr_high, unsigned long num_events, + unsigned long flags, struct kvm_vcpu_sbi_return *retdata); void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu); =20 diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index efd66835c2b8..a30f7ec31479 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -456,6 +456,73 @@ int kvm_riscv_vcpu_pmu_snapshot_set_shmem(struct kvm_v= cpu *vcpu, unsigned long s return 0; } =20 +int kvm_riscv_vcpu_pmu_event_info(struct kvm_vcpu *vcpu, unsigned long sad= dr_low, + unsigned long saddr_high, unsigned long num_events, + unsigned long flags, struct kvm_vcpu_sbi_return *retdata) +{ + unsigned long hva; + struct riscv_pmu_event_info *einfo; + int shmem_size =3D num_events * sizeof(*einfo); + bool writable; + gpa_t shmem; + u32 eidx, etype; + u64 econfig; + int ret; + + if (flags !=3D 0 || (saddr_low & (SZ_16 - 1))) { + ret =3D SBI_ERR_INVALID_PARAM; + goto out; + } + + shmem =3D saddr_low; + if (saddr_high !=3D 0) { + if (IS_ENABLED(CONFIG_32BIT)) { + shmem |=3D ((gpa_t)saddr_high << 32); + } else { + ret =3D SBI_ERR_INVALID_ADDRESS; + goto out; + } + } + + hva =3D kvm_vcpu_gfn_to_hva_prot(vcpu, shmem >> PAGE_SHIFT, &writable); + if (kvm_is_error_hva(hva) || !writable) { + ret =3D SBI_ERR_INVALID_ADDRESS; + goto out; + } + + einfo =3D kzalloc(shmem_size, GFP_KERNEL); + if (!einfo) + return -ENOMEM; + + ret =3D kvm_vcpu_read_guest(vcpu, shmem, einfo, shmem_size); + if (ret) { + ret =3D SBI_ERR_FAILURE; + goto free_mem; + } + + for (int i =3D 0; i < num_events; i++) { + eidx =3D einfo[i].event_idx; + etype =3D kvm_pmu_get_perf_event_type(eidx); + econfig =3D kvm_pmu_get_perf_event_config(eidx, einfo[i].event_data); + ret =3D riscv_pmu_get_event_info(etype, econfig, NULL); + if (ret > 0) + einfo[i].output =3D 1; + } + + kvm_vcpu_write_guest(vcpu, shmem, einfo, shmem_size); + if (ret) { + ret =3D SBI_ERR_FAILURE; + goto free_mem; + } + +free_mem: + kfree(einfo); +out: + retdata->err_val =3D ret; + + return 0; +} + int kvm_riscv_vcpu_pmu_num_ctrs(struct kvm_vcpu *vcpu, struct kvm_vcpu_sbi_return *retdata) { diff --git a/arch/riscv/kvm/vcpu_sbi_pmu.c b/arch/riscv/kvm/vcpu_sbi_pmu.c index e4be34e03e83..a020d979d179 100644 --- a/arch/riscv/kvm/vcpu_sbi_pmu.c +++ b/arch/riscv/kvm/vcpu_sbi_pmu.c @@ -73,6 +73,9 @@ static int kvm_sbi_ext_pmu_handler(struct kvm_vcpu *vcpu,= struct kvm_run *run, case SBI_EXT_PMU_SNAPSHOT_SET_SHMEM: ret =3D kvm_riscv_vcpu_pmu_snapshot_set_shmem(vcpu, cp->a0, cp->a1, cp->= a2, retdata); break; + case SBI_EXT_PMU_EVENT_GET_INFO: + ret =3D kvm_riscv_vcpu_pmu_event_info(vcpu, cp->a0, cp->a1, cp->a2, cp->= a3, retdata); + break; default: retdata->err_val =3D SBI_ERR_NOT_SUPPORTED; } --=20 2.34.1 From nobody Mon Feb 9 17:27:03 2026 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87DD71D7E5F for ; Tue, 19 Nov 2024 20:30:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732048260; cv=none; b=r7Hb6+MZ5e0hQ1I9ZbR0uKeawckdrji7mzKNhf2bkBHxkc4W+fmd6bZXRLld13OcaypU72+4QD54qqqmVgi8Vj6I8R84U5uex767mducOaaitdAdQfln/YjL+wRlrKvA7HMIwdKCpXKX8osCJUKXxxn67z/FZFCpOsSMN4UKu+M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732048260; c=relaxed/simple; bh=I61ANzW3mMGNw+TsEklnF5HMFHS9Ft60jqTehlaG7hM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Pq43GY1NmFRY9KGKdTjNzyy0MM8BGLnRqrbuiBA6qgWHs7LPSbMwnTbpID6CIXey/UoyHiBWvrbSL5UMFOnvbDpYeSGG2fP3+5DErHrKgJXyXBtS8w/gSXKlGPLkIOFEskcAu4mvxO0YqXRytJ/mIzafAV24PLI75tAxz5arddg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=Ayez7NoG; arc=none smtp.client-ip=209.85.214.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="Ayez7NoG" Received: by mail-pl1-f175.google.com with SMTP id d9443c01a7336-212008b0d6eso29111065ad.3 for ; Tue, 19 Nov 2024 12:30:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1732048258; x=1732653058; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=oS1moOcp9ct9rXCWQSjf/GhpQtGR0rWY3wjXVfG0zao=; b=Ayez7NoGQMC9UcHgiyewYOdCCbHkBpWpfNnPlD4oJkCVCqo6aySmmHdCUC+kj0dNYv IT/9SpjthbtWdrsPnBv1kpHKQeEO1GlcUJlTUY0mRFcLJjE6btuC2l7iQ5F/QxMKAlKv o/APu6wZLBpE2CcFYmkWxJ1EIUKEfTV0Dpmx8j5RI+TfkV0Ppd2ff8JdVxnLTAg52pGG BThnI/HKmh7yfhWwZdp80HJa5GomB1DcdtWtrhop40ItRulHCA/PMh7rfhq9k/Y4l9CX PdcxIX2SgwN1c+wjEgGlqXMKbfX1hyik0ZyBqu/rE51dgQeHOIECbN1dVeMnp/woa7DF 5aFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732048258; x=1732653058; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oS1moOcp9ct9rXCWQSjf/GhpQtGR0rWY3wjXVfG0zao=; b=oZsiMBz/IGqp9lSexaRE6W44F9qqDp2c7tp3OR/Gm64lJS3sJ4mdoYYNrEBibyNECC f6ffTx/PdATYDmd78OWL+tvjnBfhgGZpPb7mGHXM+QPDnEzJd8frX829OnggVZbmIZCo VXKrO6QbRplT0isCBd90D1BUY3GeVjt5GL/ajkpDV1FjGqTEeQZH4RTXjpgzINopa+iq Lq9giUjl77AAoueGR85sv9kb9sqqnJBaogFRT9zBwW9iBjYajzQOr7U3tV5zU0WsMXiU NFYbVjnmvJFORfiU+j6zGqrMNRgL1U+J6I5OXpzIJG6n/OQTcd81VNZVf/E9kT3wlYpW heeQ== X-Forwarded-Encrypted: i=1; AJvYcCWW2ttfLLUkTVf4XAk3bCwk8fpLTWnRj/PuGe5knD2xB1l4evRZsU06rnAPhIc9s3IkYVwrorP5Cylgw+A=@vger.kernel.org X-Gm-Message-State: AOJu0YyL2BksQOfEezoD3YJa5e5PW9sbswWeLzA0t+Rv0Ia2AWGPezvY guGEv7Rs+vUbEMG6XTcTfh81nUveB8kjZfgc1SGpJ9c4W+JTCSvY5luibuDV0r4= X-Google-Smtp-Source: AGHT+IHJJKUj/G9a1vcUatY4x43+GcKI1AsZDcQ+KjFbu3ubgI0Q6fpviZE7gWtG38yqh7oUq4m8sw== X-Received: by 2002:a17:902:dad0:b0:20b:7210:5859 with SMTP id d9443c01a7336-2126b07a574mr1668385ad.38.1732048257883; Tue, 19 Nov 2024 12:30:57 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-211d0f34f2fsm79001315ad.159.2024.11.19.12.30.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2024 12:30:57 -0800 (PST) From: Atish Patra Date: Tue, 19 Nov 2024 12:29:56 -0800 Subject: [PATCH 8/8] RISC-V: KVM: Upgrade the supported SBI version to 3.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241119-pmu_event_info-v1-8-a4f9691421f8@rivosinc.com> References: <20241119-pmu_event_info-v1-0-a4f9691421f8@rivosinc.com> In-Reply-To: <20241119-pmu_event_info-v1-0-a4f9691421f8@rivosinc.com> To: Anup Patel , Will Deacon , Mark Rutland , Paul Walmsley , Palmer Dabbelt , Mayuresh Chitale Cc: linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Atish Patra X-Mailer: b4 0.15-dev-13183 Upgrade the SBI version to v3.0 so that corresponding features can be enabled in the guest. Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_vcpu_sbi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm= /kvm_vcpu_sbi.h index b96705258cf9..239457b864d7 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -11,7 +11,7 @@ =20 #define KVM_SBI_IMPID 3 =20 -#define KVM_SBI_VERSION_MAJOR 2 +#define KVM_SBI_VERSION_MAJOR 3 #define KVM_SBI_VERSION_MINOR 0 =20 enum kvm_riscv_sbi_ext_status { --=20 2.34.1