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charset="utf-8" FEAT_BBM level 2 is useful to split large page table without breaking the page table entry. The following patch will use to improve performance. Detect it in cpufeature and use BOOT_CPU feature for now, if the late CPU cores have conflict, kernel will not bring them up. Signed-off-by: Yang Shi --- arch/arm64/include/asm/cpufeature.h | 15 +++++++++++++++ arch/arm64/kernel/cpufeature.c | 11 +++++++++++ arch/arm64/tools/cpucaps | 1 + 3 files changed, 27 insertions(+) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/c= pufeature.h index 3d261cc123c1..c7ca5f9f88bb 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -838,6 +838,21 @@ static inline bool system_supports_poe(void) alternative_has_cap_unlikely(ARM64_HAS_S1POE); } =20 +static inline bool system_supports_bbmlv2(void) +{ + return cpus_have_final_boot_cap(ARM64_HAS_BBMLV2); +} + +static inline bool bbmlv2_available(void) +{ + u64 mmfr2; + u32 bbm; + + mmfr2 =3D read_sanitised_ftr_reg(SYS_ID_AA64MMFR2_EL1); + bbm =3D cpuid_feature_extract_unsigned_field(mmfr2, ID_AA64MMFR2_EL1_BBM_= SHIFT); + return bbm =3D=3D ID_AA64MMFR2_EL1_BBM_2; +} + int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt); bool try_emulate_mrs(struct pt_regs *regs, u32 isn); =20 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 718728a85430..cb916747cd31 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1866,6 +1866,11 @@ static bool has_lpa2(const struct arm64_cpu_capabili= ties *entry, int scope) } #endif =20 +static bool has_bbmlv2(const struct arm64_cpu_capabilities *entry, int sco= pe) +{ + return bbmlv2_available(); +} + #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT)) =20 @@ -2890,6 +2895,12 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) }, #endif + { + .desc =3D "BBM Level 2", + .capability =3D ARM64_HAS_BBMLV2, + .type =3D ARM64_CPUCAP_BOOT_CPU_FEATURE, + .matches =3D has_bbmlv2, + }, {}, }; =20 diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index eedb5acc21ed..175b7eb42b0b 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -14,6 +14,7 @@ HAS_ADDRESS_AUTH_ARCH_QARMA5 HAS_ADDRESS_AUTH_IMP_DEF HAS_AMU_EXTN HAS_ARMv8_4_TTL +HAS_BBMLV2 HAS_CACHE_DIC HAS_CACHE_IDC HAS_CNP --=20 2.41.0