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charset="utf-8" FEAT_BBM level 2 is useful to split large page table without breaking the page table entry. The following patch will use to improve performance. Detect it in cpufeature and use BOOT_CPU feature for now, if the late CPU cores have conflict, kernel will not bring them up. Signed-off-by: Yang Shi --- arch/arm64/include/asm/cpufeature.h | 15 +++++++++++++++ arch/arm64/kernel/cpufeature.c | 11 +++++++++++ arch/arm64/tools/cpucaps | 1 + 3 files changed, 27 insertions(+) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/c= pufeature.h index 3d261cc123c1..c7ca5f9f88bb 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -838,6 +838,21 @@ static inline bool system_supports_poe(void) alternative_has_cap_unlikely(ARM64_HAS_S1POE); } =20 +static inline bool system_supports_bbmlv2(void) +{ + return cpus_have_final_boot_cap(ARM64_HAS_BBMLV2); +} + +static inline bool bbmlv2_available(void) +{ + u64 mmfr2; + u32 bbm; + + mmfr2 =3D read_sanitised_ftr_reg(SYS_ID_AA64MMFR2_EL1); + bbm =3D cpuid_feature_extract_unsigned_field(mmfr2, ID_AA64MMFR2_EL1_BBM_= SHIFT); + return bbm =3D=3D ID_AA64MMFR2_EL1_BBM_2; +} + int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt); bool try_emulate_mrs(struct pt_regs *regs, u32 isn); =20 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 718728a85430..cb916747cd31 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1866,6 +1866,11 @@ static bool has_lpa2(const struct arm64_cpu_capabili= ties *entry, int scope) } #endif =20 +static bool has_bbmlv2(const struct arm64_cpu_capabilities *entry, int sco= pe) +{ + return bbmlv2_available(); +} + #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT)) =20 @@ -2890,6 +2895,12 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) }, #endif + { + .desc =3D "BBM Level 2", + .capability =3D ARM64_HAS_BBMLV2, + .type =3D ARM64_CPUCAP_BOOT_CPU_FEATURE, + .matches =3D has_bbmlv2, + }, {}, }; =20 diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index eedb5acc21ed..175b7eb42b0b 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -14,6 +14,7 @@ HAS_ADDRESS_AUTH_ARCH_QARMA5 HAS_ADDRESS_AUTH_IMP_DEF HAS_AMU_EXTN HAS_ARMv8_4_TTL +HAS_BBMLV2 HAS_CACHE_DIC HAS_CACHE_IDC HAS_CNP --=20 2.41.0 From nobody Sun Nov 24 05:03:14 2024 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11023129.outbound.protection.outlook.com [40.93.201.129]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 606A21DF278 for ; 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charset="utf-8" When rodata=3Dfull is specified, kernel linear mapping has to be mapped at PTE level since large page table can't be split due to break-before-make rule on ARM64. This resulted in a couple of problems: - performance degradation - more TLB pressure - memory waste for kernel page table With FEAT_BBM level 2 support, splitting large block page table to smaller ones doesn't need to make the page table entry invalid anymore. This allows kernel split large block mapping on the fly. Add kernel page table split support and use large block mapping by default when FEAT_BBM level 2 is supported for rodata=3Dfull. When changing permissions for kernel linear mapping, the page table will be split to PTE level. The machine without FEAT_BBM level 2 will fallback to have kernel linear mapping PTE-mapped when rodata=3Dfull. With this we saw significant performance boost with some benchmarks and much less memory consumption on my AmpereOne machine (192 cores, 1P) with 256GB memory. * Memory use after boot Before: MemTotal: 258988984 kB MemFree: 254821700 kB After: MemTotal: 259505132 kB MemFree: 255410264 kB Around 500MB more memory are free to use. The larger the machine, the more memory saved. * Memcached We saw performance degradation when running Memcached benchmark with rodata=3Dfull vs rodata=3Don. Our profiling pointed to kernel TLB pressure. With this patchset we saw ops/sec is increased by around 3.5%, P99 latency is reduced by around 9.6%. The gain mainly came from reduced kernel TLB misses. The kernel TLB MPKI is reduced by 28.5%. The benchmark data is now on par with rodata=3Don too. * Disk encryption (dm-crypt) benchmark Ran fio benchmark with the below command on a 128G ramdisk (ext4) with disk encryption (by dm-crypt). fio --directory=3D/data --random_generator=3Dlfsr --norandommap --randrepea= t 1 \ --status-interval=3D999 --rw=3Dwrite --bs=3D4k --loops=3D1 --ioengine= =3Dsync \ --iodepth=3D1 --numjobs=3D1 --fsync_on_close=3D1 --group_reporting --th= read \ --name=3Diops-test-job --eta-newline=3D1 --size 100G The IOPS is increased by 90% - 150% (the variance is high, but the worst number of good case is around 90% more than the best number of bad case). The bandwidth is increased and the avg clat is reduced proportionally. * Sequential file read Read 100G file sequentially on XFS (xfs_io read with page cache populated). The bandwidth is increased by 150%. Keep using PTE mapping when pagealloc debug is enabled. It is not worth the complexity. Kfence can be converted to use page block mapping later. Signed-off-by: Yang Shi --- arch/arm64/include/asm/pgtable.h | 7 +- arch/arm64/mm/mmu.c | 31 +++++- arch/arm64/mm/pageattr.c | 173 +++++++++++++++++++++++++++++-- 3 files changed, 202 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgta= ble.h index c329ea061dc9..473c133ce10c 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -750,7 +750,7 @@ static inline bool in_swapper_pgdir(void *addr) ((unsigned long)swapper_pg_dir & PAGE_MASK); } =20 -static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) +static inline void __set_pmd_nosync(pmd_t *pmdp, pmd_t pmd) { #ifdef __PAGETABLE_PMD_FOLDED if (in_swapper_pgdir(pmdp)) { @@ -760,6 +760,11 @@ static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) #endif /* __PAGETABLE_PMD_FOLDED */ =20 WRITE_ONCE(*pmdp, pmd); +} + +static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) +{ + __set_pmd_nosync(pmdp, pmd); =20 if (pmd_valid(pmd)) { dsb(ishst); diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index e55b02fbddc8..09ccb4f8964a 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -620,6 +620,18 @@ static inline void arm64_kfence_map_pool(phys_addr_t k= fence_pool, pgd_t *pgdp) { =20 #endif /* CONFIG_KFENCE */ =20 +static inline bool force_pte_mapping(void) +{ + /* + * Can't use cpufeature API to determine whether BBM level 2 + * is supported or not since cpufeature have not been + * finalized yet. + */ + return (rodata_full && !bbmlv2_available()) || + debug_pagealloc_enabled() || + arm64_kfence_can_set_direct_map(); +} + static void __init map_mem(pgd_t *pgdp) { static const u64 direct_map_end =3D _PAGE_END(VA_BITS_MIN); @@ -645,9 +657,21 @@ static void __init map_mem(pgd_t *pgdp) =20 early_kfence_pool =3D arm64_kfence_alloc_pool(); =20 - if (can_set_direct_map()) + if (force_pte_mapping()) flags |=3D NO_BLOCK_MAPPINGS | NO_CONT_MAPPINGS; =20 + /* + * With FEAT_BBM level 2 we can split large block mapping without + * making it invalid. So kernel linear mapping can be mapped with + * large block instead of PTE level. + * + * Need to break cont for CONT_MAPPINGS when changing permission, + * and need to inspect the adjacent page table entries to make + * them cont again later. It sounds not worth the complexity. + */ + if (rodata_full) + flags |=3D NO_CONT_MAPPINGS; + /* * Take care not to create a writable alias for the * read-only text and rodata sections of the kernel image. @@ -1342,9 +1366,12 @@ int arch_add_memory(int nid, u64 start, u64 size, =20 VM_BUG_ON(!mhp_range_allowed(start, size, true)); =20 - if (can_set_direct_map()) + if (force_pte_mapping()) flags |=3D NO_BLOCK_MAPPINGS | NO_CONT_MAPPINGS; =20 + if (rodata_full) + flags |=3D NO_CONT_MAPPINGS; + __create_pgd_mapping(swapper_pg_dir, start, __phys_to_virt(start), size, params->pgprot, __pgd_pgtable_alloc, flags); diff --git a/arch/arm64/mm/pageattr.c b/arch/arm64/mm/pageattr.c index 0e270a1c51e6..dbb2b709d184 100644 --- a/arch/arm64/mm/pageattr.c +++ b/arch/arm64/mm/pageattr.c @@ -45,6 +45,145 @@ static int change_page_range(pte_t *ptep, unsigned long= addr, void *data) return 0; } =20 +static int __split_linear_mapping_pmd(pud_t *pudp, + unsigned long vaddr, unsigned long end) +{ + pmd_t *pmdp; + unsigned long next; + + pmdp =3D pmd_offset(pudp, vaddr); + + do { + next =3D pmd_addr_end(vaddr, end); + + if (pmd_leaf(pmdp_get(pmdp))) { + struct page *pte_page; + unsigned long pfn =3D pmd_pfn(pmdp_get(pmdp)); + pgprot_t prot =3D pmd_pgprot(pmdp_get(pmdp)); + pte_t *ptep_new; + int i; + + pte_page =3D alloc_page(GFP_KERNEL); + if (!pte_page) + return -ENOMEM; + + prot =3D __pgprot(pgprot_val(prot) | PTE_TYPE_PAGE); + ptep_new =3D (pte_t *)page_address(pte_page); + for (i =3D 0; i < PTRS_PER_PTE; ++i, ++ptep_new) + __set_pte_nosync(ptep_new, + pfn_pte(pfn + i, prot)); + + dsb(ishst); + isb(); + + set_pmd(pmdp, pfn_pmd(page_to_pfn(pte_page), + __pgprot(PMD_TYPE_TABLE))); + } + } while (pmdp++, vaddr =3D next, vaddr !=3D end); + + return 0; +} + +static int __split_linear_mapping_pud(p4d_t *p4dp, + unsigned long vaddr, unsigned long end) +{ + pud_t *pudp; + unsigned long next; + int ret; + + pudp =3D pud_offset(p4dp, vaddr); + + do { + next =3D pud_addr_end(vaddr, end); + + if (pud_leaf(pudp_get(pudp))) { + struct page *pmd_page; + unsigned long pfn =3D pud_pfn(pudp_get(pudp)); + pgprot_t prot =3D pud_pgprot(pudp_get(pudp)); + pmd_t *pmdp_new; + int i; + unsigned int step; + + pmd_page =3D alloc_page(GFP_KERNEL); + if (!pmd_page) + return -ENOMEM; + + pmdp_new =3D (pmd_t *)page_address(pmd_page); + for (i =3D 0; i < PTRS_PER_PMD; ++i, ++pmdp_new) { + step =3D (i * PMD_SIZE) >> PAGE_SHIFT; + __set_pmd_nosync(pmdp_new, + pfn_pmd(pfn + step, prot)); + } + + dsb(ishst); + isb(); + + set_pud(pudp, pfn_pud(page_to_pfn(pmd_page), + __pgprot(PUD_TYPE_TABLE))); + } + + ret =3D __split_linear_mapping_pmd(pudp, vaddr, next); + if (ret) + return ret; + } while (pudp++, vaddr =3D next, vaddr !=3D end); + + return 0; +} + +static int __split_linear_mapping_p4d(pgd_t *pgdp, + unsigned long vaddr, unsigned long end) +{ + p4d_t *p4dp; + unsigned long next; + int ret; + + p4dp =3D p4d_offset(pgdp, vaddr); + + do { + next =3D p4d_addr_end(vaddr, end); + + ret =3D __split_linear_mapping_pud(p4dp, vaddr, next); + if (ret) + return ret; + } while (p4dp++, vaddr =3D next, vaddr !=3D end); + + return 0; +} + +static int __split_linear_mapping_pgd(pgd_t *pgdp, + unsigned long vaddr, + unsigned long end) +{ + unsigned long next; + int ret =3D 0; + + mmap_write_lock(&init_mm); + + do { + next =3D pgd_addr_end(vaddr, end); + ret =3D __split_linear_mapping_p4d(pgdp, vaddr, next); + if (ret) + break; + } while (pgdp++, vaddr =3D next, vaddr !=3D end); + + mmap_write_unlock(&init_mm); + + return ret; +} + +static int split_linear_mapping(unsigned long start, unsigned long end) +{ + int ret; + + if (!system_supports_bbmlv2()) + return 0; + + ret =3D __split_linear_mapping_pgd(pgd_offset_k(start), start, end); + flush_tlb_kernel_range(start, end); + + return ret; +} + /* * This function assumes that the range is mapped with PAGE_SIZE pages. */ @@ -70,8 +209,9 @@ static int change_memory_common(unsigned long addr, int = numpages, unsigned long start =3D addr; unsigned long size =3D PAGE_SIZE * numpages; unsigned long end =3D start + size; + unsigned long l_start; struct vm_struct *area; - int i; + int i, ret; =20 if (!PAGE_ALIGNED(addr)) { start &=3D PAGE_MASK; @@ -108,7 +248,12 @@ static int change_memory_common(unsigned long addr, in= t numpages, if (rodata_full && (pgprot_val(set_mask) =3D=3D PTE_RDONLY || pgprot_val(clear_mask) =3D=3D PTE_RDONLY)) { for (i =3D 0; i < area->nr_pages; i++) { - __change_memory_common((u64)page_address(area->pages[i]), + l_start =3D (u64)page_address(area->pages[i]); + ret =3D split_linear_mapping(l_start, l_start + PAGE_SIZE); + if (WARN_ON_ONCE(ret)) + return ret; + + __change_memory_common(l_start, PAGE_SIZE, set_mask, clear_mask); } } @@ -164,6 +309,9 @@ int set_memory_valid(unsigned long addr, int numpages, = int enable) =20 int set_direct_map_invalid_noflush(struct page *page) { + unsigned long l_start; + int ret; + struct page_change_data data =3D { .set_mask =3D __pgprot(0), .clear_mask =3D __pgprot(PTE_VALID), @@ -172,13 +320,21 @@ int set_direct_map_invalid_noflush(struct page *page) if (!can_set_direct_map()) return 0; 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charset="utf-8" FEAT_BBM level 2 is not advertised on AmpereOne because of a bug when collapsing stage 2 mappings from smaller to larger translations. That doesn't impact splitting stage 1 mappings (whether stage 2 is enabled or not), so workaround it by detecting CPUID. Signed-off-by: Yang Shi Reviewed-by: Christoph Lameter --- arch/arm64/include/asm/cpufeature.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/c= pufeature.h index c7ca5f9f88bb..d9b20eb43d31 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -847,10 +847,19 @@ static inline bool bbmlv2_available(void) { u64 mmfr2; u32 bbm; + static const struct midr_range ampereone[] =3D { + MIDR_ALL_VERSIONS(MIDR_AMPERE1), + MIDR_ALL_VERSIONS(MIDR_AMPERE1A), + {} + }; =20 mmfr2 =3D read_sanitised_ftr_reg(SYS_ID_AA64MMFR2_EL1); bbm =3D cpuid_feature_extract_unsigned_field(mmfr2, ID_AA64MMFR2_EL1_BBM_= SHIFT); - return bbm =3D=3D ID_AA64MMFR2_EL1_BBM_2; + if ((bbm =3D=3D ID_AA64MMFR2_EL1_BBM_2) || + is_midr_in_range_list(read_cpuid_id(), ampereone)) + return true; + + return false; } =20 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt); --=20 2.41.0