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charset="utf-8" From: Krishna chaitanya chundru Add dedicated schema for the PCIe controllers found on QCS615. Signed-off-by: Krishna chaitanya chundru Signed-off-by: Ziyue Zhang --- .../devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-p= hy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.= yaml index dcf4fa55fbba..d13eb46adbbb 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -16,6 +16,7 @@ description: properties: compatible: enum: + - qcom,qcs615-qmp-gen3x1-pcie-phy - qcom,sa8775p-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x4-pcie-phy - qcom,sc8180x-qmp-pcie-phy @@ -168,6 +169,7 @@ allOf: compatible: contains: enum: + - qcom,qcs615-qmp-gen3x1-pcie-phy - qcom,sc8280xp-qmp-gen3x1-pcie-phy - qcom,sc8280xp-qmp-gen3x2-pcie-phy - qcom,sc8280xp-qmp-gen3x4-pcie-phy --=20 2.34.1 From nobody Sat Nov 23 12:01:12 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C350D14A08E; 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charset="utf-8" From: Krishna chaitanya chundru Add support for GEN3 x1 PCIe PHY found on Qualcomm QCS615 platform. Signed-off-by: Krishna chaitanya chundru Signed-off-by: Ziyue Zhang --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 105 +++++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h | 1 + 2 files changed, 106 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index f71787fb4d7e..df82f95a1fa2 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -726,6 +726,83 @@ static const struct qmp_phy_init_tbl ipq9574_gen3x2_pc= ie_pcs_misc_tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), }; =20 +static const struct qmp_phy_init_tbl qcs615_pcie_serdes_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), + QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x9), + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x4), + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x35), + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x4), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x30), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), +}; + +static const struct qmp_phy_init_tbl qcs615_pcie_rx_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x4), +}; + +static const struct qmp_phy_init_tbl qcs615_pcie_tx_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), + QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), + QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), +}; + +static const struct qmp_phy_init_tbl qcs615_pcie_pcs_tbl[] =3D { + QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_SIGDET_CNTRL, 0x7), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe), +}; + static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), @@ -2963,6 +3040,31 @@ static const struct qmp_phy_cfg ipq9574_gen3x2_pciep= hy_cfg =3D { .pipe_clock_rate =3D 250000000, }; =20 +static const struct qmp_phy_cfg qcs615_pciephy_cfg =3D { + .lanes =3D 1, + + .offsets =3D &qmp_pcie_offsets_v2, + + .tbls =3D { + .serdes =3D qcs615_pcie_serdes_tbl, + .serdes_num =3D ARRAY_SIZE(qcs615_pcie_serdes_tbl), + .tx =3D qcs615_pcie_tx_tbl, + .tx_num =3D ARRAY_SIZE(qcs615_pcie_tx_tbl), + .rx =3D qcs615_pcie_rx_tbl, + .rx_num =3D ARRAY_SIZE(qcs615_pcie_rx_tbl), + .pcs =3D qcs615_pcie_pcs_tbl, + .pcs_num =3D ARRAY_SIZE(qcs615_pcie_pcs_tbl), + }, + .reset_list =3D sdm845_pciephy_reset_l, + .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .regs =3D pciephy_v2_regs_layout, + + .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status =3D PHYSTATUS, +}; + static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg =3D { .lanes =3D 1, =20 @@ -4400,6 +4502,9 @@ static const struct of_device_id qmp_pcie_of_match_ta= ble[] =3D { }, { .compatible =3D "qcom,msm8998-qmp-pcie-phy", .data =3D &msm8998_pciephy_cfg, + }, { + .compatible =3D "qcom,qcs615-qmp-gen3x1-pcie-phy", + .data =3D &qcs615_pciephy_cfg, }, { .compatible =3D "qcom,sa8775p-qmp-gen4x2-pcie-phy", .data =3D &sa8775p_qmp_gen4x2_pciephy_cfg, diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h b/drivers/phy/qualc= omm/phy-qcom-qmp-pcs-v2.h index bf36399d0057..1ecf4b5beba6 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h @@ -34,6 +34,7 @@ #define QPHY_V2_PCS_USB_PCS_STATUS 0x17c /* USB */ #define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8 #define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac +#define QPHY_V2_PCS_SIGDET_CNTRL 0x1b0 #define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8 #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 --=20 2.34.1 From nobody Sat Nov 23 12:01:12 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C34BE1DFED; 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charset="utf-8" From: Krishna chaitanya chundru Add dedicated schema for the PCIe controllers found on QCS615. A new compatible for qcs615 is needed, for we do not find the similar one which is ok to use. Signed-off-by: Krishna chaitanya chundru Signed-off-by: Ziyue Zhang --- .../bindings/pci/qcom,pcie-qcs615.yaml | 161 ++++++++++++++++++ 1 file changed, 161 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-qcs615.= yaml diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-qcs615.yaml b/= Documentation/devicetree/bindings/pci/qcom,pcie-qcs615.yaml new file mode 100644 index 000000000000..8f7571538d23 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-qcs615.yaml @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-qcs615.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QCS615 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm QCS615 SoC (and compatible) PCIe root complex controller is bas= ed on + the Synopsys DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-qcs615 + + reg: + minItems: 6 + maxItems: 6 + + reg-names: + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 6 + maxItems: 6 + + clock-names: + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ref # REFERENCE clock + + interrupts: + minItems: 9 + maxItems: 9 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + - const: global + + resets: + minItems: 1 + maxItems: 1 + + reset-names: + items: + - const: pci # PCIe core reset + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@1c08000 { + compatible =3D "qcom,pcie-qcs615"; + reg =3D <0 0x01c08000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>, + <0 0x01c0b000 0 0x1000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config", "mhi"; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100= 000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x3d000= 00>; + + bus-range =3D <0x00 0xff>; + device_type =3D "pci"; + linux,pci-domain =3D <0>; + num-lanes =3D <1>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref"; + + dma-coherent; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7", "global"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH= >, /* int_a */ + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,= /* int_b */ + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,= /* int_c */ + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;= /* int_d */ + + interconnects =3D <&agree1_noc MASTER_PCIE 0 &mc_virt SLAVE_EB= I1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE= _PCIE_0 0>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + iommu-map =3D <0x0 &apps_smmu 0x400 0x1>, + <0x100 &apps_smmu 0x401 0x1>; + + phys =3D <&pcie_phy>; + phy-names =3D "pciephy"; + + pinctrl-0 =3D <&pcie_default_state>; + pinctrl-names =3D "default"; + + power-domains =3D <&gcc PCIE_0_GDSC>; + + resets =3D <&gcc GCC_PCIE_0_BCR>; + reset-names =3D "pci"; + + perst-gpios =3D <&tlmm 101 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 100 GPIO_ACTIVE_HIGH>; + }; + }; --=20 2.34.1 From nobody Sat Nov 23 12:01:12 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1DA515250F; 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charset="utf-8" From: Krishna chaitanya chundru Add the compatible and the driver data for QCS615 PCIe controller. There is only one controller instance found on this platform, out of which is Gen3 with speeds of up to 8.0GT/s. The version of the controller is 1.38.0 for all instances, but they are compatible with 1.9.0 config. Signed-off-by: Krishna chaitanya chundru Signed-off-by: Ziyue Zhang --- drivers/pci/controller/dwc/pcie-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index ef44a82be058..da7200b56b1e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1830,6 +1830,7 @@ static const struct of_device_id qcom_pcie_match[] = =3D { { .compatible =3D "qcom,pcie-ipq8074-gen3", .data =3D &cfg_2_9_0 }, { .compatible =3D "qcom,pcie-msm8996", .data =3D &cfg_2_3_2 }, { .compatible =3D "qcom,pcie-qcs404", .data =3D &cfg_2_4_0 }, + { .compatible =3D "qcom,pcie-qcs615", .data =3D &cfg_1_9_0 }, { .compatible =3D "qcom,pcie-sa8540p", .data =3D &cfg_sc8280xp }, { .compatible =3D "qcom,pcie-sa8775p", .data =3D &cfg_1_34_0}, { .compatible =3D "qcom,pcie-sc7280", .data =3D &cfg_1_9_0 }, --=20 2.34.1 From nobody Sat Nov 23 12:01:12 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03E16176242; 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charset="utf-8" From: Krishna chaitanya chundru Add configurations in devicetree for PCIe0, including registers, clocks, interrupts and phy setting sequence. Signed-off-by: Krishna chaitanya chundru Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 42 ++++++ arch/arm64/boot/dts/qcom/qcs615.dtsi | 158 +++++++++++++++++++++++ 2 files changed, 200 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts= /qcom/qcs615-ride.dts index 4ef969a6af15..dd245a8a50f5 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -205,6 +205,23 @@ &gcc { <&sleep_clk>; }; =20 +&pcie { + perst-gpios =3D <&tlmm 101 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 100 GPIO_ACTIVE_HIGH>; + + pinctrl-0 =3D <&pcie_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie_phy { + vdda-phy-supply =3D <&vreg_l5a>; + vdda-pll-supply =3D <&vreg_l12a>; + + status =3D "okay"; +}; + &qupv3_id_0 { status =3D "okay"; }; @@ -213,6 +230,31 @@ &rpmhcc { clocks =3D <&xo_board_clk>; }; =20 +&tlmm { + pcie_default_state: pcie-default-state { + perst-pins { + pins =3D "gpio101"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + clkreq-pins { + pins =3D "gpio90"; + function =3D "pcie_clk_req"; + drive-strength =3D <2>; + bias-pull-up; + }; + + wake-pins { + pins =3D "gpio100"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; +}; + &uart0 { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qco= m/qcs615.dtsi index ac4c4c751da1..1e30951a0d2a 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -678,6 +678,164 @@ rpmhpd_opp_turbo_l1: opp-9 { }; }; =20 + pcie: pcie@1c08000 { + compatible =3D "qcom,pcie-qcs615"; + reg =3D <0x0 0x1c08000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf1d>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x1000>, + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x1c0b000 0x0 0x1000>; + + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + + device_type =3D "pci"; + linux,pci-domain =3D <0>; + bus-range =3D <0x00 0xff>; + num-lanes =3D <1>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + + interrupts =3D , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + interrupt-map =3D <0 0 0 0 &intc 0 0 0 140 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + + interconnects =3D <&aggre1_noc MASTER_PCIE QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref"; + + assigned-clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&pcie_opp_table>; + + resets =3D <&gcc GCC_PCIE_0_BCR>; + reset-names =3D "pci"; + + phys =3D <&pcie_phy>; + phy-names =3D "pciephy"; + + power-domains =3D <&gcc PCIE_0_GDSC>; + + dma-coherent; + + iommu-map =3D <0x0 &apps_smmu 0x400 0x1>, + <0x100 &apps_smmu 0x401 0x1>; + + status =3D "disabled"; + pcie_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz =3D /bits/ 64 <2500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <250000 1>; + }; + + /* GEN 2 x1 */ + opp-5000000 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz =3D /bits/ 64 <8000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + opp-peak-kBps =3D <984500 1>; + }; + }; + + pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie_phy: phy@1c0e000 { + compatible =3D "qcom,qcs615-qmp-gen3x1-pcie-phy"; + reg =3D <0 0x01c0e000 0 0x1000>; + + clocks =3D <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "refgen", + "pipe"; + + clock-output-names =3D "pcie_0_pipe_clk"; + #clock-cells =3D <0>; + + #phy-cells =3D <0>; + + resets =3D <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names =3D "phy"; + + assigned-clocks =3D <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; + assigned-clock-rates =3D <100000000>; + + status =3D "disabled"; + }; + arch_timer: timer { compatible =3D "arm,armv8-timer"; interrupts =3D , --=20 2.34.1