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Mon, 18 Nov 2024 13:02:37 +0000 (GMT) Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa (172.25.16.114) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Mon, 18 Nov 2024 13:02:36 +0000 From: Matt Coster Date: Mon, 18 Nov 2024 13:01:59 +0000 Subject: [PATCH v2 07/21] arm64: dts: ti: k3-am62: New GPU binding details Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241118-sets-bxs-4-64-patch-v1-v2-7-3fd45d9fb0cf@imgtec.com> References: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> In-Reply-To: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1299; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=JynAPQCpoSPGJAEKxgTWnnzJahrwymyyHaR1SDFf7+4=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaRbWz3h8YkVvncp/tqTDvGFZ+/Nlmth6UjkvpXfr7s2V 1z4l8/RjlIWBjEOBlkxRZYdKyxXqP1R05K48asYZg4rE8gQBi5OAZjI/Q+MDHstBRj2Xj5x0Sm5 bOdS239L/y35khCz09PO+tCfiNUs8uWMDFeWmsnMUZaQUj9z4X17mt9mNyH7TfsNt+YxC4ULf9Y /wwIA X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Proofpoint-ORIG-GUID: QyH0-FuXm1v6qF4WeMm00GT6QSKEhbNY X-Authority-Analysis: v=2.4 cv=E4efprdl c=1 sm=1 tr=0 ts=673b3aed cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=hzDjp0mCheYA:10 a=IkcTkHD0fZMA:10 a=VlfZXiiP6vEA:10 a=VwQbUJbxAAAA:8 a=r_1tXGB3AAAA:8 a=OLj8r6_nq0VfqmG8xPEA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: QyH0-FuXm1v6qF4WeMm00GT6QSKEhbNY Use the new compatible string introduced earlier (in "dt-bindings: gpu: img: More explicit compatible strings") and add a name to the single power domain for this GPU (introduced in "dt-bindings: gpu: img: Power domain details"). Signed-off-by: Matt Coster --- Changes in v2: - None - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 7-4ed30e865892@imgtec.com --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am62-main.dtsi index 5b92aef5b284b78749a01d44184b66e7776a124d..93dcc67c3138ad5b4a7ad6c9bca= bb71a2b7e408d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -693,12 +693,13 @@ ospi0: spi@fc40000 { }; =20 gpu: gpu@fd00000 { - compatible =3D "ti,am62-gpu", "img,img-axe"; + compatible =3D "ti,am62-gpu", "img,img-axe-1-16m", "img,img-rogue"; reg =3D <0x00 0x0fd00000 0x00 0x20000>; clocks =3D <&k3_clks 187 0>; clock-names =3D "core"; interrupts =3D ; power-domains =3D <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; + power-domain-names =3D "a"; }; =20 cpsw3g: ethernet@8000000 { --=20 2.47.0