From nobody Mon Feb 9 08:56:48 2026 Received: from mx07-00376f01.pphosted.com (mx07-00376f01.pphosted.com [185.132.180.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF4321991C6; Mon, 18 Nov 2024 13:29:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.180.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731936590; cv=none; b=pGB6ZZr7WINXua/y+gYd3tlYh8tUJliNiwHkm9JvbvQshIAiAgE92FkeOYBDGLgi0HBw3crNqbqU4TejrgyiaCKfC+o0pG7ooyVs3TP8HOawr+AcjHLiF/gePAvkcq7JVoEXvuz95FK1aEf962dlJd8ny22bh/+vfywXAJP7Xyo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731936590; c=relaxed/simple; bh=gCR0QmeLLh8m/GksD06xa8wPF2LoimnvoNWbI8BLlgQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=TlyrouHEkBO4f1f9faDXlB1UDiuc5m0qXDaBLFZTF+EVF0nJKUexgU+SCiIaePeRrGYJLaGylHrL7op3JoURJ0XUtDWugYQP4wYrWIUjDJnwuD95iA9jSHyYcIaqXL+EmMI/F08McZT14GP53p+PpJhR0+Ie8OBB1TnqYzGR6HI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=imgtec.com; spf=pass smtp.mailfrom=imgtec.com; dkim=pass (2048-bit key) header.d=imgtec.com header.i=@imgtec.com header.b=s2OPyEmn; arc=none smtp.client-ip=185.132.180.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=imgtec.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=imgtec.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=imgtec.com header.i=@imgtec.com header.b="s2OPyEmn" Received: from pps.filterd (m0168889.ppops.net [127.0.0.1]) by mx07-00376f01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4AICJqTT027657; Mon, 18 Nov 2024 13:02:42 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=imgtec.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=dk201812; bh=a s1cb0Ho8uzTVCC+7kk+ZbW5T7Wctbdgc7WA7ZUdIM4=; b=s2OPyEmn3G0RHJ7TR eOZevDjxtLbmlPOdk486XDR5slREJFh1BuwU5sTZ479lh5AZu6X6PSkupmwtUkWX VaBZkd1stIIiE0RftQHBDSuCSWb0SVxGvLPT2avVW4mujO9zOpBoQcpfwjgvfCKC hb2zuyP7TeoVQc6dTPrMa57ibkKyQiMZFihwiLuP7GLISvpl83Yg4M/r/RqBp3G9 OUrswM80M4IBfRpNzBK3Amv/5205vIQpby6qYAbWxqI8MY77ZfqWLylUIvYlY0FF Y2hVjWpL5fgGDfEzo9kUg8s5V53Ygwuw/9V23m5mB+Fu5aYhZbjAQb7NdY+RK9WO 9PPQg== Received: from hhmail05.hh.imgtec.org (83-244-153-141.cust-83.exponential-e.net [83.244.153.141]) by mx07-00376f01.pphosted.com (PPS) with ESMTPS id 42xmc1hmj5-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Mon, 18 Nov 2024 13:02:42 +0000 (GMT) Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa (172.25.16.114) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Mon, 18 Nov 2024 13:02:41 +0000 From: Matt Coster Date: Mon, 18 Nov 2024 13:02:07 +0000 Subject: [PATCH v2 15/21] drm/imagination: Add register required for RISC-V firmware Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241118-sets-bxs-4-64-patch-v1-v2-15-3fd45d9fb0cf@imgtec.com> References: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> In-Reply-To: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2191; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=gCR0QmeLLh8m/GksD06xa8wPF2LoimnvoNWbI8BLlgQ=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaRbWz27uL2vRprx4rUQhdm++s1THUOOeLx4t51z6dX6w 4dtpxjqdpSyMIhxMMiKKbLsWGG5Qu2PmpbEjV/FMHNYmUCGMHBxCsBExG4x/HdQ/Sf31DUoJbXb 0iHqXbDztrvmm35/Zfdb7xvLuFuguYDhf+AiQ7N4zRsLLO4vt2fwsFzkqS/mzehtkfDpxCblY9O tGQE= X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Proofpoint-ORIG-GUID: ZHzw0g5Vn5KpI8Ec9DW_qkSXOb9wgpjZ X-Authority-Analysis: v=2.4 cv=E4efprdl c=1 sm=1 tr=0 ts=673b3af2 cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=hzDjp0mCheYA:10 a=IkcTkHD0fZMA:10 a=VlfZXiiP6vEA:10 a=VwQbUJbxAAAA:8 a=r_1tXGB3AAAA:8 a=V6O2pL_JGeI7trGcscQA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: ZHzw0g5Vn5KpI8Ec9DW_qkSXOb9wgpjZ Add definitions for a register required for a subsequent patch adding support for RISC-V firmware. ROGUE_CR_FWCORE_DMI_DMCONTROL is used to control the debug module in the firmware processor. Signed-off-by: Matt Coster --- Changes in v2: - None - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 15-4ed30e865892@imgtec.com --- drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h b/drivers/gpu/= drm/imagination/pvr_rogue_cr_defs.h index 2a90d02796d3e071b18e18dead105e29798bcddc..4e99832a667a2d88ee21469595d= 3abdad3a07c06 100644 --- a/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h +++ b/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h @@ -3751,7 +3751,22 @@ =20 /* Register ROGUE_CR_FWCORE_DMI_DMCONTROL */ #define ROGUE_CR_FWCORE_DMI_DMCONTROL 0x3480U -#define ROGUE_CR_FWCORE_DMI_DMCONTROL_MASKFULL 0x0000000000000000ULL +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_MASKFULL 0x00000000D0000003ULL +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_HALTREQ_SHIFT 31U +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_HALTREQ_CLRMSK 0x7FFFFFFFULL +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_HALTREQ_EN 0x80000000ULL +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_RESUMEREQ_SHIFT 30U +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_RESUMEREQ_CLRMSK 0xBFFFFFFFULL +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_RESUMEREQ_EN 0x40000000ULL +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_ACKHAVERESET_SHIFT 28U +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_ACKHAVERESET_CLRMSK 0xEFFFFFFFULL +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_ACKHAVERESET_EN 0x10000000ULL +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_NDMRESET_SHIFT 1U +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_NDMRESET_CLRMSK 0xFFFFFFFDULL +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_NDMRESET_EN 0x00000002ULL +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_DMACTIVE_SHIFT 0U +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_DMACTIVE_CLRMSK 0xFFFFFFFEULL +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_DMACTIVE_EN 0x00000001ULL =20 /* Register ROGUE_CR_FWCORE_DMI_DMSTATUS */ #define ROGUE_CR_FWCORE_DMI_DMSTATUS 0x3488U --=20 2.47.0