From nobody Sun Nov 24 12:34:29 2024 Received: from mx07-00376f01.pphosted.com (mx07-00376f01.pphosted.com [185.132.180.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 293191AA1C9; Mon, 18 Nov 2024 13:31:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.180.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731936711; cv=none; b=nUlZc0DaWMftJ8KKVMG4ME8vSSeqqpBmV7vfBMTrbY68KfC9tZUG6JVOmouIgwXAka+V52j/FilRxTfWk9H8GiPWPzqOKi3ZOpU2NLz3OrhxqUvG1Z1MJHVx9EGUDHjq2I+Uq2/RjI63ZR7nQW3UrTj5IUTPdpFeGi7RTJottB4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731936711; c=relaxed/simple; bh=DpicsLvRYco/Cskx2EYJLwUk9He6m1kHonPNsF2bICE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=eyNcoaY3GI2u7yg3G8OS9WWkQJ2ZMPkGi1y9sgEbLieI5fpNdA9KgbmzrPv1WSz2RGru2zPTfIcgrcJkqAzccmNzmUzRYrwe7/rj7WXDrvOhY0zW26Pvbk/i7AgVu0JAcxNTDZGH2f1x1Mo91/ZXpf1nMM3NRw+xogpu0SZkeqE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=imgtec.com; spf=pass smtp.mailfrom=imgtec.com; dkim=pass (2048-bit key) header.d=imgtec.com header.i=@imgtec.com header.b=KLmj6G1B; arc=none smtp.client-ip=185.132.180.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=imgtec.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=imgtec.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=imgtec.com header.i=@imgtec.com header.b="KLmj6G1B" Received: from pps.filterd (m0168889.ppops.net [127.0.0.1]) by mx07-00376f01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4AICKePf029230; Mon, 18 Nov 2024 13:02:33 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=imgtec.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=dk201812; bh=c PZ9rm162er/TnZeptBWDE184JcGib5AQramdw2qhZY=; b=KLmj6G1B62d5vd/Yp lZApZzjFw857dc2BOuEcFjNhS1NCIitB1DUzuFdprxTbc1QIMYrypcrNKZA8tqDs 7Y6t19r7f605skEpQgzsNrHpMVH7cITrV3LxXDUraKNchlJrbDhhyAwB1ksoha+O +bQtwW9Te8B8KTgULEw2jTYouZ0oGO23tW3hp3KqPbRLzwF2aXn0R/axLjjqp2tl u4l/h4pE/MCtMwqzTkLF3JSuB8KltzlyLNXal9SJ/cxbfWrojmkQV3fQCsyJav7Z we7Jnhy9oqr78BgUVKR17jZKlHddUvhAMT1LLl9cxsnZVbavUMbalRhBTRrwJW7N DwFLw== Received: from hhmail05.hh.imgtec.org (83-244-153-141.cust-83.exponential-e.net [83.244.153.141]) by mx07-00376f01.pphosted.com (PPS) with ESMTPS id 42xmc1hmhv-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Mon, 18 Nov 2024 13:02:32 +0000 (GMT) Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa (172.25.16.114) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Mon, 18 Nov 2024 13:02:31 +0000 From: Matt Coster Date: Mon, 18 Nov 2024 13:01:53 +0000 Subject: [PATCH v2 01/21] dt-bindings: gpu: img: More explicit compatible strings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241118-sets-bxs-4-64-patch-v1-v2-1-3fd45d9fb0cf@imgtec.com> References: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> In-Reply-To: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3013; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=DpicsLvRYco/Cskx2EYJLwUk9He6m1kHonPNsF2bICE=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaRbWz2pnuv2+B/H0/LcrAMqPS39Sw3SdGLX3nkSeXav0 iOdyYx+HaUsDGIcDLJiiiw7VliuUPujpiVx41cxzBxWJpAhDFycAjCRuoUM/+zi5t1WT93/lXu7 tVJIt95dni9tsoc+1D30mfr0KI/Yi0CGf5ZF5vO9HuXdmPhVrjj44+usm/y7Z/FEx4Zwd35ceuv gd34A X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Proofpoint-ORIG-GUID: 7MkrfIZQhJbBM942VtzARgiKbgOx9A6Q X-Authority-Analysis: v=2.4 cv=E4efprdl c=1 sm=1 tr=0 ts=673b3ae8 cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=hzDjp0mCheYA:10 a=IkcTkHD0fZMA:10 a=VlfZXiiP6vEA:10 a=VwQbUJbxAAAA:8 a=r_1tXGB3AAAA:8 a=nBKxard2HoEgs5BrZHgA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: 7MkrfIZQhJbBM942VtzARgiKbgOx9A6Q The current compatible strings are not specific enough to constrain the hardware in devicetree. For example, the current "img,img-axe" string refers to the entire family of Series AXE GPUs. The more specific "img,img-axe-1-16m" string refers to the AXE-1-16M GPU which, unlike the rest of its family, only uses a single power domain. While in this instance there is already "ti,am62-gpu" for the more specific case, the intent here is to draw a line between properties inherent to the IP core and choices made by the silicon vendor at integration time. For example, the number of power domains is a property of the IP core, whereas the decision to use one or three clocks (see next patch) is a vendor one. Work is currently underway to add support for volcanic-based Imagination GPUs, for which bindings will be added in "img,powervr-volcanic.yaml". The split between rogue and volcanic cores is non-obvious at times, so add a generic top-level "img,img-rogue" compatible string here to allow for simpler differentiation in devicetrees without referring back to the bindings. Make these changes now before introducing more compatible strings to keep the legacy versions to a minimum. Signed-off-by: Matt Coster --- Changes in v2: - Clarified justification for compatible strings - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 1-4ed30e865892@imgtec.com --- .../devicetree/bindings/gpu/img,powervr-rogue.yaml | 19 ++++++++++++++-= ---- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b= /Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index 256e252f8087fa0d6081f771a01601d34b66fe19..ef7070daf213277d0190fe319e2= 02fdc597337d4 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -12,10 +12,19 @@ maintainers: =20 properties: compatible: - items: - - enum: - - ti,am62-gpu - - const: img,img-axe # IMG AXE GPU model/revision is fully discovera= ble + oneOf: + - items: + - enum: + - ti,am62-gpu + - const: img,img-axe-1-16m + - const: img,img-rogue + + # This legacy combination of compatible strings was introduced early= on before the more + # specific GPU identifiers were used. Keep it around here for compat= ibility, but never use + # "img,img-axe" in new devicetrees. + - items: + - const: ti,am62-gpu + - const: img,img-axe =20 reg: maxItems: 1 @@ -64,7 +73,7 @@ examples: #include =20 gpu@fd00000 { - compatible =3D "ti,am62-gpu", "img,img-axe"; + compatible =3D "ti,am62-gpu", "img,img-axe-1-16m", "img,img-rogue"; reg =3D <0x0fd00000 0x20000>; clocks =3D <&k3_clks 187 0>; clock-names =3D "core"; --=20 2.47.0 From nobody Sun Nov 24 12:34:29 2024 Received: from mx07-00376f01.pphosted.com (mx07-00376f01.pphosted.com [185.132.180.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E06FD1A9B51; Mon, 18 Nov 2024 13:29:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.180.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731936594; cv=none; b=ecSYOZU8dGxaHsujP5gCAVXkgzjBt6LoGRJhitQEKt/NWwJSNU9/3Ljdx52rANAWulS1d98sAA63uhc2/KTF2hNoX4zybv+R73ihdaCIYYuEfftu8vWpXKr5eWoTUQ8ovPhsD7z5EvU/7BwN0vMi0RJNfEt4L0KcCVEEvi91Ops= ARC-Message-Signature: i=1; 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Mon, 18 Nov 2024 13:02:32 +0000 From: Matt Coster Date: Mon, 18 Nov 2024 13:01:54 +0000 Subject: [PATCH v2 02/21] dt-bindings: gpu: img: Further constrain clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241118-sets-bxs-4-64-patch-v1-v2-2-3fd45d9fb0cf@imgtec.com> References: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> In-Reply-To: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1955; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=3Or83jNpwXbaO0NeKSfl6slWC+kAbeyA+TIPsN7OvD4=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaRbWz0R/W9n9emB3hMNZpU0meLN9eeenmcv/VxQeepYU 2ujzfGkjlIWBjEOBlkxRZYdKyxXqP1R05K48asYZg4rE8gQBi5OAZiI6ieG/15Gujnc/p8m3Nl0 UvlwYIxEUuPKkCtXtZ65aK2SWL35bzojw6lO4berrBbbztx7aFr3sfZf75kZJidnTO1rPfLtd9V XdlYA X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Proofpoint-ORIG-GUID: 1_2GWLb-HJ1S4agGL_gup0fp_194pibE X-Authority-Analysis: v=2.4 cv=E4efprdl c=1 sm=1 tr=0 ts=673b3ae9 cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=hzDjp0mCheYA:10 a=IkcTkHD0fZMA:10 a=VlfZXiiP6vEA:10 a=VwQbUJbxAAAA:8 a=r_1tXGB3AAAA:8 a=cDXhS4k7GDcpIX9mfQgA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: 1_2GWLb-HJ1S4agGL_gup0fp_194pibE All Imagination GPUs use three clocks: core, mem and sys. All reasonably modern Imagination GPUs also support a single-clock mode where the SoC only hooks up core and the other two are derived internally. On GPUs which support this mode, it is the default and most commonly used integration. Codify this "1 or 3" constraint in our bindings and hang the specifics off the vendor compatible string to mirror the integration-time choice. Signed-off-by: Matt Coster --- Changes in v2: - Simplified clocks constraints (P2) - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 2-4ed30e865892@imgtec.com --- .../devicetree/bindings/gpu/img,powervr-rogue.yaml | 20 +++++++++++-----= ---- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b= /Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index ef7070daf213277d0190fe319e202fdc597337d4..3b5a5b966585ac29ad104c7aef1= 9881eca73ce80 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -29,16 +29,16 @@ properties: reg: maxItems: 1 =20 - clocks: - minItems: 1 - maxItems: 3 + clocks: true =20 clock-names: - items: - - const: core - - const: mem - - const: sys - minItems: 1 + oneOf: + - items: + - const: core + - items: + - const: core + - const: mem + - const: sys =20 interrupts: maxItems: 1 @@ -56,11 +56,13 @@ required: additionalProperties: false =20 allOf: + # Vendor integrations using a single clock domain - if: properties: compatible: contains: - const: ti,am62-gpu + anyOf: + - const: ti,am62-gpu then: properties: clocks: --=20 2.47.0 From nobody Sun Nov 24 12:34:29 2024 Received: from mx07-00376f01.pphosted.com (mx07-00376f01.pphosted.com [185.132.180.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BBE3C1A2630; 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Mon, 18 Nov 2024 13:02:34 +0000 (GMT) Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa (172.25.16.114) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Mon, 18 Nov 2024 13:02:33 +0000 From: Matt Coster Date: Mon, 18 Nov 2024 13:01:55 +0000 Subject: [PATCH v2 03/21] dt-bindings: gpu: img: Power domain details Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241118-sets-bxs-4-64-patch-v1-v2-3-3fd45d9fb0cf@imgtec.com> References: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> In-Reply-To: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1988; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=7vjLrqeVbec/kiwK1+Loh1po9ifOS9rsUyR0/I/IY3Y=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaRbWz053CKe9/RyYeJqtd88z6+Lr7n1V0QrS0HE6aC24 I2jd7gsOkpZGMQ4GGTFFFl2rLBcofZHTUvixq9imDmsTCBDGLg4BWAizmsYfrO+7qrLTePp28g2 Vf+gcqhqknf1uQb7vVssxNhWTr5lN5XhnylPhqzC0ttmfCZ79bK5o9hnK6kZ2AYbT6pfY59Trvy MDQA= X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Proofpoint-ORIG-GUID: mpMDQoUd_fyBH3X77gZaBE9_QoRIEL-H X-Authority-Analysis: v=2.4 cv=E4efprdl c=1 sm=1 tr=0 ts=673b3aea cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=hzDjp0mCheYA:10 a=IkcTkHD0fZMA:10 a=VlfZXiiP6vEA:10 a=VwQbUJbxAAAA:8 a=r_1tXGB3AAAA:8 a=Vh8Z_yn72AIZk_KtqmMA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: mpMDQoUd_fyBH3X77gZaBE9_QoRIEL-H The single existing GPU (AXE-1-16M) only requires a single power domain. Subsequent patches will add support for BXS-4-64 MC1, which has two power domains. Add infrastructure now to allow for this. Signed-off-by: Matt Coster --- Changes in v2: - Simplified power-domains constraints P3 - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 3-4ed30e865892@imgtec.com --- .../devicetree/bindings/gpu/img,powervr-rogue.yaml | 25 ++++++++++++++++++= ++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b= /Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index 3b5a5b966585ac29ad104c7aef19881eca73ce80..c629f54c86c441b4cc9e57925f1= d65129cbe285b 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -43,8 +43,15 @@ properties: interrupts: maxItems: 1 =20 - power-domains: - maxItems: 1 + power-domains: true + + power-domain-names: + oneOf: + - items: + - const: a + - items: + - const: a + - const: b =20 required: - compatible @@ -52,10 +59,23 @@ required: - clocks - clock-names - interrupts + - power-domains + - power-domain-names =20 additionalProperties: false =20 allOf: + # Cores with a single power domain + - if: + properties: + compatible: + contains: + anyOf: + - const: img,img-axe-1-16m + then: + properties: + power-domains: + maxItems: 1 # Vendor integrations using a single clock domain - if: properties: @@ -81,4 +101,5 @@ examples: clock-names =3D "core"; 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Mon, 18 Nov 2024 13:02:33 +0000 From: Matt Coster Date: Mon, 18 Nov 2024 13:01:56 +0000 Subject: [PATCH v2 04/21] dt-bindings: gpu: img: Allow dma-coherent Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241118-sets-bxs-4-64-patch-v1-v2-4-3fd45d9fb0cf@imgtec.com> References: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> In-Reply-To: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1040; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=QR/jy18Q3nJy2xtQXtFeNujl4LHlr+a2FMAmw0I4okU=; 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Signed-off-by: Matt Coster --- Changes in v2: - Simplified power-domains constraints - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 4-4ed30e865892@imgtec.com --- Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b= /Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index c629f54c86c441b4cc9e57925f1d65129cbe285b..9dc55a6d0d4023983a3fc480340= 351f3fa974ce5 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -53,6 +53,8 @@ properties: - const: a - const: b =20 + dma-coherent: true + required: - compatible - reg --=20 2.47.0 From nobody Sun Nov 24 12:34:29 2024 Received: from mx07-00376f01.pphosted.com (mx07-00376f01.pphosted.com [185.132.180.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 276B81AA1C1; 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Keep the previous compatible string around for backwards compatibility. Signed-off-by: Matt Coster --- Changes in v2: - None - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 5-4ed30e865892@imgtec.com --- drivers/gpu/drm/imagination/pvr_drv.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/imagination/pvr_drv.c b/drivers/gpu/drm/imagin= ation/pvr_drv.c index 684a9b9a2247b8f5b0f4a91ec984af2cff5a4c29..fbd8802abcf1271e260209957d9= 5ea705dbe7f14 100644 --- a/drivers/gpu/drm/imagination/pvr_drv.c +++ b/drivers/gpu/drm/imagination/pvr_drv.c @@ -1471,6 +1471,16 @@ static void pvr_remove(struct platform_device *plat_= dev) } =20 static const struct of_device_id dt_match[] =3D { + { .compatible =3D "img,img-rogue", .data =3D NULL }, + + /* All supported GPU models */ + { .compatible =3D "img,img-axe-1-16m", .data =3D NULL }, + + /* + * This legacy compatible string was introduced early on before the more = specific GPU + * identifiers were used. Keep it around here for compatibility, but neve= r use + * "img,img-axe" in new devicetrees. + */ { .compatible =3D "img,img-axe", .data =3D NULL }, {} }; --=20 2.47.0 From nobody Sun Nov 24 12:34:29 2024 Received: from mx07-00376f01.pphosted.com (mx07-00376f01.pphosted.com [185.132.180.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF47A19ABB6; Mon, 18 Nov 2024 13:29:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.180.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731936590; cv=none; b=ueU7yun3Xz5duDN1VyRdcmgOefyZU8McmUE9ZqpTQxEcg2EB2kzTypiJxWvUgGHzT1M4mZiz5IUOz3RM/ca73D/iNFGN19QF5dXr7Ut6275FQtRc8vABUop4xNG9NflOz5o5cd3U36bLd8CFj7l/PIOs6oO36klzd4M98iVvQ+g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731936590; c=relaxed/simple; bh=EDeQt3mie167DrpZUwHp7UeO+k68HDTaFgW5fNU+Z1E=; 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Mon, 18 Nov 2024 13:02:35 +0000 From: Matt Coster Date: Mon, 18 Nov 2024 13:01:58 +0000 Subject: [PATCH v2 06/21] drm/imagination: Add power domain control Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241118-sets-bxs-4-64-patch-v1-v2-6-3fd45d9fb0cf@imgtec.com> References: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> In-Reply-To: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7141; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=EDeQt3mie167DrpZUwHp7UeO+k68HDTaFgW5fNU+Z1E=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaRbWz3pcHH8zHxDy3XqH9XDkx/rbJuZJ2fMN2lq0Ky3Q tU6276Wd5SyMIhxMMiKKbLsWGG5Qu2PmpbEjV/FMHNYmUCGMHBxCsBEwnYz/LNlevTk80SFqb7K n/paGsvZQ3VdqtWV7VisN1Z6PHgQwMjw32mV65ZfB9Z0CH9JW9Qs+C59yU4pLrvFC6KXHPM+cf1 8JjsA X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Proofpoint-ORIG-GUID: PKqxLTvkMabC7AHCY__wLTdJbNiKOYOG X-Authority-Analysis: v=2.4 cv=E4efprdl c=1 sm=1 tr=0 ts=673b3aec cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=hzDjp0mCheYA:10 a=IkcTkHD0fZMA:10 a=VlfZXiiP6vEA:10 a=VwQbUJbxAAAA:8 a=r_1tXGB3AAAA:8 a=Iu228gY9Y64KKxsXE-4A:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: PKqxLTvkMabC7AHCY__wLTdJbNiKOYOG The first supported GPU only used a single power domain so this was automatically handled by the device runtime. In order to support multiple power domains, they must be enumerated from devicetree and linked to both the GPU device and each other to ensure correct power sequencing at start time. For all Imagination Rogue GPUs, power domains are named "a", "b", etc. and the sequence A->B->... is always valid for startup with the reverse true for shutdown. Note this is not always the *only* valid sequence, but it's simple and does not require special-casing for different GPU power topologies. Signed-off-by: Matt Coster --- Changes in v2: - None - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 6-4ed30e865892@imgtec.com --- drivers/gpu/drm/imagination/pvr_device.h | 8 +++ drivers/gpu/drm/imagination/pvr_drv.c | 10 ++- drivers/gpu/drm/imagination/pvr_power.c | 114 +++++++++++++++++++++++++++= ++++ drivers/gpu/drm/imagination/pvr_power.h | 3 + 4 files changed, 134 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/imagination/pvr_device.h b/drivers/gpu/drm/ima= gination/pvr_device.h index b574e23d484ba80785a2220e046dbab3f91f6e15..470945ccfcac7ce91161aa6c70d= 33177fbb3533f 100644 --- a/drivers/gpu/drm/imagination/pvr_device.h +++ b/drivers/gpu/drm/imagination/pvr_device.h @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -130,6 +131,13 @@ struct pvr_device { */ struct clk *mem_clk; =20 + struct pvr_device_power { + struct device **domain_devs; + struct device_link **domain_links; + + u32 domain_count; + } power; + /** @irq: IRQ number. */ int irq; =20 diff --git a/drivers/gpu/drm/imagination/pvr_drv.c b/drivers/gpu/drm/imagin= ation/pvr_drv.c index fbd8802abcf1271e260209957d95ea705dbe7f14..1ab97933e14f20ee3fbf603c23b= 8dde2d33572c2 100644 --- a/drivers/gpu/drm/imagination/pvr_drv.c +++ b/drivers/gpu/drm/imagination/pvr_drv.c @@ -1409,13 +1409,17 @@ pvr_probe(struct platform_device *plat_dev) =20 platform_set_drvdata(plat_dev, drm_dev); =20 + err =3D pvr_power_domains_init(pvr_dev); + if (err) + goto err_context_fini; + init_rwsem(&pvr_dev->reset_sem); =20 pvr_context_device_init(pvr_dev); =20 err =3D pvr_queue_device_init(pvr_dev); if (err) - goto err_context_fini; + goto err_power_domains_fini; =20 devm_pm_runtime_enable(&plat_dev->dev); pm_runtime_mark_last_busy(&plat_dev->dev); @@ -1448,6 +1452,9 @@ pvr_probe(struct platform_device *plat_dev) err_context_fini: pvr_context_device_fini(pvr_dev); =20 +err_power_domains_fini: + pvr_power_domains_fini(pvr_dev); + return err; } =20 @@ -1468,6 +1475,7 @@ static void pvr_remove(struct platform_device *plat_d= ev) pvr_watchdog_fini(pvr_dev); pvr_queue_device_fini(pvr_dev); pvr_context_device_fini(pvr_dev); + pvr_power_domains_fini(pvr_dev); } =20 static const struct of_device_id dt_match[] =3D { diff --git a/drivers/gpu/drm/imagination/pvr_power.c b/drivers/gpu/drm/imag= ination/pvr_power.c index ba7816fd28ec77e6ca5ce408302a413ce1afeb6e..19b079b357df78e8bcdecfa377f= c9c05b6e8e4b0 100644 --- a/drivers/gpu/drm/imagination/pvr_power.c +++ b/drivers/gpu/drm/imagination/pvr_power.c @@ -10,10 +10,13 @@ =20 #include #include +#include #include #include #include +#include #include +#include #include #include #include @@ -431,3 +434,114 @@ pvr_watchdog_fini(struct pvr_device *pvr_dev) { cancel_delayed_work_sync(&pvr_dev->watchdog.work); } + +int pvr_power_domains_init(struct pvr_device *pvr_dev) +{ + struct device *dev =3D from_pvr_device(pvr_dev)->dev; + + struct device_link **domain_links __free(kfree) =3D NULL; + struct device **domain_devs __free(kfree) =3D NULL; + int domain_count; + int link_count; + + char dev_name[2] =3D "a"; + int err; + int i; + + domain_count =3D of_count_phandle_with_args(dev->of_node, "power-domains", + "#power-domain-cells"); + if (domain_count < 0) + return domain_count; + + if (domain_count <=3D 1) + return 0; + + link_count =3D domain_count + (domain_count - 1); + + domain_devs =3D kcalloc(domain_count, sizeof(*domain_devs), GFP_KERNEL); + if (!domain_devs) + return -ENOMEM; + + domain_links =3D kcalloc(link_count, sizeof(*domain_links), GFP_KERNEL); + if (!domain_links) + return -ENOMEM; + + for (i =3D 0; i < domain_count; i++) { + struct device *domain_dev; + + dev_name[0] =3D 'a' + i; + domain_dev =3D dev_pm_domain_attach_by_name(dev, dev_name); + if (IS_ERR_OR_NULL(domain_dev)) { + err =3D domain_dev ? PTR_ERR(domain_dev) : -ENODEV; + goto err_detach; + } + + domain_devs[i] =3D domain_dev; + } + + for (i =3D 0; i < domain_count; i++) { + struct device_link *link; + + link =3D device_link_add(dev, domain_devs[i], DL_FLAG_STATELESS | DL_FLA= G_PM_RUNTIME); + if (!link) { + err =3D -ENODEV; + goto err_unlink; + } + + domain_links[i] =3D link; + } + + for (i =3D domain_count; i < link_count; i++) { + struct device_link *link; + + link =3D device_link_add(domain_devs[i - domain_count + 1], + domain_devs[i - domain_count], + DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME); + if (!link) { + err =3D -ENODEV; + goto err_unlink; + } + + domain_links[i] =3D link; + } + + pvr_dev->power =3D (struct pvr_device_power){ + .domain_devs =3D no_free_ptr(domain_devs), + .domain_links =3D no_free_ptr(domain_links), + .domain_count =3D domain_count, + }; + + return 0; + +err_unlink: + while (--i >=3D 0) + device_link_del(domain_links[i]); + + i =3D domain_count; + +err_detach: + while (--i >=3D 0) + dev_pm_domain_detach(domain_devs[i], true); + + return err; +} + +void pvr_power_domains_fini(struct pvr_device *pvr_dev) +{ + const int domain_count =3D pvr_dev->power.domain_count; + + int i =3D domain_count + (domain_count - 1); + + while (--i >=3D 0) + device_link_del(pvr_dev->power.domain_links[i]); + + i =3D domain_count; + + while (--i >=3D 0) + dev_pm_domain_detach(pvr_dev->power.domain_devs[i], true); + + kfree(pvr_dev->power.domain_links); + kfree(pvr_dev->power.domain_devs); + + pvr_dev->power =3D (struct pvr_device_power){ 0 }; +} diff --git a/drivers/gpu/drm/imagination/pvr_power.h b/drivers/gpu/drm/imag= ination/pvr_power.h index 9a9312dcb2dab7d36ee8ff7f69e69d126c5469a9..ada85674a7ca762dcf92df40424= 230e1c3910342 100644 --- a/drivers/gpu/drm/imagination/pvr_power.h +++ b/drivers/gpu/drm/imagination/pvr_power.h @@ -38,4 +38,7 @@ pvr_power_put(struct pvr_device *pvr_dev) return pm_runtime_put(drm_dev->dev); } =20 +int pvr_power_domains_init(struct pvr_device *pvr_dev); +void pvr_power_domains_fini(struct pvr_device *pvr_dev); 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Signed-off-by: Matt Coster --- Changes in v2: - None - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 7-4ed30e865892@imgtec.com --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am62-main.dtsi index 5b92aef5b284b78749a01d44184b66e7776a124d..93dcc67c3138ad5b4a7ad6c9bca= bb71a2b7e408d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -693,12 +693,13 @@ ospi0: spi@fc40000 { }; =20 gpu: gpu@fd00000 { - compatible =3D "ti,am62-gpu", "img,img-axe"; + compatible =3D "ti,am62-gpu", "img,img-axe-1-16m", "img,img-rogue"; reg =3D <0x00 0x0fd00000 0x00 0x20000>; clocks =3D <&k3_clks 187 0>; clock-names =3D "core"; interrupts =3D ; power-domains =3D <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; + power-domain-names =3D "a"; }; =20 cpsw3g: ethernet@8000000 { --=20 2.47.0 From nobody Sun Nov 24 12:34:29 2024 Received: from mx07-00376f01.pphosted.com (mx07-00376f01.pphosted.com [185.132.180.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B37A91A9B4B; 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Signed-off-by: Matt Coster --- Changes in v2: - Use normal reg syntax for 64-bit values - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 8-4ed30e865892@imgtec.com --- .../devicetree/bindings/gpu/img,powervr-rogue.yaml | 41 ++++++++++++++++++= ++++ 1 file changed, 41 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b= /Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index 9dc55a6d0d4023983a3fc480340351f3fa974ce5..b620baa56a4caa41246f7b53064= d0e3309bdda8e 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -18,6 +18,11 @@ properties: - ti,am62-gpu - const: img,img-axe-1-16m - const: img,img-rogue + - items: + - enum: + - ti,j721s2-gpu + - const: img,img-bxs-4-64 + - const: img,img-rogue =20 # This legacy combination of compatible strings was introduced early= on before the more # specific GPU identifiers were used. Keep it around here for compat= ibility, but never use @@ -78,6 +83,18 @@ allOf: properties: power-domains: maxItems: 1 + # Cores with two power domains + - if: + properties: + compatible: + contains: + anyOf: + - const: img,img-bxs-4-64 + then: + properties: + power-domains: + minItems: 2 + maxItems: 2 # Vendor integrations using a single clock domain - if: properties: @@ -85,6 +102,7 @@ allOf: contains: anyOf: - const: ti,am62-gpu + - const: ti,j721s2-gpu then: properties: clocks: @@ -105,3 +123,26 @@ examples: power-domains =3D <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; power-domain-names =3D "a"; }; + - | + #include + #include + #include + + / { + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <3>; + + gpu@4e20000000 { + compatible =3D "ti,j721s2-gpu", "img,img-bxs-4-64", "img,img-r= ogue"; + reg =3D <0x4e 0x20000000 0x00 0x80000>; + clocks =3D <&k3_clks 130 1>; + clock-names =3D "core"; + interrupts =3D ; + power-domains =3D <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 373 TI_SCI_PD_EXCLUSIVE>; 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Mon, 18 Nov 2024 13:02:37 +0000 From: Matt Coster Date: Mon, 18 Nov 2024 13:02:01 +0000 Subject: [PATCH v2 09/21] drm/imagination: Revert to non-threaded IRQs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241118-sets-bxs-4-64-patch-v1-v2-9-3fd45d9fb0cf@imgtec.com> References: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> In-Reply-To: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=12417; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=fqYyXHPumIuy6+GbVwJYarv1fjdoowD8X4wyH3FYNA0=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaRbWz1VM5i7U3LtIs2VP3if7D/dFP5+D5tkRZh05p9VR QLSSyVmdpSyMIhxMMiKKbLsWGG5Qu2PmpbEjV/FMHNYmUCGMHBxCsBEyu4w/JVY6OPWeMORZS2L fjtr+aMZotdKzmjN+qKQqNjYtDlRt5GR4UADS/KzCSaRT+f4uou9uXXsWPRJnw08ambOT/zDzmv PYgEA X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Proofpoint-ORIG-GUID: ba_yTsHJh6CK94QP5HOnI4TAZYKhiXRz X-Authority-Analysis: v=2.4 cv=E4efprdl c=1 sm=1 tr=0 ts=673b3aee cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=hzDjp0mCheYA:10 a=IkcTkHD0fZMA:10 a=VlfZXiiP6vEA:10 a=VwQbUJbxAAAA:8 a=r_1tXGB3AAAA:8 a=1hQr5poaKPxSApStpg4A:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: ba_yTsHJh6CK94QP5HOnI4TAZYKhiXRz For some reason, threaded IRQs do not play nice with the RISC-V firmware processor in BXS on our test platform (TI AM68). Until we can resolve this issue, revert to a more traditional workqueue- based IRQ implementation so the platform is at least functional. Signed-off-by: Matt Coster --- Changes in v2: - None - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 9-4ed30e865892@imgtec.com --- drivers/gpu/drm/imagination/pvr_ccb.c | 25 +++++++-- drivers/gpu/drm/imagination/pvr_device.c | 94 ++++++++++------------------= ---- drivers/gpu/drm/imagination/pvr_device.h | 12 ++++ drivers/gpu/drm/imagination/pvr_fw.c | 1 + drivers/gpu/drm/imagination/pvr_power.c | 4 +- drivers/gpu/drm/imagination/pvr_queue.c | 23 +++++++- 6 files changed, 87 insertions(+), 72 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_ccb.c b/drivers/gpu/drm/imagin= ation/pvr_ccb.c index 2bbdc05a3b97791426fd1f2ffe8f306d15622901..3bc3dc1bcc30ace720a09a2af5c= adc1c6ccfd93f 100644 --- a/drivers/gpu/drm/imagination/pvr_ccb.c +++ b/drivers/gpu/drm/imagination/pvr_ccb.c @@ -156,6 +156,13 @@ process_fwccb_command(struct pvr_device *pvr_dev, stru= ct rogue_fwif_fwccb_cmd *c } } =20 +static void pvr_fwccb_process_worker(struct work_struct *work) +{ + struct pvr_device *pvr_dev =3D container_of_const(work, struct pvr_device= , fwccb_work); + + pvr_fwccb_process(pvr_dev); +} + /** * pvr_fwccb_process() - Process any pending FWCCB commands * @pvr_dev: Target PowerVR device @@ -463,19 +470,16 @@ struct pvr_kccb_fence { }; =20 /** - * pvr_kccb_wake_up_waiters() - Check the KCCB waiters + * pvr_kccb_check_waiters() - Check the KCCB waiters * @pvr_dev: Target PowerVR device * * Signal as many KCCB fences as we have slots available. */ -void pvr_kccb_wake_up_waiters(struct pvr_device *pvr_dev) +static void pvr_kccb_check_waiters(struct pvr_device *pvr_dev) { struct pvr_kccb_fence *fence, *tmp_fence; u32 used_count, available_count; =20 - /* Wake up those waiting for KCCB slot execution. */ - wake_up_all(&pvr_dev->kccb.rtn_q); - /* Then iterate over all KCCB fences and signal as many as we can. */ mutex_lock(&pvr_dev->kccb.ccb.lock); used_count =3D pvr_kccb_used_slot_count_locked(pvr_dev); @@ -499,12 +503,20 @@ void pvr_kccb_wake_up_waiters(struct pvr_device *pvr_= dev) mutex_unlock(&pvr_dev->kccb.ccb.lock); } =20 +static void pvr_kccb_process_worker(struct work_struct *work) +{ + struct pvr_device *pvr_dev =3D container_of_const(work, struct pvr_device= , kccb.work); + + pvr_kccb_check_waiters(pvr_dev); +} + /** * pvr_kccb_fini() - Cleanup device KCCB * @pvr_dev: Target PowerVR device */ void pvr_kccb_fini(struct pvr_device *pvr_dev) { + cancel_work_sync(&pvr_dev->kccb.work); pvr_ccb_fini(&pvr_dev->kccb.ccb); WARN_ON(!list_empty(&pvr_dev->kccb.waiters)); WARN_ON(pvr_dev->kccb.reserved_count); @@ -525,6 +537,7 @@ pvr_kccb_init(struct pvr_device *pvr_dev) INIT_LIST_HEAD(&pvr_dev->kccb.waiters); pvr_dev->kccb.fence_ctx.id =3D dma_fence_context_alloc(1); spin_lock_init(&pvr_dev->kccb.fence_ctx.lock); + INIT_WORK(&pvr_dev->kccb.work, pvr_kccb_process_worker); =20 return pvr_ccb_init(pvr_dev, &pvr_dev->kccb.ccb, ROGUE_FWIF_KCCB_NUMCMDS_LOG2_DEFAULT, @@ -639,6 +652,8 @@ void pvr_kccb_release_slot(struct pvr_device *pvr_dev) int pvr_fwccb_init(struct pvr_device *pvr_dev) { + INIT_WORK(&pvr_dev->fwccb_work, pvr_fwccb_process_worker); + return pvr_ccb_init(pvr_dev, &pvr_dev->fwccb, ROGUE_FWIF_FWCCB_NUMCMDS_LOG2, sizeof(struct rogue_fwif_fwccb_cmd)); diff --git a/drivers/gpu/drm/imagination/pvr_device.c b/drivers/gpu/drm/ima= gination/pvr_device.c index 1704c0268589bdeb65fa6535f9ec63182b0a3e94..43411fe64fcecd8f84c0ceabb32= 9f2901d63ed93 100644 --- a/drivers/gpu/drm/imagination/pvr_device.c +++ b/drivers/gpu/drm/imagination/pvr_device.c @@ -120,72 +120,24 @@ static int pvr_device_clk_init(struct pvr_device *pvr= _dev) return 0; } =20 -/** - * pvr_device_process_active_queues() - Process all queue related events. - * @pvr_dev: PowerVR device to check - * - * This is called any time we receive a FW event. It iterates over all - * active queues and calls pvr_queue_process() on them. - */ -static void pvr_device_process_active_queues(struct pvr_device *pvr_dev) -{ - struct pvr_queue *queue, *tmp_queue; - LIST_HEAD(active_queues); - - mutex_lock(&pvr_dev->queues.lock); - - /* Move all active queues to a temporary list. Queues that remain - * active after we're done processing them are re-inserted to - * the queues.active list by pvr_queue_process(). - */ - list_splice_init(&pvr_dev->queues.active, &active_queues); - - list_for_each_entry_safe(queue, tmp_queue, &active_queues, node) - pvr_queue_process(queue); - - mutex_unlock(&pvr_dev->queues.lock); -} - -static irqreturn_t pvr_device_irq_thread_handler(int irq, void *data) +static irqreturn_t pvr_device_irq_handler(int irq, void *data) { struct pvr_device *pvr_dev =3D data; - irqreturn_t ret =3D IRQ_NONE; - - /* We are in the threaded handler, we can keep dequeuing events until we - * don't see any. This should allow us to reduce the number of interrupts - * when the GPU is receiving a massive amount of short jobs. - */ - while (pvr_fw_irq_pending(pvr_dev)) { - pvr_fw_irq_clear(pvr_dev); =20 - if (pvr_dev->fw_dev.booted) { - pvr_fwccb_process(pvr_dev); - pvr_kccb_wake_up_waiters(pvr_dev); - pvr_device_process_active_queues(pvr_dev); - } + if (!pvr_fw_irq_pending(pvr_dev)) + return IRQ_NONE; /* Spurious IRQ - ignore */ =20 - pm_runtime_mark_last_busy(from_pvr_device(pvr_dev)->dev); + pvr_fw_irq_clear(pvr_dev); =20 - ret =3D IRQ_HANDLED; + /* Only process IRQ work if FW is currently running */ + if (pvr_dev->fw_dev.booted) { + queue_work(pvr_dev->irq_wq, &pvr_dev->fwccb_work); + wake_up_all(&pvr_dev->kccb.rtn_q); + queue_work(pvr_dev->irq_wq, &pvr_dev->kccb.work); + queue_work(pvr_dev->irq_wq, &pvr_dev->queues.work); } =20 - /* Unmask FW irqs before returning, so new interrupts can be received. */ - pvr_fw_irq_enable(pvr_dev); - return ret; -} - -static irqreturn_t pvr_device_irq_handler(int irq, void *data) -{ - struct pvr_device *pvr_dev =3D data; - - if (!pvr_fw_irq_pending(pvr_dev)) - return IRQ_NONE; /* Spurious IRQ - ignore. */ - - /* Mask the FW interrupts before waking up the thread. Will be unmasked - * when the thread handler is done processing events. - */ - pvr_fw_irq_disable(pvr_dev); - return IRQ_WAKE_THREAD; + return IRQ_HANDLED; } =20 /** @@ -202,20 +154,33 @@ pvr_device_irq_init(struct pvr_device *pvr_dev) { struct drm_device *drm_dev =3D from_pvr_device(pvr_dev); struct platform_device *plat_dev =3D to_platform_device(drm_dev->dev); + int err; =20 init_waitqueue_head(&pvr_dev->kccb.rtn_q); =20 + pvr_dev->irq_wq =3D alloc_workqueue("powervr-irq", WQ_UNBOUND, 0); + if (!pvr_dev->irq_wq) { + err =3D -ENOMEM; + goto err_out; + } + pvr_dev->irq =3D platform_get_irq(plat_dev, 0); - if (pvr_dev->irq < 0) - return pvr_dev->irq; + if (pvr_dev->irq < 0) { + err =3D pvr_dev->irq; + goto err_destroy_wq; + } =20 /* Clear any pending events before requesting the IRQ line. */ pvr_fw_irq_clear(pvr_dev); pvr_fw_irq_enable(pvr_dev); =20 - return request_threaded_irq(pvr_dev->irq, pvr_device_irq_handler, - pvr_device_irq_thread_handler, - IRQF_SHARED, "gpu", pvr_dev); + return request_irq(pvr_dev->irq, pvr_device_irq_handler, 0, "gpu", pvr_de= v); + +err_destroy_wq: + destroy_workqueue(pvr_dev->irq_wq); + +err_out: + return err; } =20 /** @@ -226,6 +191,7 @@ static void pvr_device_irq_fini(struct pvr_device *pvr_dev) { free_irq(pvr_dev->irq, pvr_dev); + destroy_workqueue(pvr_dev->irq_wq); } =20 /** diff --git a/drivers/gpu/drm/imagination/pvr_device.h b/drivers/gpu/drm/ima= gination/pvr_device.h index 470945ccfcac7ce91161aa6c70d33177fbb3533f..930129334807168cf11ee843f44= 6eb5063464d55 100644 --- a/drivers/gpu/drm/imagination/pvr_device.h +++ b/drivers/gpu/drm/imagination/pvr_device.h @@ -141,9 +141,15 @@ struct pvr_device { /** @irq: IRQ number. */ int irq; =20 + /** @irq_wq: Workqueue for actions triggered off the IRQ handler. */ + struct workqueue_struct *irq_wq; + /** @fwccb: Firmware CCB. */ struct pvr_ccb fwccb; =20 + /** @fwccb_work: Work item for FWCCB processing. */ + struct work_struct fwccb_work; + /** * @kernel_vm_ctx: Virtual memory context used for kernel mappings. * @@ -210,6 +216,9 @@ struct pvr_device { /** @queues.lock: Lock protecting access to the active/idle * lists. */ struct mutex lock; + + /** @queues.work: Work item for queue processing. */ + struct work_struct work; } queues; =20 /** @@ -258,6 +267,9 @@ struct pvr_device { * future use. */ u32 reserved_count; =20 + /** @kccb.work: Work item for KCCB processing. */ + struct work_struct work; + /** * @kccb.waiters: List of KCCB slot waiters. */ diff --git a/drivers/gpu/drm/imagination/pvr_fw.c b/drivers/gpu/drm/imagina= tion/pvr_fw.c index 3debc9870a82ae7de9b2dc173df84c466c137bb3..9c8929d8602ead3390aa5c1b250= 5845b961b1406 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.c +++ b/drivers/gpu/drm/imagination/pvr_fw.c @@ -1036,6 +1036,7 @@ pvr_fw_fini(struct pvr_device *pvr_dev) * Ensure FWCCB worker has finished executing before destroying FWCCB. Th= e IRQ handler has * been unregistered at this point so no new work should be being submitt= ed. */ + flush_work(&pvr_dev->fwccb_work); pvr_ccb_fini(&pvr_dev->fwccb); pvr_kccb_fini(pvr_dev); pvr_fw_cleanup(pvr_dev); diff --git a/drivers/gpu/drm/imagination/pvr_power.c b/drivers/gpu/drm/imag= ination/pvr_power.c index 19b079b357df78e8bcdecfa377fc9c05b6e8e4b0..000ded17f7ca4c5cdadc5aba4f4= d76fac0bbcc0c 100644 --- a/drivers/gpu/drm/imagination/pvr_power.c +++ b/drivers/gpu/drm/imagination/pvr_power.c @@ -122,7 +122,7 @@ pvr_power_fw_enable(struct pvr_device *pvr_dev) return err; } =20 - queue_delayed_work(pvr_dev->sched_wq, &pvr_dev->watchdog.work, + queue_delayed_work(pvr_dev->irq_wq, &pvr_dev->watchdog.work, msecs_to_jiffies(WATCHDOG_TIME_MS)); =20 return 0; @@ -212,7 +212,7 @@ pvr_watchdog_worker(struct work_struct *work) =20 out_requeue: if (!pvr_dev->lost) { - queue_delayed_work(pvr_dev->sched_wq, &pvr_dev->watchdog.work, + queue_delayed_work(pvr_dev->irq_wq, &pvr_dev->watchdog.work, msecs_to_jiffies(WATCHDOG_TIME_MS)); } } diff --git a/drivers/gpu/drm/imagination/pvr_queue.c b/drivers/gpu/drm/imag= ination/pvr_queue.c index c4f08432882b12f5cdfeb7fc991fd941f0946676..5f6a880987d9f35804da60e1258= efa30beed56ab 100644 --- a/drivers/gpu/drm/imagination/pvr_queue.c +++ b/drivers/gpu/drm/imagination/pvr_queue.c @@ -838,7 +838,7 @@ pvr_queue_timedout_job(struct drm_sched_job *s_job) } else { atomic_set(&queue->in_flight_job_count, job_count); list_move_tail(&queue->node, &pvr_dev->queues.active); - pvr_queue_process(queue); + queue_work(pvr_dev->irq_wq, &pvr_dev->queues.work); } mutex_unlock(&pvr_dev->queues.lock); =20 @@ -991,6 +991,26 @@ void pvr_queue_process(struct pvr_queue *queue) pvr_queue_update_active_state_locked(queue); } =20 +static void pvr_queue_process_worker(struct work_struct *work) +{ + struct pvr_device *pvr_dev =3D container_of_const(work, struct pvr_device= , queues.work); + struct pvr_queue *queue, *tmp_queue; + LIST_HEAD(active_queues); + + mutex_lock(&pvr_dev->queues.lock); + + list_splice_init(&pvr_dev->queues.active, &active_queues); + + list_for_each_entry_safe(queue, tmp_queue, &active_queues, node) { + pvr_queue_check_job_waiting_for_cccb_space(queue); + pvr_queue_signal_done_fences(queue); + + pvr_queue_update_active_state_locked(queue); + } + + mutex_unlock(&pvr_dev->queues.lock); +} + static u32 get_dm_type(struct pvr_queue *queue) { switch (queue->type) { @@ -1407,6 +1427,7 @@ int pvr_queue_device_init(struct pvr_device *pvr_dev) { int err; =20 + INIT_WORK(&pvr_dev->queues.work, pvr_queue_process_worker); INIT_LIST_HEAD(&pvr_dev->queues.active); INIT_LIST_HEAD(&pvr_dev->queues.idle); err =3D drmm_mutex_init(from_pvr_device(pvr_dev), &pvr_dev->queues.lock); --=20 2.47.0 From nobody Sun Nov 24 12:34:29 2024 Received: from mx07-00376f01.pphosted.com (mx07-00376f01.pphosted.com [185.132.180.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A52AD1A08BC; Mon, 18 Nov 2024 13:03:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 18 Nov 2024 13:02:39 +0000 (GMT) Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa (172.25.16.114) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Mon, 18 Nov 2024 13:02:38 +0000 From: Matt Coster Date: Mon, 18 Nov 2024 13:02:02 +0000 Subject: [PATCH v2 10/21] drm/imagination: Remove firmware enable_reg Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241118-sets-bxs-4-64-patch-v1-v2-10-3fd45d9fb0cf@imgtec.com> References: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> In-Reply-To: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4077; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=Toz53IIpgIXLmkp0yGnmtz94H7xZNFG0wc+rzXVmIF4=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaRbWz29GmW8UZWnu6h6SoPaF/loB7Y94uUt5UImt3eXv 8m4FZDcUcrCIMbBICumyLJjheUKtT9qWhI3fhXDzGFlAhnCwMUpABO5k8rw36+P9UztriOzpBft FAg3ONDqMz961ZdSm2mTtZjc29889WH4n5PesX8Cg/gKzvub1liZmFgLnFJd3bhuQ6fYCt35QqU HeAE= X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Proofpoint-ORIG-GUID: r-wWE0BXv41NCOW1tnDkYQkYysXfbl8l X-Authority-Analysis: v=2.4 cv=E4efprdl c=1 sm=1 tr=0 ts=673b3aef cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=hzDjp0mCheYA:10 a=IkcTkHD0fZMA:10 a=VlfZXiiP6vEA:10 a=VwQbUJbxAAAA:8 a=r_1tXGB3AAAA:8 a=NvQRLi1s1fuHPRDSktsA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: r-wWE0BXv41NCOW1tnDkYQkYysXfbl8l After the previous commit ("drm/imagination: Revert to non-threaded IRQs"), this register is now only used to enable firmware interrupts at start-of-day. This is, however, unnecessary since they are enabled by default. In addition, the soon-to-be-added RISC-V firmware processors do not have an equivalent register. Signed-off-by: Matt Coster --- Changes in v2: - None - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 10-4ed30e865892@imgtec.com --- drivers/gpu/drm/imagination/pvr_device.c | 1 - drivers/gpu/drm/imagination/pvr_fw.h | 11 +---------- drivers/gpu/drm/imagination/pvr_fw_meta.c | 1 - drivers/gpu/drm/imagination/pvr_fw_mips.c | 1 - 4 files changed, 1 insertion(+), 13 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_device.c b/drivers/gpu/drm/ima= gination/pvr_device.c index 43411fe64fcecd8f84c0ceabb329f2901d63ed93..52d7641a1a0c62a9c4029092e84= 6472d82950a61 100644 --- a/drivers/gpu/drm/imagination/pvr_device.c +++ b/drivers/gpu/drm/imagination/pvr_device.c @@ -172,7 +172,6 @@ pvr_device_irq_init(struct pvr_device *pvr_dev) =20 /* Clear any pending events before requesting the IRQ line. */ pvr_fw_irq_clear(pvr_dev); - pvr_fw_irq_enable(pvr_dev); =20 return request_irq(pvr_dev->irq, pvr_device_irq_handler, 0, "gpu", pvr_de= v); =20 diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagina= tion/pvr_fw.h index b7966bd574a924862b7877c175fa2b5d757d89db..29bae4bc244a243a6a95bcf838d= 924060cc043e2 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.h +++ b/drivers/gpu/drm/imagination/pvr_fw.h @@ -188,9 +188,6 @@ struct pvr_fw_defs { * processor backend in pvr_fw_funcs::init(). */ struct { - /** @enable_reg: FW interrupt enable register. */ - u32 enable_reg; - /** @status_reg: FW interrupt status register. */ u32 status_reg; =20 @@ -202,7 +199,7 @@ struct pvr_fw_defs { */ u32 clear_reg; =20 - /** @event_mask: Bitmask of events to listen for. */ + /** @event_mask: Bitmask of events to listen for in the status_reg. */ u32 event_mask; =20 /** @clear_mask: Value to write to the clear_reg in order to clear FW IR= Qs. */ @@ -412,12 +409,6 @@ struct pvr_fw_device { #define pvr_fw_irq_clear(pvr_dev) \ pvr_fw_irq_write_reg(pvr_dev, clear, (pvr_dev)->fw_dev.defs->irq.clear_ma= sk) =20 -#define pvr_fw_irq_enable(pvr_dev) \ - pvr_fw_irq_write_reg(pvr_dev, enable, (pvr_dev)->fw_dev.defs->irq.event_m= ask) - -#define pvr_fw_irq_disable(pvr_dev) \ - pvr_fw_irq_write_reg(pvr_dev, enable, 0) - extern const struct pvr_fw_defs pvr_fw_defs_meta; extern const struct pvr_fw_defs pvr_fw_defs_mips; =20 diff --git a/drivers/gpu/drm/imagination/pvr_fw_meta.c b/drivers/gpu/drm/im= agination/pvr_fw_meta.c index c39beb70c3173ebdab13b4e810ce5d9a3419f0ba..76b24ad9aa221b6a384dc7b55ed= 2e78d2e761550 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_meta.c +++ b/drivers/gpu/drm/imagination/pvr_fw_meta.c @@ -546,7 +546,6 @@ const struct pvr_fw_defs pvr_fw_defs_meta =3D { .wrapper_init =3D pvr_meta_wrapper_init, .has_fixed_data_addr =3D pvr_meta_has_fixed_data_addr, .irq =3D { - .enable_reg =3D ROGUE_CR_META_SP_MSLVIRQENABLE, .status_reg =3D ROGUE_CR_META_SP_MSLVIRQSTATUS, .clear_reg =3D ROGUE_CR_META_SP_MSLVIRQSTATUS, .event_mask =3D ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN, diff --git a/drivers/gpu/drm/imagination/pvr_fw_mips.c b/drivers/gpu/drm/im= agination/pvr_fw_mips.c index 0bed0257e2ab75f66d8b8966b2ceac6342396fb5..c810a67eeecf1016064e76baf53= 4e31a44c859b5 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_mips.c +++ b/drivers/gpu/drm/imagination/pvr_fw_mips.c @@ -243,7 +243,6 @@ const struct pvr_fw_defs pvr_fw_defs_mips =3D { .wrapper_init =3D pvr_mips_wrapper_init, .has_fixed_data_addr =3D pvr_mips_has_fixed_data_addr, .irq =3D { - .enable_reg =3D ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE, .status_reg =3D ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS, .clear_reg =3D ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR, .event_mask =3D ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN, --=20 2.47.0 From nobody Sun Nov 24 12:34:29 2024 Received: from mx07-00376f01.pphosted.com (mx07-00376f01.pphosted.com [185.132.180.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C87DB1991C6; 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Mon, 18 Nov 2024 13:02:39 +0000 (GMT) Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa (172.25.16.114) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Mon, 18 Nov 2024 13:02:38 +0000 From: Matt Coster Date: Mon, 18 Nov 2024 13:02:03 +0000 Subject: [PATCH v2 11/21] drm/imagination: Rename event_mask -> status_mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241118-sets-bxs-4-64-patch-v1-v2-11-3fd45d9fb0cf@imgtec.com> References: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> In-Reply-To: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Signed-off-by: Matt Coster --- Changes in v2: - None - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 11-4ed30e865892@imgtec.com --- drivers/gpu/drm/imagination/pvr_fw.h | 6 +++--- drivers/gpu/drm/imagination/pvr_fw_meta.c | 2 +- drivers/gpu/drm/imagination/pvr_fw_mips.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagina= tion/pvr_fw.h index 29bae4bc244a243a6a95bcf838d924060cc043e2..eead744835726712622d5aba9b3= 480fe264a089f 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.h +++ b/drivers/gpu/drm/imagination/pvr_fw.h @@ -199,8 +199,8 @@ struct pvr_fw_defs { */ u32 clear_reg; =20 - /** @event_mask: Bitmask of events to listen for in the status_reg. */ - u32 event_mask; + /** @status_mask: Bitmask of events to listen for in the status_reg. */ + u32 status_mask; =20 /** @clear_mask: Value to write to the clear_reg in order to clear FW IR= Qs. */ u32 clear_mask; @@ -404,7 +404,7 @@ struct pvr_fw_device { pvr_cr_write32((pvr_dev), (pvr_dev)->fw_dev.defs->irq.name ## _reg, value) =20 #define pvr_fw_irq_pending(pvr_dev) \ - (pvr_fw_irq_read_reg(pvr_dev, status) & (pvr_dev)->fw_dev.defs->irq.event= _mask) + (pvr_fw_irq_read_reg(pvr_dev, status) & (pvr_dev)->fw_dev.defs->irq.statu= s_mask) =20 #define pvr_fw_irq_clear(pvr_dev) \ pvr_fw_irq_write_reg(pvr_dev, clear, (pvr_dev)->fw_dev.defs->irq.clear_ma= sk) diff --git a/drivers/gpu/drm/imagination/pvr_fw_meta.c b/drivers/gpu/drm/im= agination/pvr_fw_meta.c index 76b24ad9aa221b6a384dc7b55ed2e78d2e761550..cf86701ca8f14920329ccb4c281= 1424b0c394b14 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_meta.c +++ b/drivers/gpu/drm/imagination/pvr_fw_meta.c @@ -548,7 +548,7 @@ const struct pvr_fw_defs pvr_fw_defs_meta =3D { .irq =3D { .status_reg =3D ROGUE_CR_META_SP_MSLVIRQSTATUS, .clear_reg =3D ROGUE_CR_META_SP_MSLVIRQSTATUS, - .event_mask =3D ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN, + .status_mask =3D ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN, .clear_mask =3D ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK, }, }; 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Mon, 18 Nov 2024 13:02:40 +0000 (GMT) Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa (172.25.16.114) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Mon, 18 Nov 2024 13:02:39 +0000 From: Matt Coster Date: Mon, 18 Nov 2024 13:02:04 +0000 Subject: [PATCH v2 12/21] drm/imagination: Make has_fixed_data_addr a value Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241118-sets-bxs-4-64-patch-v1-v2-12-3fd45d9fb0cf@imgtec.com> References: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> In-Reply-To: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4835; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=nOt5ApVgZuETQYzKBPBYt6GJLr9diaqfv44XAVaDcyk=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaRbWz0VXPaKzVX0ibzc2uM7GZzqNtxaF3O29x2L5WvGw kucfB1mHaUsDGIcDLJiiiw7VliuUPujpiVx41cxzBxWJpAhDFycAjCRCecY/qdG6BReuaOUZdW+ O+1q8oplM7hcIu5sPm2Zs3PrU4vjnqKMDAdFL1nWJM3x+nlLXpLttex8B8tFOxkuWhRYrDgce1J kMzcA X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Proofpoint-ORIG-GUID: AVrWksr7rEKzpG4eSoxnjOfP7NgwNsGs X-Authority-Analysis: v=2.4 cv=E4efprdl c=1 sm=1 tr=0 ts=673b3af0 cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=hzDjp0mCheYA:10 a=IkcTkHD0fZMA:10 a=VlfZXiiP6vEA:10 a=VwQbUJbxAAAA:8 a=r_1tXGB3AAAA:8 a=_sBYpape5WJv0mR81mQA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: AVrWksr7rEKzpG4eSoxnjOfP7NgwNsGs This is currently a callback function which takes no parameters; there's no reason for this so let's make it a straightforward value in pvr_fw_defs. Signed-off-by: Matt Coster --- Changes in v2: - None - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 12-4ed30e865892@imgtec.com --- drivers/gpu/drm/imagination/pvr_fw.c | 2 +- drivers/gpu/drm/imagination/pvr_fw.h | 23 ++++++++--------------- drivers/gpu/drm/imagination/pvr_fw_meta.c | 8 +------- drivers/gpu/drm/imagination/pvr_fw_mips.c | 8 +------- 4 files changed, 11 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_fw.c b/drivers/gpu/drm/imagina= tion/pvr_fw.c index 9c8929d8602ead3390aa5c1b2505845b961b1406..808844eb10b5ccb29ed2b8e9bdf= e3be829cc57d1 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.c +++ b/drivers/gpu/drm/imagination/pvr_fw.c @@ -663,7 +663,7 @@ pvr_fw_process(struct pvr_device *pvr_dev) return PTR_ERR(fw_code_ptr); } =20 - if (pvr_dev->fw_dev.defs->has_fixed_data_addr()) { + if (pvr_dev->fw_dev.defs->has_fixed_data_addr) { u32 base_addr =3D private_data->base_addr & pvr_dev->fw_dev.fw_heap_info= .offset_mask; =20 fw_data_ptr =3D diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagina= tion/pvr_fw.h index eead744835726712622d5aba9b3480fe264a089f..180d310074e3585c641e540a9e2= 576b5ab2a5705 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.h +++ b/drivers/gpu/drm/imagination/pvr_fw.h @@ -166,21 +166,6 @@ struct pvr_fw_defs { */ int (*wrapper_init)(struct pvr_device *pvr_dev); =20 - /** - * @has_fixed_data_addr: - * - * Called to check if firmware fixed data must be loaded at the address g= iven by the - * firmware layout table. - * - * This function is mandatory. - * - * Returns: - * * %true if firmware fixed data must be loaded at the address given by= the firmware - * layout table. - * * %false otherwise. - */ - bool (*has_fixed_data_addr)(void); - /** * @irq: FW Interrupt information. * @@ -205,6 +190,14 @@ struct pvr_fw_defs { /** @clear_mask: Value to write to the clear_reg in order to clear FW IR= Qs. */ u32 clear_mask; } irq; + + /** + * @has_fixed_data_addr: Specify whether the firmware fixed data must be = loaded at the + * address given by the firmware layout table. + * + * This value is mandatory. + */ + bool has_fixed_data_addr; }; =20 /** diff --git a/drivers/gpu/drm/imagination/pvr_fw_meta.c b/drivers/gpu/drm/im= agination/pvr_fw_meta.c index cf86701ca8f14920329ccb4c2811424b0c394b14..4433b04e0adb3684b86a4e90f63= d670a81ecd826 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_meta.c +++ b/drivers/gpu/drm/imagination/pvr_fw_meta.c @@ -531,12 +531,6 @@ pvr_meta_vm_unmap(struct pvr_device *pvr_dev, struct p= vr_fw_object *fw_obj) fw_obj->fw_mm_node.size); } =20 -static bool -pvr_meta_has_fixed_data_addr(void) -{ - return false; -} - const struct pvr_fw_defs pvr_fw_defs_meta =3D { .init =3D pvr_meta_init, .fw_process =3D pvr_meta_fw_process, @@ -544,11 +538,11 @@ const struct pvr_fw_defs pvr_fw_defs_meta =3D { .vm_unmap =3D pvr_meta_vm_unmap, .get_fw_addr_with_offset =3D pvr_meta_get_fw_addr_with_offset, .wrapper_init =3D pvr_meta_wrapper_init, - .has_fixed_data_addr =3D pvr_meta_has_fixed_data_addr, .irq =3D { .status_reg =3D ROGUE_CR_META_SP_MSLVIRQSTATUS, .clear_reg =3D ROGUE_CR_META_SP_MSLVIRQSTATUS, .status_mask =3D ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN, .clear_mask =3D ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK, }, + .has_fixed_data_addr =3D false, }; diff --git a/drivers/gpu/drm/imagination/pvr_fw_mips.c b/drivers/gpu/drm/im= agination/pvr_fw_mips.c index f195c602bb112066e88210d0106cb5ffc0a9abc6..2c3172841886b70eb7a9992ec38= 51f18adcad8d5 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_mips.c +++ b/drivers/gpu/drm/imagination/pvr_fw_mips.c @@ -227,12 +227,6 @@ pvr_mips_get_fw_addr_with_offset(struct pvr_fw_object = *fw_obj, u32 offset) ROGUE_FW_HEAP_MIPS_BASE; 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Mon, 18 Nov 2024 13:02:41 +0000 (GMT) Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa (172.25.16.114) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Mon, 18 Nov 2024 13:02:39 +0000 From: Matt Coster Date: Mon, 18 Nov 2024 13:02:05 +0000 Subject: [PATCH v2 13/21] drm/imagination: Use a lookup table for fw defs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241118-sets-bxs-4-64-patch-v1-v2-13-3fd45d9fb0cf@imgtec.com> References: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> In-Reply-To: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Use a static array indexed on pvr_fw_processor_type (which is now a proper enum instead of #defines) instead. Signed-off-by: Matt Coster --- Changes in v2: - None - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 13-4ed30e865892@imgtec.com --- drivers/gpu/drm/imagination/pvr_device.h | 4 ---- drivers/gpu/drm/imagination/pvr_fw.c | 21 ++++++++++++++++----- drivers/gpu/drm/imagination/pvr_fw.h | 7 +++++++ 3 files changed, 23 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_device.h b/drivers/gpu/drm/ima= gination/pvr_device.h index 930129334807168cf11ee843f446eb5063464d55..ec5eb78af82a3f3c32d6c89b68b= 7bc0fcee0b9d2 100644 --- a/drivers/gpu/drm/imagination/pvr_device.h +++ b/drivers/gpu/drm/imagination/pvr_device.h @@ -738,8 +738,4 @@ pvr_ioctl_union_padding_check(void *instance, size_t un= ion_offset, __union_size, __member_size); \ }) =20 -#define PVR_FW_PROCESSOR_TYPE_META 0 -#define PVR_FW_PROCESSOR_TYPE_MIPS 1 -#define PVR_FW_PROCESSOR_TYPE_RISCV 2 - #endif /* PVR_DEVICE_H */ diff --git a/drivers/gpu/drm/imagination/pvr_fw.c b/drivers/gpu/drm/imagina= tion/pvr_fw.c index 808844eb10b5ccb29ed2b8e9bdfe3be829cc57d1..b77c4a42caf2f208f6289160e5c= ec36c683b1e65 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.c +++ b/drivers/gpu/drm/imagination/pvr_fw.c @@ -926,16 +926,27 @@ pvr_fw_validate_init_device_info(struct pvr_device *p= vr_dev) int pvr_fw_init(struct pvr_device *pvr_dev) { + static const struct pvr_fw_defs *fw_defs[PVR_FW_PROCESSOR_TYPE_COUNT] =3D= { + [PVR_FW_PROCESSOR_TYPE_META] =3D &pvr_fw_defs_meta, + [PVR_FW_PROCESSOR_TYPE_MIPS] =3D &pvr_fw_defs_mips, + [PVR_FW_PROCESSOR_TYPE_RISCV] =3D NULL, + }; + u32 kccb_size_log2 =3D ROGUE_FWIF_KCCB_NUMCMDS_LOG2_DEFAULT; u32 kccb_rtn_size =3D (1 << kccb_size_log2) * sizeof(*pvr_dev->kccb.rtn); struct pvr_fw_device *fw_dev =3D &pvr_dev->fw_dev; int err; =20 - if (fw_dev->processor_type =3D=3D PVR_FW_PROCESSOR_TYPE_META) - fw_dev->defs =3D &pvr_fw_defs_meta; - else if (fw_dev->processor_type =3D=3D PVR_FW_PROCESSOR_TYPE_MIPS) - fw_dev->defs =3D &pvr_fw_defs_mips; - else + if (fw_dev->processor_type >=3D PVR_FW_PROCESSOR_TYPE_COUNT) + return -EINVAL; + + fw_dev->defs =3D fw_defs[fw_dev->processor_type]; + + /* + * Not all firmware processor types are currently supported. + * Once they are, this check can be removed. + */ + if (!fw_dev->defs) return -EINVAL; =20 err =3D fw_dev->defs->init(pvr_dev); diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagina= tion/pvr_fw.h index 180d310074e3585c641e540a9e2576b5ab2a5705..88ad713468ce3a1ee459b04dde5= 363c24791a4f1 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.h +++ b/drivers/gpu/drm/imagination/pvr_fw.h @@ -402,6 +402,13 @@ struct pvr_fw_device { #define pvr_fw_irq_clear(pvr_dev) \ pvr_fw_irq_write_reg(pvr_dev, clear, (pvr_dev)->fw_dev.defs->irq.clear_ma= sk) =20 +enum pvr_fw_processor_type { + PVR_FW_PROCESSOR_TYPE_META =3D 0, + PVR_FW_PROCESSOR_TYPE_MIPS, + PVR_FW_PROCESSOR_TYPE_RISCV, + PVR_FW_PROCESSOR_TYPE_COUNT, +}; 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Mon, 18 Nov 2024 13:02:40 +0000 From: Matt Coster Date: Mon, 18 Nov 2024 13:02:06 +0000 Subject: [PATCH v2 14/21] drm/imagination: Use callbacks for fw irq handling Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241118-sets-bxs-4-64-patch-v1-v2-14-3fd45d9fb0cf@imgtec.com> References: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> In-Reply-To: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6860; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=HtINBE16dRwtsNH1r+/yJtIFe6VjO7f0xTf6DhF+fFg=; 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Signed-off-by: Matt Coster --- Changes in v2: - None - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 14-4ed30e865892@imgtec.com --- drivers/gpu/drm/imagination/pvr_device.h | 18 +++++++++++++ drivers/gpu/drm/imagination/pvr_fw.h | 45 +++++++++------------------= ---- drivers/gpu/drm/imagination/pvr_fw_meta.c | 22 ++++++++++----- drivers/gpu/drm/imagination/pvr_fw_mips.c | 22 ++++++++++----- 4 files changed, 63 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_device.h b/drivers/gpu/drm/ima= gination/pvr_device.h index ec5eb78af82a3f3c32d6c89b68b7bc0fcee0b9d2..76f79b18af354f0e0070530dfc5= c8fe0f6a41ce1 100644 --- a/drivers/gpu/drm/imagination/pvr_device.h +++ b/drivers/gpu/drm/imagination/pvr_device.h @@ -738,4 +738,22 @@ pvr_ioctl_union_padding_check(void *instance, size_t u= nion_offset, __union_size, __member_size); \ }) =20 +/* + * These utility functions should more properly be placed in pvr_fw.h, but= that + * would cause a dependency cycle between that header and this one. Since + * they're primarily used in pvr_device.c, let's put them in here for now. + */ + +static __always_inline bool +pvr_fw_irq_pending(struct pvr_device *pvr_dev) +{ + return pvr_dev->fw_dev.defs->irq_pending(pvr_dev); +} + +static __always_inline void +pvr_fw_irq_clear(struct pvr_device *pvr_dev) +{ + pvr_dev->fw_dev.defs->irq_clear(pvr_dev); +} + #endif /* PVR_DEVICE_H */ diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagina= tion/pvr_fw.h index 88ad713468ce3a1ee459b04dde5363c24791a4f1..ab69f40a7fbc6304171f16dd16d= 825a68b0362a5 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.h +++ b/drivers/gpu/drm/imagination/pvr_fw.h @@ -167,29 +167,22 @@ struct pvr_fw_defs { int (*wrapper_init)(struct pvr_device *pvr_dev); =20 /** - * @irq: FW Interrupt information. + * @irq_pending: Check interrupt status register for pending interrupts. * - * Those are processor dependent, and should be initialized by the - * processor backend in pvr_fw_funcs::init(). + * @pvr_dev: Target PowerVR device. + * + * This function is mandatory. */ - struct { - /** @status_reg: FW interrupt status register. */ - u32 status_reg; + bool (*irq_pending)(struct pvr_device *pvr_dev); =20 - /** - * @clear_reg: FW interrupt clear register. - * - * If @status_reg =3D=3D @clear_reg, we clear by write a bit to zero, - * otherwise we clear by writing a bit to one. - */ - u32 clear_reg; - - /** @status_mask: Bitmask of events to listen for in the status_reg. */ - u32 status_mask; - - /** @clear_mask: Value to write to the clear_reg in order to clear FW IR= Qs. */ - u32 clear_mask; - } irq; + /** + * @irq_clear: Clear pending interrupts. + * + * @pvr_dev: Target PowerVR device. + * + * This function is mandatory. + */ + void (*irq_clear)(struct pvr_device *pvr_dev); =20 /** * @has_fixed_data_addr: Specify whether the firmware fixed data must be = loaded at the @@ -390,18 +383,6 @@ struct pvr_fw_device { } fw_objs; }; =20 -#define pvr_fw_irq_read_reg(pvr_dev, name) \ - pvr_cr_read32((pvr_dev), (pvr_dev)->fw_dev.defs->irq.name ## _reg) - -#define pvr_fw_irq_write_reg(pvr_dev, name, value) \ - pvr_cr_write32((pvr_dev), (pvr_dev)->fw_dev.defs->irq.name ## _reg, value) - -#define pvr_fw_irq_pending(pvr_dev) \ - (pvr_fw_irq_read_reg(pvr_dev, status) & (pvr_dev)->fw_dev.defs->irq.statu= s_mask) - -#define pvr_fw_irq_clear(pvr_dev) \ - pvr_fw_irq_write_reg(pvr_dev, clear, (pvr_dev)->fw_dev.defs->irq.clear_ma= sk) - enum pvr_fw_processor_type { PVR_FW_PROCESSOR_TYPE_META =3D 0, PVR_FW_PROCESSOR_TYPE_MIPS, diff --git a/drivers/gpu/drm/imagination/pvr_fw_meta.c b/drivers/gpu/drm/im= agination/pvr_fw_meta.c index 4433b04e0adb3684b86a4e90f63d670a81ecd826..09de3a30b625013c190196e0207= 4fe72d08629a6 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_meta.c +++ b/drivers/gpu/drm/imagination/pvr_fw_meta.c @@ -531,6 +531,20 @@ pvr_meta_vm_unmap(struct pvr_device *pvr_dev, struct p= vr_fw_object *fw_obj) fw_obj->fw_mm_node.size); } =20 +static bool +pvr_meta_irq_pending(struct pvr_device *pvr_dev) +{ + return pvr_cr_read32(pvr_dev, ROGUE_CR_META_SP_MSLVIRQSTATUS) & + ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN; +} + +static void +pvr_meta_irq_clear(struct pvr_device *pvr_dev) +{ + pvr_cr_write32(pvr_dev, ROGUE_CR_META_SP_MSLVIRQSTATUS, + ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK); +} + const struct pvr_fw_defs pvr_fw_defs_meta =3D { .init =3D pvr_meta_init, .fw_process =3D pvr_meta_fw_process, @@ -538,11 +552,7 @@ const struct pvr_fw_defs pvr_fw_defs_meta =3D { .vm_unmap =3D pvr_meta_vm_unmap, .get_fw_addr_with_offset =3D pvr_meta_get_fw_addr_with_offset, .wrapper_init =3D pvr_meta_wrapper_init, - .irq =3D { - .status_reg =3D ROGUE_CR_META_SP_MSLVIRQSTATUS, - .clear_reg =3D ROGUE_CR_META_SP_MSLVIRQSTATUS, - .status_mask =3D ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN, - .clear_mask =3D ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK, - }, + .irq_pending =3D pvr_meta_irq_pending, + .irq_clear =3D pvr_meta_irq_clear, .has_fixed_data_addr =3D false, }; diff --git a/drivers/gpu/drm/imagination/pvr_fw_mips.c b/drivers/gpu/drm/im= agination/pvr_fw_mips.c index 2c3172841886b70eb7a9992ec3851f18adcad8d5..524a9bd0a20b64c509f5708cc61= d93b4c864b835 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_mips.c +++ b/drivers/gpu/drm/imagination/pvr_fw_mips.c @@ -227,6 +227,20 @@ pvr_mips_get_fw_addr_with_offset(struct pvr_fw_object = *fw_obj, u32 offset) ROGUE_FW_HEAP_MIPS_BASE; } =20 +static bool +pvr_mips_irq_pending(struct pvr_device *pvr_dev) +{ + return pvr_cr_read32(pvr_dev, ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS) & + ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN; +} + +static void +pvr_mips_irq_clear(struct pvr_device *pvr_dev) +{ + pvr_cr_write32(pvr_dev, ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR, + ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_EN); +} + const struct pvr_fw_defs pvr_fw_defs_mips =3D { .init =3D pvr_mips_init, .fini =3D pvr_mips_fini, @@ -235,11 +249,7 @@ const struct pvr_fw_defs pvr_fw_defs_mips =3D { .vm_unmap =3D pvr_vm_mips_unmap, .get_fw_addr_with_offset =3D pvr_mips_get_fw_addr_with_offset, .wrapper_init =3D pvr_mips_wrapper_init, - .irq =3D { - .status_reg =3D ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS, - .clear_reg =3D ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR, - .status_mask =3D ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN, - .clear_mask =3D ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_EN, - }, + .irq_pending =3D pvr_mips_irq_pending, + .irq_clear =3D pvr_mips_irq_clear, .has_fixed_data_addr =3D true, }; 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ROGUE_CR_FWCORE_DMI_DMCONTROL is used to control the debug module in the firmware processor. Signed-off-by: Matt Coster --- Changes in v2: - None - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 15-4ed30e865892@imgtec.com --- drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h b/drivers/gpu/= drm/imagination/pvr_rogue_cr_defs.h index 2a90d02796d3e071b18e18dead105e29798bcddc..4e99832a667a2d88ee21469595d= 3abdad3a07c06 100644 --- a/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h +++ b/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h @@ -3751,7 +3751,22 @@ =20 /* Register ROGUE_CR_FWCORE_DMI_DMCONTROL */ #define ROGUE_CR_FWCORE_DMI_DMCONTROL 0x3480U -#define ROGUE_CR_FWCORE_DMI_DMCONTROL_MASKFULL 0x0000000000000000ULL +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_MASKFULL 0x00000000D0000003ULL +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_HALTREQ_SHIFT 31U +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_HALTREQ_CLRMSK 0x7FFFFFFFULL +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_HALTREQ_EN 0x80000000ULL +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_RESUMEREQ_SHIFT 30U +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_RESUMEREQ_CLRMSK 0xBFFFFFFFULL +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_RESUMEREQ_EN 0x40000000ULL +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_ACKHAVERESET_SHIFT 28U +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_ACKHAVERESET_CLRMSK 0xEFFFFFFFULL +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_ACKHAVERESET_EN 0x10000000ULL +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_NDMRESET_SHIFT 1U +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_NDMRESET_CLRMSK 0xFFFFFFFDULL +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_NDMRESET_EN 0x00000002ULL +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_DMACTIVE_SHIFT 0U +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_DMACTIVE_CLRMSK 0xFFFFFFFEULL +#define ROGUE_CR_FWCORE_DMI_DMCONTROL_DMACTIVE_EN 0x00000001ULL =20 /* Register ROGUE_CR_FWCORE_DMI_DMSTATUS */ #define ROGUE_CR_FWCORE_DMI_DMSTATUS 0x3488U --=20 2.47.0 From nobody Sun Nov 24 12:34:29 2024 Received: from mx07-00376f01.pphosted.com (mx07-00376f01.pphosted.com [185.132.180.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF4C919AD7E; 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Mon, 18 Nov 2024 13:02:43 +0000 (GMT) Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa (172.25.16.114) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Mon, 18 Nov 2024 13:02:42 +0000 From: Matt Coster Date: Mon, 18 Nov 2024 13:02:08 +0000 Subject: [PATCH v2 16/21] drm/imagination: Move ELF fw utils to common file Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241118-sets-bxs-4-64-patch-v1-v2-16-3fd45d9fb0cf@imgtec.com> References: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> In-Reply-To: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7232; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=xXbzl2XXxqkx/Lfmf4ybowFt9Rq0TJ6W0fChWIkO/O0=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaRbWz27m3j91jbLQM3+GSzfWThaKmylXUVvyXTzNb1iW ipw6XJXRykLgxgHg6yYIsuOFZYr1P6oaUnc+FUMM4eVCWQIAxenAExkWw3DX3mDyGNdjjGvus4/ LcvUuBN16nvRotfLXZyV/Q58N75xLZyR4bJyhuc3/fBH6/4tnq7QO7npldd2P//Q1WGSi5l1P90 R4wMA X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Proofpoint-ORIG-GUID: 03jTR1EQgqUoVGFkkscmnqrGGxI_nylN X-Authority-Analysis: v=2.4 cv=E4efprdl c=1 sm=1 tr=0 ts=673b3af3 cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=hzDjp0mCheYA:10 a=IkcTkHD0fZMA:10 a=VlfZXiiP6vEA:10 a=VwQbUJbxAAAA:8 a=r_1tXGB3AAAA:8 a=gtgaOig2gG6QrLUE_6sA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: 03jTR1EQgqUoVGFkkscmnqrGGxI_nylN Currently only MIPS firmware processors use ELF-formatted firmware. When adding support for RISC-V firmware processors, it will be useful to have ELF handling functions ready to go. Signed-off-by: Matt Coster --- Changes in v2: - None - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 16-4ed30e865892@imgtec.com --- drivers/gpu/drm/imagination/Makefile | 1 + drivers/gpu/drm/imagination/pvr_fw.h | 5 +++ drivers/gpu/drm/imagination/pvr_fw_mips.c | 59 +-------------------------- drivers/gpu/drm/imagination/pvr_fw_util.c | 67 +++++++++++++++++++++++++++= ++++ 4 files changed, 75 insertions(+), 57 deletions(-) diff --git a/drivers/gpu/drm/imagination/Makefile b/drivers/gpu/drm/imagina= tion/Makefile index 9bc6a3884c2239e44265f3cdebee149841b270de..077e4762c7c383b6e339da1584c= 3865d830ef8d6 100644 --- a/drivers/gpu/drm/imagination/Makefile +++ b/drivers/gpu/drm/imagination/Makefile @@ -16,6 +16,7 @@ powervr-y :=3D \ pvr_fw_mips.o \ pvr_fw_startstop.o \ pvr_fw_trace.o \ + pvr_fw_util.o \ pvr_gem.o \ pvr_hwrt.o \ pvr_job.o \ diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagina= tion/pvr_fw.h index ab69f40a7fbc6304171f16dd16d825a68b0362a5..8d3f0ee0aac69373f15ac5919d5= b0f27c67cb284 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.h +++ b/drivers/gpu/drm/imagination/pvr_fw.h @@ -478,4 +478,9 @@ pvr_fw_object_get_fw_addr(struct pvr_fw_object *fw_obj,= u32 *fw_addr_out) pvr_fw_object_get_fw_addr_offset(fw_obj, 0, fw_addr_out); } =20 +/* Util functions defined in pvr_util.c. These are intended for use in pvr= _fw_.c files. */ +int +pvr_fw_process_elf_command_stream(struct pvr_device *pvr_dev, const u8 *fw= , u8 *fw_code_ptr, + u8 *fw_data_ptr, u8 *fw_core_code_ptr, u8 *fw_core_data_ptr); + #endif /* PVR_FW_H */ diff --git a/drivers/gpu/drm/imagination/pvr_fw_mips.c b/drivers/gpu/drm/im= agination/pvr_fw_mips.c index 524a9bd0a20b64c509f5708cc61d93b4c864b835..7f341ceb0661c61ac059654faee= c91e149036467 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_mips.c +++ b/drivers/gpu/drm/imagination/pvr_fw_mips.c @@ -8,7 +8,6 @@ #include "pvr_rogue_mips.h" #include "pvr_vm_mips.h" =20 -#include #include #include =20 @@ -16,60 +15,6 @@ #define ROGUE_FW_HEAP_MIPS_SHIFT 24 /* 16 MB */ #define ROGUE_FW_HEAP_MIPS_RESERVED_SIZE SZ_1M =20 -/** - * process_elf_command_stream() - Process ELF firmware image and populate - * firmware sections - * @pvr_dev: Device pointer. - * @fw: Pointer to firmware image. - * @fw_code_ptr: Pointer to FW code section. - * @fw_data_ptr: Pointer to FW data section. - * @fw_core_code_ptr: Pointer to FW coremem code section. - * @fw_core_data_ptr: Pointer to FW coremem data section. - * - * Returns : - * * 0 on success, or - * * -EINVAL on any error in ELF command stream. - */ -static int -process_elf_command_stream(struct pvr_device *pvr_dev, const u8 *fw, u8 *f= w_code_ptr, - u8 *fw_data_ptr, u8 *fw_core_code_ptr, u8 *fw_core_data_ptr) -{ - struct elf32_hdr *header =3D (struct elf32_hdr *)fw; - struct elf32_phdr *program_header =3D (struct elf32_phdr *)(fw + header->= e_phoff); - struct drm_device *drm_dev =3D from_pvr_device(pvr_dev); - u32 entry; - int err; - - for (entry =3D 0; entry < header->e_phnum; entry++, program_header++) { - void *write_addr; - - /* Only consider loadable entries in the ELF segment table */ - if (program_header->p_type !=3D PT_LOAD) - continue; - - err =3D pvr_fw_find_mmu_segment(pvr_dev, program_header->p_vaddr, - program_header->p_memsz, fw_code_ptr, fw_data_ptr, - fw_core_code_ptr, fw_core_data_ptr, &write_addr); - if (err) { - drm_err(drm_dev, - "Addr 0x%x (size: %d) not found in any firmware segment", - program_header->p_vaddr, program_header->p_memsz); - return err; - } - - /* Write to FW allocation only if available */ - if (write_addr) { - memcpy(write_addr, fw + program_header->p_offset, - program_header->p_filesz); - - memset((u8 *)write_addr + program_header->p_filesz, 0, - program_header->p_memsz - program_header->p_filesz); - } - } - - return 0; -} - static int pvr_mips_init(struct pvr_device *pvr_dev) { @@ -100,8 +45,8 @@ pvr_mips_fw_process(struct pvr_device *pvr_dev, const u8= *fw, u32 page_nr; int err; =20 - err =3D process_elf_command_stream(pvr_dev, fw, fw_code_ptr, fw_data_ptr,= fw_core_code_ptr, - fw_core_data_ptr); + err =3D pvr_fw_process_elf_command_stream(pvr_dev, fw, fw_code_ptr, fw_da= ta_ptr, + fw_core_code_ptr, fw_core_data_ptr); if (err) return err; =20 diff --git a/drivers/gpu/drm/imagination/pvr_fw_util.c b/drivers/gpu/drm/im= agination/pvr_fw_util.c new file mode 100644 index 0000000000000000000000000000000000000000..7bc8a5c48e9b0eed2045607ab2c= fed80a60a32b5 --- /dev/null +++ b/drivers/gpu/drm/imagination/pvr_fw_util.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* Copyright (c) 2024 Imagination Technologies Ltd. */ + +#include "pvr_device.h" +#include "pvr_fw.h" + +#include +#include + +#include +#include +#include + +/** + * pvr_fw_process_elf_command_stream() - Process ELF firmware image and po= pulate + * firmware sections + * @pvr_dev: Device pointer. + * @fw: Pointer to firmware image. + * @fw_code_ptr: Pointer to FW code section. + * @fw_data_ptr: Pointer to FW data section. + * @fw_core_code_ptr: Pointer to FW coremem code section. + * @fw_core_data_ptr: Pointer to FW coremem data section. + * + * Returns : + * * 0 on success, or + * * -EINVAL on any error in ELF command stream. + */ +int +pvr_fw_process_elf_command_stream(struct pvr_device *pvr_dev, const u8 *fw, + u8 *fw_code_ptr, u8 *fw_data_ptr, + u8 *fw_core_code_ptr, u8 *fw_core_data_ptr) +{ + struct elf32_hdr *header =3D (struct elf32_hdr *)fw; + struct elf32_phdr *program_header =3D (struct elf32_phdr *)(fw + header->= e_phoff); + struct drm_device *drm_dev =3D from_pvr_device(pvr_dev); + u32 entry; + int err; + + for (entry =3D 0; entry < header->e_phnum; entry++, program_header++) { + void *write_addr; + + /* Only consider loadable entries in the ELF segment table */ + if (program_header->p_type !=3D PT_LOAD) + continue; + + err =3D pvr_fw_find_mmu_segment(pvr_dev, program_header->p_vaddr, + program_header->p_memsz, fw_code_ptr, fw_data_ptr, + fw_core_code_ptr, fw_core_data_ptr, &write_addr); + if (err) { + drm_err(drm_dev, + "Addr 0x%x (size: %d) not found in any firmware segment", + program_header->p_vaddr, program_header->p_memsz); + return err; + } + + /* Write to FW allocation only if available */ + if (write_addr) { + memcpy(write_addr, fw + program_header->p_offset, + program_header->p_filesz); + + memset((u8 *)write_addr + program_header->p_filesz, 0, + program_header->p_memsz - program_header->p_filesz); + } + } + + return 0; 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Mon, 18 Nov 2024 13:02:44 +0000 (GMT) Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa (172.25.16.114) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Mon, 18 Nov 2024 13:02:42 +0000 From: Matt Coster Date: Mon, 18 Nov 2024 13:02:09 +0000 Subject: [PATCH v2 17/21] drm/imagination: Add RISC-V firmware processor support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241118-sets-bxs-4-64-patch-v1-v2-17-3fd45d9fb0cf@imgtec.com> References: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> In-Reply-To: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge , Sarah Walker X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=13021; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=p9VueALeBg41eruXFYhkM6kUFzwJq/l25ze51is+Vd0=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaRbWz17lhXol3FKleWC2fdP6WuPNuUdzuWz19O5zfT9l n3eiQU6HaUsDGIcDLJiiiw7VliuUPujpiVx41cxzBxWJpAhDFycAjCRhn8M/yzdXI9GLm5cvvGp 5yH1idx3bO9btF/92uD3zvuZgOYJzwSGf9b2QSw3sgP6Uw+0HV49b9P/T4d111R06dzbtPdP28q MYFYA X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Proofpoint-ORIG-GUID: 3GDD_Gcn-EcxOXv1EPp4kyUCOXa-i-lN X-Authority-Analysis: v=2.4 cv=E4efprdl c=1 sm=1 tr=0 ts=673b3af4 cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=hzDjp0mCheYA:10 a=IkcTkHD0fZMA:10 a=VlfZXiiP6vEA:10 a=VwQbUJbxAAAA:8 a=r_1tXGB3AAAA:8 a=ZOYM-m_f2s-OnT4_e-EA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: 3GDD_Gcn-EcxOXv1EPp4kyUCOXa-i-lN From: Sarah Walker Newer PowerVR GPUs (such as the BXS-4-64 MC1) use a RISC-V firmware processor instead of the previous MIPS or META. Signed-off-by: Sarah Walker Signed-off-by: Matt Coster --- Changes in v2: - None - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 17-4ed30e865892@imgtec.com --- drivers/gpu/drm/imagination/Makefile | 1 + drivers/gpu/drm/imagination/pvr_fw.c | 18 +-- drivers/gpu/drm/imagination/pvr_fw.h | 10 ++ drivers/gpu/drm/imagination/pvr_fw_riscv.c | 163 +++++++++++++++++++++= ++++ drivers/gpu/drm/imagination/pvr_fw_startstop.c | 21 ++++ drivers/gpu/drm/imagination/pvr_rogue_riscv.h | 41 +++++++ 6 files changed, 246 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/imagination/Makefile b/drivers/gpu/drm/imagina= tion/Makefile index 077e4762c7c383b6e339da1584c3865d830ef8d6..d748ad9d62e092ed7c3d772214c= cd327818d507f 100644 --- a/drivers/gpu/drm/imagination/Makefile +++ b/drivers/gpu/drm/imagination/Makefile @@ -14,6 +14,7 @@ powervr-y :=3D \ pvr_fw.o \ pvr_fw_meta.o \ pvr_fw_mips.o \ + pvr_fw_riscv.o \ pvr_fw_startstop.o \ pvr_fw_trace.o \ pvr_fw_util.o \ diff --git a/drivers/gpu/drm/imagination/pvr_fw.c b/drivers/gpu/drm/imagina= tion/pvr_fw.c index b77c4a42caf2f208f6289160e5cec36c683b1e65..7373220fa4fc05f5beb239f1ceb= 92b3caba97765 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.c +++ b/drivers/gpu/drm/imagination/pvr_fw.c @@ -929,7 +929,7 @@ pvr_fw_init(struct pvr_device *pvr_dev) static const struct pvr_fw_defs *fw_defs[PVR_FW_PROCESSOR_TYPE_COUNT] =3D= { [PVR_FW_PROCESSOR_TYPE_META] =3D &pvr_fw_defs_meta, [PVR_FW_PROCESSOR_TYPE_MIPS] =3D &pvr_fw_defs_mips, - [PVR_FW_PROCESSOR_TYPE_RISCV] =3D NULL, + [PVR_FW_PROCESSOR_TYPE_RISCV] =3D &pvr_fw_defs_riscv, }; =20 u32 kccb_size_log2 =3D ROGUE_FWIF_KCCB_NUMCMDS_LOG2_DEFAULT; @@ -942,13 +942,6 @@ pvr_fw_init(struct pvr_device *pvr_dev) =20 fw_dev->defs =3D fw_defs[fw_dev->processor_type]; =20 - /* - * Not all firmware processor types are currently supported. - * Once they are, this check can be removed. - */ - if (!fw_dev->defs) - return -EINVAL; - err =3D fw_dev->defs->init(pvr_dev); if (err) return err; @@ -1455,6 +1448,15 @@ void pvr_fw_object_get_fw_addr_offset(struct pvr_fw_= object *fw_obj, u32 offset, *fw_addr_out =3D pvr_dev->fw_dev.defs->get_fw_addr_with_offset(fw_obj, of= fset); } =20 +u64 +pvr_fw_obj_get_gpu_addr(struct pvr_fw_object *fw_obj) +{ + struct pvr_device *pvr_dev =3D to_pvr_device(gem_from_pvr_gem(fw_obj->gem= )->dev); + struct pvr_fw_device *fw_dev =3D &pvr_dev->fw_dev; + + return fw_dev->fw_heap_info.gpu_addr + fw_obj->fw_addr_offset; +} + /* * pvr_fw_hard_reset() - Re-initialise the FW code and data segments, and = reset all global FW * structures diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagina= tion/pvr_fw.h index 8d3f0ee0aac69373f15ac5919d5b0f27c67cb284..24b9852dbc18d6cec94a4efff2e= b0925fb4b5374 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.h +++ b/drivers/gpu/drm/imagination/pvr_fw.h @@ -392,6 +392,7 @@ enum pvr_fw_processor_type { =20 extern const struct pvr_fw_defs pvr_fw_defs_meta; extern const struct pvr_fw_defs pvr_fw_defs_mips; +extern const struct pvr_fw_defs pvr_fw_defs_riscv; =20 int pvr_fw_validate_init_device_info(struct pvr_device *pvr_dev); int pvr_fw_init(struct pvr_device *pvr_dev); @@ -478,6 +479,15 @@ pvr_fw_object_get_fw_addr(struct pvr_fw_object *fw_obj= , u32 *fw_addr_out) pvr_fw_object_get_fw_addr_offset(fw_obj, 0, fw_addr_out); } =20 +u64 +pvr_fw_obj_get_gpu_addr(struct pvr_fw_object *fw_obj); + +static __always_inline size_t +pvr_fw_obj_get_object_size(struct pvr_fw_object *fw_obj) +{ + return pvr_gem_object_size(fw_obj->gem); +} + /* Util functions defined in pvr_util.c. These are intended for use in pvr= _fw_.c files. */ int pvr_fw_process_elf_command_stream(struct pvr_device *pvr_dev, const u8 *fw= , u8 *fw_code_ptr, diff --git a/drivers/gpu/drm/imagination/pvr_fw_riscv.c b/drivers/gpu/drm/i= magination/pvr_fw_riscv.c new file mode 100644 index 0000000000000000000000000000000000000000..14021e6ef7533f7185dc3c2378f= c1d0c46c2ffed --- /dev/null +++ b/drivers/gpu/drm/imagination/pvr_fw_riscv.c @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* Copyright (c) 2024 Imagination Technologies Ltd. */ + +#include "pvr_device.h" +#include "pvr_fw.h" +#include "pvr_fw_info.h" +#include "pvr_fw_mips.h" +#include "pvr_gem.h" +#include "pvr_rogue_cr_defs.h" +#include "pvr_rogue_riscv.h" +#include "pvr_vm.h" + +#include +#include +#include +#include +#include + +#define ROGUE_FW_HEAP_RISCV_SHIFT 25 /* 32 MB */ +#define ROGUE_FW_HEAP_RISCV_SIZE (1u << ROGUE_FW_HEAP_RISCV_SHIFT) + +static int +pvr_riscv_wrapper_init(struct pvr_device *pvr_dev) +{ + const u64 common_opts =3D + ((u64)(ROGUE_FW_HEAP_RISCV_SIZE >> FWCORE_ADDR_REMAP_CONFIG0_SIZE_ALIGNS= HIFT) + << ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_SIZE_SHIFT) | + ((u64)MMU_CONTEXT_MAPPING_FWPRIV + << FWCORE_ADDR_REMAP_CONFIG0_MMU_CONTEXT_SHIFT); + + u64 code_addr =3D pvr_fw_obj_get_gpu_addr(pvr_dev->fw_dev.mem.code_obj); + u64 data_addr =3D pvr_fw_obj_get_gpu_addr(pvr_dev->fw_dev.mem.data_obj); + + /* This condition allows us to OR the addresses into the register directl= y. */ + static_assert(ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_SHIFT =3D=3D + ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_ALIGNSHIFT); + + WARN_ON(code_addr & ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_CLRMSK); + WARN_ON(data_addr & ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_CLRMSK); + + pvr_cr_write64(pvr_dev, ROGUE_RISCVFW_REGION_REMAP_CR(BOOTLDR_CODE), + code_addr | common_opts | ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_FETC= H_EN_EN); + + pvr_cr_write64(pvr_dev, ROGUE_RISCVFW_REGION_REMAP_CR(BOOTLDR_DATA), + data_addr | common_opts | + ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_LOAD_STORE_EN_EN); + + /* Garten IDLE bit controlled by RISC-V. */ + pvr_cr_write64(pvr_dev, ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG, + ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_META); + + return 0; +} + +struct rogue_riscv_fw_boot_data { + u64 coremem_code_dev_vaddr; + u64 coremem_data_dev_vaddr; + u32 coremem_code_fw_addr; + u32 coremem_data_fw_addr; + u32 coremem_code_size; + u32 coremem_data_size; + u32 flags; + u32 reserved; +}; + +static int +pvr_riscv_fw_process(struct pvr_device *pvr_dev, const u8 *fw, + u8 *fw_code_ptr, u8 *fw_data_ptr, u8 *fw_core_code_ptr, u8 *fw_core_= data_ptr, + u32 core_code_alloc_size) +{ + struct pvr_fw_device *fw_dev =3D &pvr_dev->fw_dev; + struct pvr_fw_mem *fw_mem =3D &fw_dev->mem; + struct rogue_riscv_fw_boot_data *boot_data; + int err; + + err =3D pvr_fw_process_elf_command_stream(pvr_dev, fw, fw_code_ptr, fw_da= ta_ptr, + fw_core_code_ptr, fw_core_data_ptr); + if (err) + goto err_out; + + boot_data =3D (struct rogue_riscv_fw_boot_data *)fw_data_ptr; + + if (fw_mem->core_code_obj) { + boot_data->coremem_code_dev_vaddr =3D pvr_fw_obj_get_gpu_addr(fw_mem->co= re_code_obj); + pvr_fw_object_get_fw_addr(fw_mem->core_code_obj, &boot_data->coremem_cod= e_fw_addr); + boot_data->coremem_code_size =3D pvr_fw_obj_get_object_size(fw_mem->core= _code_obj); + } + + if (fw_mem->core_data_obj) { + boot_data->coremem_data_dev_vaddr =3D pvr_fw_obj_get_gpu_addr(fw_mem->co= re_data_obj); + pvr_fw_object_get_fw_addr(fw_mem->core_data_obj, &boot_data->coremem_dat= a_fw_addr); + boot_data->coremem_data_size =3D pvr_fw_obj_get_object_size(fw_mem->core= _data_obj); + } + + return 0; + +err_out: + return err; +} + +static int +pvr_riscv_init(struct pvr_device *pvr_dev) +{ + pvr_fw_heap_info_init(pvr_dev, ROGUE_FW_HEAP_RISCV_SHIFT, 0); + + return 0; +} + +static u32 +pvr_riscv_get_fw_addr_with_offset(struct pvr_fw_object *fw_obj, u32 offset) +{ + u32 fw_addr =3D fw_obj->fw_addr_offset + offset; + + /* RISC-V cacheability is determined by address. */ + if (fw_obj->gem->flags & PVR_BO_FW_FLAGS_DEVICE_UNCACHED) + fw_addr |=3D ROGUE_RISCVFW_REGION_BASE(SHARED_UNCACHED_DATA); + else + fw_addr |=3D ROGUE_RISCVFW_REGION_BASE(SHARED_CACHED_DATA); + + return fw_addr; +} + +static int +pvr_riscv_vm_map(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj) +{ + struct pvr_gem_object *pvr_obj =3D fw_obj->gem; + + return pvr_vm_map(pvr_dev->kernel_vm_ctx, pvr_obj, 0, fw_obj->fw_mm_node.= start, + pvr_gem_object_size(pvr_obj)); +} + +static void +pvr_riscv_vm_unmap(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_ob= j) +{ + pvr_vm_unmap(pvr_dev->kernel_vm_ctx, fw_obj->fw_mm_node.start, + fw_obj->fw_mm_node.size); +} + +static bool +pvr_riscv_irq_pending(struct pvr_device *pvr_dev) +{ + return pvr_cr_read32(pvr_dev, ROGUE_CR_IRQ_OS0_EVENT_STATUS) & + ROGUE_CR_IRQ_OS0_EVENT_STATUS_SOURCE_EN; +} + +static void +pvr_riscv_irq_clear(struct pvr_device *pvr_dev) +{ + pvr_cr_write32(pvr_dev, ROGUE_CR_IRQ_OS0_EVENT_CLEAR, + ROGUE_CR_IRQ_OS0_EVENT_CLEAR_SOURCE_EN); +} + +const struct pvr_fw_defs pvr_fw_defs_riscv =3D { + .init =3D pvr_riscv_init, + .fw_process =3D pvr_riscv_fw_process, + .vm_map =3D pvr_riscv_vm_map, + .vm_unmap =3D pvr_riscv_vm_unmap, + .get_fw_addr_with_offset =3D pvr_riscv_get_fw_addr_with_offset, + .wrapper_init =3D pvr_riscv_wrapper_init, + .irq_pending =3D pvr_riscv_irq_pending, + .irq_clear =3D pvr_riscv_irq_clear, + .has_fixed_data_addr =3D false, +}; diff --git a/drivers/gpu/drm/imagination/pvr_fw_startstop.c b/drivers/gpu/d= rm/imagination/pvr_fw_startstop.c index 36cec227cfe3cf5b1e293f48b164bb1be1b0ea54..31edf7e49a9c3f3d64022129c8b= b7e2151aa9cdf 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_startstop.c +++ b/drivers/gpu/drm/imagination/pvr_fw_startstop.c @@ -49,6 +49,14 @@ rogue_bif_init(struct pvr_device *pvr_dev) =20 pvr_cr_write64(pvr_dev, BIF_CAT_BASEX(MMU_CONTEXT_MAPPING_FWPRIV), pc_addr); + + if (pvr_dev->fw_dev.processor_type =3D=3D PVR_FW_PROCESSOR_TYPE_RISCV) { + pc_addr =3D (((u64)pc_dma_addr >> ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_ALI= GNSHIFT) + << ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_SHIFT) & + ~ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_CLRMSK; + + pvr_cr_write64(pvr_dev, FWCORE_MEM_CAT_BASEX(MMU_CONTEXT_MAPPING_FWPRIV)= , pc_addr); + } } =20 static int @@ -114,6 +122,9 @@ pvr_fw_start(struct pvr_device *pvr_dev) (void)pvr_cr_read32(pvr_dev, ROGUE_CR_SYS_BUS_SECURE); /* Fence write */ } =20 + if (pvr_dev->fw_dev.processor_type =3D=3D PVR_FW_PROCESSOR_TYPE_RISCV) + pvr_cr_write32(pvr_dev, ROGUE_CR_FWCORE_BOOT, 0); + /* Set Rogue in soft-reset. */ pvr_cr_write64(pvr_dev, ROGUE_CR_SOFT_RESET, soft_reset_mask); if (has_reset2) @@ -167,6 +178,16 @@ pvr_fw_start(struct pvr_device *pvr_dev) /* ... and afterwards. */ udelay(3); =20 + if (pvr_dev->fw_dev.processor_type =3D=3D PVR_FW_PROCESSOR_TYPE_RISCV) { + /* Bring Debug Module out of reset. */ + pvr_cr_write32(pvr_dev, ROGUE_CR_FWCORE_DMI_DMCONTROL, + ROGUE_CR_FWCORE_DMI_DMCONTROL_DMACTIVE_EN); + + /* Boot the FW. */ + pvr_cr_write32(pvr_dev, ROGUE_CR_FWCORE_BOOT, 1); + udelay(3); + } + return 0; =20 err_reset: diff --git a/drivers/gpu/drm/imagination/pvr_rogue_riscv.h b/drivers/gpu/dr= m/imagination/pvr_rogue_riscv.h new file mode 100644 index 0000000000000000000000000000000000000000..9a070e24fa6a8bb44ff1e421ae6= 750cbf724d346 --- /dev/null +++ b/drivers/gpu/drm/imagination/pvr_rogue_riscv.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* Copyright (c) 2024 Imagination Technologies Ltd. */ + +#ifndef PVR_ROGUE_RISCV_H +#define PVR_ROGUE_RISCV_H + +#include "pvr_rogue_cr_defs.h" + +#include +#include +#include + +#define ROGUE_RISCVFW_REGION_SIZE SZ_256M +#define ROGUE_RISCVFW_REGION_SHIFT __ffs(ROGUE_RISCVFW_REGION_SIZE) + +enum rogue_riscvfw_region { + ROGUE_RISCV_REGION__RESERVED_0 =3D 0, + ROGUE_RISCV_REGION__RESERVED_1, + ROGUE_RISCV_REGION_SOCIF, + ROGUE_RISCV_REGION__RESERVED_3, + ROGUE_RISCV_REGION__RESERVED_4, + ROGUE_RISCV_REGION_BOOTLDR_DATA, + ROGUE_RISCV_REGION_SHARED_CACHED_DATA, + ROGUE_RISCV_REGION__RESERVED_7, + ROGUE_RISCV_REGION_COREMEM, + ROGUE_RISCV_REGION__RESERVED_9, + ROGUE_RISCV_REGION__RESERVED_A, + ROGUE_RISCV_REGION__RESERVED_B, + ROGUE_RISCV_REGION_BOOTLDR_CODE, + ROGUE_RISCV_REGION_SHARED_UNCACHED_DATA, + ROGUE_RISCV_REGION__RESERVED_E, + ROGUE_RISCV_REGION__RESERVED_F, + + ROGUE_RISCV_REGION__COUNT, +}; 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Mon, 18 Nov 2024 13:02:43 +0000 From: Matt Coster Date: Mon, 18 Nov 2024 13:02:10 +0000 Subject: [PATCH v2 18/21] drm/imagination: Add platform overrides infrastructure Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241118-sets-bxs-4-64-patch-v1-v2-18-3fd45d9fb0cf@imgtec.com> References: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> In-Reply-To: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7481; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=VAAm9NNUHNCdfIZ/puO043Muv9ZbHxTrP8A3DF7x5Jc=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaRbWz3rkZy6bN+89ed8jKeeMDDbKnpvmu7Cr7c95WO21 P2f2M9V1FHKwiDGwSArpsiyY4XlCrU/aloSN34Vw8xhZQIZwsDFKQATSZnGyDD7QOXn+QEie9um rn3uuepReIfg3XdHn8hwBeWr/KwJ1t7MyPBB7MVv9gUNTsp5sqxfq/afOP08YO8fgQ2hx/ICLdM f9HMCAA== X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Proofpoint-ORIG-GUID: jpPhY4ad37ebojwRrk4BFu2tbd67bVX9 X-Authority-Analysis: v=2.4 cv=E4efprdl c=1 sm=1 tr=0 ts=673b3af4 cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=hzDjp0mCheYA:10 a=IkcTkHD0fZMA:10 a=VlfZXiiP6vEA:10 a=VwQbUJbxAAAA:8 a=r_1tXGB3AAAA:8 a=NJLOqUG6SynMPaEuFzYA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: jpPhY4ad37ebojwRrk4BFu2tbd67bVX9 This infrastructure will be used in cases where a specific GPU integration or implementation requires some special handling in the driver. The first use case is the device cached memory override added in the next patch. The infrastructure is built out in this separate commit to make it clear which specific changes refer to the workaround added there. Signed-off-by: Matt Coster --- Changes in v2: - None - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 18-4ed30e865892@imgtec.com --- drivers/gpu/drm/imagination/pvr_device.c | 26 ++++++++++++++++++++++++ drivers/gpu/drm/imagination/pvr_device.h | 26 ++++++++++++++++++++++++ drivers/gpu/drm/imagination/pvr_drv.c | 34 ++++++++++++++++++++++++----= ---- 3 files changed, 78 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_device.c b/drivers/gpu/drm/ima= gination/pvr_device.c index 52d7641a1a0c62a9c4029092e846472d82950a61..2ce46b9a8ab7609faebeeb4e782= 0751b00047806 100644 --- a/drivers/gpu/drm/imagination/pvr_device.c +++ b/drivers/gpu/drm/imagination/pvr_device.c @@ -621,3 +621,29 @@ pvr_device_has_feature(struct pvr_device *pvr_dev, u32= feature) return false; } } + +/** + * pvr_device_overrides_validate() - Ensure the overrides specified are co= mpatible with a device. + * @pvr_dev: Target PowerVR device. + * @overrides: Device overrides to validate. + * + * Return: + * * %true if every override specified in @overrides is compatible with t= he current device, or + * * %false otherwise; as many incompatibilities as possible will be repo= rted in the kernel log. + */ +bool +pvr_device_overrides_validate(struct pvr_device *pvr_dev, + const struct pvr_device_overrides *overrides) +{ + bool ret =3D true; + + /* + * Where possible, avoid early returns in this function. This allows for = as + * many errors to be reported at once as possible. + * + * Note that this function may be called early during device initializati= on + * so it should not be assumed that @pvr_dev is ready for normal use yet. + */ + + return ret; +} diff --git a/drivers/gpu/drm/imagination/pvr_device.h b/drivers/gpu/drm/ima= gination/pvr_device.h index 76f79b18af354f0e0070530dfc5c8fe0f6a41ce1..ad0a02a37154099542247dfc62f= 411c10f4e41f4 100644 --- a/drivers/gpu/drm/imagination/pvr_device.h +++ b/drivers/gpu/drm/imagination/pvr_device.h @@ -16,6 +16,7 @@ #include =20 #include +#include #include #include #include @@ -56,6 +57,13 @@ struct pvr_fw_version { u16 major, minor; }; =20 +/** + * struct pvr_device_overrides - Hardware-level overrides loaded from + * MODULE_DEVICE_TABLE() or similar. + */ +struct pvr_device_overrides { +}; + /** * struct pvr_device - powervr-specific wrapper for &struct drm_device */ @@ -94,6 +102,13 @@ struct pvr_device { */ struct pvr_device_enhancements enhancements; =20 + /** + * @overrides: Platform-specific overrides required for this device. + * + * Do not access this member directly, instead use PVR_HAS_OVERRIDE(). + */ + struct pvr_device_overrides overrides; + /** @fw_version: Firmware version detected at runtime. */ struct pvr_fw_version fw_version; =20 @@ -436,6 +451,13 @@ struct pvr_file { */ #define PVR_HAS_ENHANCEMENT(pvr_dev, enhancement) ((pvr_dev)->enhancements= .has_ern##enhancement) =20 +/** + * PVR_HAS_OVERRIDE() - Tests whether a physical device requires a given o= verride + * @pvr_dev: [IN] Target PowerVR device. + * @override: [IN] Override name. + */ +#define PVR_HAS_OVERRIDE(pvr_dev, override) unlikely((pvr_dev)->overrides.= override) + #define from_pvr_device(pvr_dev) (&(pvr_dev)->base) =20 #define to_pvr_device(drm_dev) container_of_const(drm_dev, struct pvr_devi= ce, base) @@ -516,6 +538,10 @@ pvr_device_has_uapi_enhancement(struct pvr_device *pvr= _dev, u32 enhancement); bool pvr_device_has_feature(struct pvr_device *pvr_dev, u32 feature); =20 +bool +pvr_device_overrides_validate(struct pvr_device *pvr_dev, + const struct pvr_device_overrides *overrides); + /** * PVR_CR_FIELD_GET() - Extract a single field from a PowerVR control regi= ster * @val: Value of the target register. diff --git a/drivers/gpu/drm/imagination/pvr_drv.c b/drivers/gpu/drm/imagin= ation/pvr_drv.c index 1ab97933e14f20ee3fbf603c23b8dde2d33572c2..b56ee2cda9b54c4388a6eef38b0= ff81acdb05874 100644 --- a/drivers/gpu/drm/imagination/pvr_drv.c +++ b/drivers/gpu/drm/imagination/pvr_drv.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include @@ -1396,11 +1397,13 @@ static struct drm_driver pvr_drm_driver =3D { static int pvr_probe(struct platform_device *plat_dev) { + const struct pvr_device_overrides *overrides; + struct device *dev =3D &plat_dev->dev; struct pvr_device *pvr_dev; struct drm_device *drm_dev; int err; =20 - pvr_dev =3D devm_drm_dev_alloc(&plat_dev->dev, &pvr_drm_driver, + pvr_dev =3D devm_drm_dev_alloc(dev, &pvr_drm_driver, struct pvr_device, base); if (IS_ERR(pvr_dev)) return PTR_ERR(pvr_dev); @@ -1409,6 +1412,15 @@ pvr_probe(struct platform_device *plat_dev) =20 platform_set_drvdata(plat_dev, drm_dev); =20 + overrides =3D of_device_get_match_data(dev); + if (!overrides) + return -EINVAL; + + if (!pvr_device_overrides_validate(pvr_dev, overrides)) + return -EINVAL; + + pvr_dev->overrides =3D *overrides; + err =3D pvr_power_domains_init(pvr_dev); if (err) goto err_context_fini; @@ -1421,11 +1433,11 @@ pvr_probe(struct platform_device *plat_dev) if (err) goto err_power_domains_fini; =20 - devm_pm_runtime_enable(&plat_dev->dev); - pm_runtime_mark_last_busy(&plat_dev->dev); + devm_pm_runtime_enable(dev); + pm_runtime_mark_last_busy(dev); =20 - pm_runtime_set_autosuspend_delay(&plat_dev->dev, 50); - pm_runtime_use_autosuspend(&plat_dev->dev); + pm_runtime_set_autosuspend_delay(dev, 50); + pm_runtime_use_autosuspend(dev); pvr_watchdog_init(pvr_dev); =20 err =3D pvr_device_init(pvr_dev); @@ -1478,18 +1490,24 @@ static void pvr_remove(struct platform_device *plat= _dev) pvr_power_domains_fini(pvr_dev); } =20 +static const struct pvr_device_overrides pvr_device_overrides_default =3D = {}; + +/* + * Always specify &pvr_device_overrides_default instead of %NULL for &stru= ct of_device_id->data so + * that we know of_device_get_match_data() returning %NULL is an error. + */ static const struct of_device_id dt_match[] =3D { - { .compatible =3D "img,img-rogue", .data =3D NULL }, + { .compatible =3D "img,img-rogue", .data =3D &pvr_device_overrides_defaul= t }, =20 /* All supported GPU models */ - { .compatible =3D "img,img-axe-1-16m", .data =3D NULL }, + { .compatible =3D "img,img-axe-1-16m", .data =3D &pvr_device_overrides_de= fault }, =20 /* * This legacy compatible string was introduced early on before the more = specific GPU * identifiers were used. Keep it around here for compatibility, but neve= r use * "img,img-axe" in new devicetrees. */ - { .compatible =3D "img,img-axe", .data =3D NULL }, + { .compatible =3D "img,img-axe", .data =3D &pvr_device_overrides_default = }, {} }; MODULE_DEVICE_TABLE(of, dt_match); --=20 2.47.0 From nobody Sun Nov 24 12:34:29 2024 Received: from mx07-00376f01.pphosted.com (mx07-00376f01.pphosted.com [185.132.180.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BFDE1A9B2F; Mon, 18 Nov 2024 13:29:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.180.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731936592; cv=none; b=rhVDxZb+uVUM4dEyRGS8gS0LEjTU/ahLbioMgQ292i8EtCShP3zemIjIZMnLf88kcD5g7OELBoO09tDXJkV1g43GphZN0ms64CMZvayeZXCw/NUN7tfRx/xzCsaZ4NHET4EraVskdfsngvUMKze4AYgDz67TVYZh+5lBdrhu7K0= ARC-Message-Signature: i=1; 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Mon, 18 Nov 2024 13:02:44 +0000 From: Matt Coster Date: Mon, 18 Nov 2024 13:02:11 +0000 Subject: [PATCH v2 19/21] drm/imagination: Add device_memory_force_cpu_cached override Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241118-sets-bxs-4-64-patch-v1-v2-19-3fd45d9fb0cf@imgtec.com> References: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> In-Reply-To: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7048; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=cB8Xf2NvNov9ZHbtNEv9xGMvJyEWiDLKefTxZkGcESs=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaRbWz3bWq1zq8XKtzDkPMvajiNTV+x+k/q6/tnTvauLd nOcWpb9tKOUhUGMg0FWTJFlxwrLFWp/1LQkbvwqhpnDygQyhIGLUwAmIjyX4X+Bo/m+jTLXuBn+ lMVc+ry1v3nrqXj+yonPv4rVeMXklLUz/DPYsftd8bnoC685du/3udFf1abAJrBv/rbL+ZNjF4m cS2YFAA== X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Proofpoint-ORIG-GUID: SNuPUNGDYeQdHQI_KDsgBwNMblS5mBmg X-Authority-Analysis: v=2.4 cv=E4efprdl c=1 sm=1 tr=0 ts=673b3af5 cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=hzDjp0mCheYA:10 a=IkcTkHD0fZMA:10 a=VlfZXiiP6vEA:10 a=VwQbUJbxAAAA:8 a=r_1tXGB3AAAA:8 a=ZhBkjoDcyXaoxMow2pUA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: SNuPUNGDYeQdHQI_KDsgBwNMblS5mBmg The TI k3-j721s2 platform has a bug relating to cache snooping on the AXI ACE-Lite interface. Disabling cache snooping altogether would also resolve the issue, but is considered more of a performance hit. Given the platform is dma-coherent, forcing all device-accessible memory allocations through the CPU cache is the preferred solution. Implement this workaround so that it can later be enabled for the TI k3-j721s2 platform. Signed-off-by: Matt Coster --- Changes in v2: - None - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 19-4ed30e865892@imgtec.com --- drivers/gpu/drm/imagination/pvr_device.c | 11 ++++++++++- drivers/gpu/drm/imagination/pvr_device.h | 11 +++++++++++ drivers/gpu/drm/imagination/pvr_drv.c | 2 +- drivers/gpu/drm/imagination/pvr_gem.c | 3 +++ drivers/gpu/drm/imagination/pvr_gem.h | 7 +++++-- drivers/gpu/drm/imagination/pvr_mmu.c | 7 ++++++- 6 files changed, 36 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_device.c b/drivers/gpu/drm/ima= gination/pvr_device.c index 2ce46b9a8ab7609faebeeb4e7820751b00047806..ffc177c383c1be16061eff0290c= 347918b0991f7 100644 --- a/drivers/gpu/drm/imagination/pvr_device.c +++ b/drivers/gpu/drm/imagination/pvr_device.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -635,6 +636,7 @@ bool pvr_device_overrides_validate(struct pvr_device *pvr_dev, const struct pvr_device_overrides *overrides) { + struct drm_device *drm_dev =3D from_pvr_device(pvr_dev); bool ret =3D true; =20 /* @@ -643,7 +645,14 @@ pvr_device_overrides_validate(struct pvr_device *pvr_d= ev, * * Note that this function may be called early during device initializati= on * so it should not be assumed that @pvr_dev is ready for normal use yet. - */ + */ + + if (overrides->device_memory_force_cpu_cached && + device_get_dma_attr(drm_dev->dev) !=3D DEV_DMA_COHERENT) { + drm_err(drm_dev, + "Specifying device_memory_force_cpu_cached override without dma-coheren= t attribute is unsupported."); + ret =3D false; + } =20 return ret; } diff --git a/drivers/gpu/drm/imagination/pvr_device.h b/drivers/gpu/drm/ima= gination/pvr_device.h index ad0a02a37154099542247dfc62f411c10f4e41f4..7ae14899db24f4c747e8cf4d61d= 252eb403713f4 100644 --- a/drivers/gpu/drm/imagination/pvr_device.h +++ b/drivers/gpu/drm/imagination/pvr_device.h @@ -60,8 +60,19 @@ struct pvr_fw_version { /** * struct pvr_device_overrides - Hardware-level overrides loaded from * MODULE_DEVICE_TABLE() or similar. + * + * @device_memory_force_cpu_cached: By default, all device memory buffer o= bjects + * are mapped write-combined on the CPU (see %PVR_BO_CPU_CACHED) including= MMU + * page table backing pages which do not use the regular device memory obj= ects. + * This override forces all CPU mappings to be mapped cached instead. Sinc= e this + * could require additional cache maintenance operations to be performed, + * pvr_device_overrides_validate() ensures that the dma-coherent attribute= is + * set when this override is specified. Required on some TI platforms wher= e a + * bug causes device-to-cpu cache snooping to behave incorrectly when + * interacting with cpu-uncached memory. */ struct pvr_device_overrides { + bool device_memory_force_cpu_cached; }; =20 /** diff --git a/drivers/gpu/drm/imagination/pvr_drv.c b/drivers/gpu/drm/imagin= ation/pvr_drv.c index b56ee2cda9b54c4388a6eef38b0ff81acdb05874..e074cfb0d2055b5387dbb142ca9= 72108977f9854 100644 --- a/drivers/gpu/drm/imagination/pvr_drv.c +++ b/drivers/gpu/drm/imagination/pvr_drv.c @@ -1490,7 +1490,7 @@ static void pvr_remove(struct platform_device *plat_d= ev) pvr_power_domains_fini(pvr_dev); } =20 -static const struct pvr_device_overrides pvr_device_overrides_default =3D = {}; +static const struct pvr_device_overrides pvr_device_overrides_default =3D = { 0 }; =20 /* * Always specify &pvr_device_overrides_default instead of %NULL for &stru= ct of_device_id->data so diff --git a/drivers/gpu/drm/imagination/pvr_gem.c b/drivers/gpu/drm/imagin= ation/pvr_gem.c index 6a8c81fe8c1e85c2130a4fe90fce35b6a2be35aa..c67c30518f89af3de2e617a9b65= e5cd78870fa2c 100644 --- a/drivers/gpu/drm/imagination/pvr_gem.c +++ b/drivers/gpu/drm/imagination/pvr_gem.c @@ -345,6 +345,9 @@ pvr_gem_object_create(struct pvr_device *pvr_dev, size_= t size, u64 flags) if (size =3D=3D 0 || !pvr_gem_object_flags_validate(flags)) return ERR_PTR(-EINVAL); =20 + if (PVR_HAS_OVERRIDE(pvr_dev, device_memory_force_cpu_cached)) + flags |=3D PVR_BO_CPU_CACHED; + shmem_obj =3D drm_gem_shmem_create(from_pvr_device(pvr_dev), size); if (IS_ERR(shmem_obj)) return ERR_CAST(shmem_obj); diff --git a/drivers/gpu/drm/imagination/pvr_gem.h b/drivers/gpu/drm/imagin= ation/pvr_gem.h index e0e5ea509a2e88a437b8d241ea13c7bab2220f56..9b3cbcbe48dfbbc8be211a8a409= 699a43452e178 100644 --- a/drivers/gpu/drm/imagination/pvr_gem.h +++ b/drivers/gpu/drm/imagination/pvr_gem.h @@ -44,8 +44,11 @@ struct pvr_file; * Bits not defined anywhere are "undefined". * * CPU mapping options - * :PVR_BO_CPU_CACHED: By default, all GEM objects are mapped write-com= bined on the CPU. Set this - * flag to override this behaviour and map the object cached. + * :PVR_BO_CPU_CACHED: By default, all GEM objects are mapped write-com= bined on the CPU. Set + * this flag to override this behaviour and map the object cached. If + * &struct pvr_device_overrides->device_memory_force_cpu_cached is s= pecified, all allocations + * will be mapped as if this flag was set. This does not require any= additional consideration + * at allocation time since the override is only valid if the dma-co= herent attribute is set. * * Firmware options * :PVR_BO_FW_NO_CLEAR_ON_RESET: By default, all FW objects are cleared= and reinitialised on hard diff --git a/drivers/gpu/drm/imagination/pvr_mmu.c b/drivers/gpu/drm/imagin= ation/pvr_mmu.c index 4fe70610ed94cf707e631f8148af081a94f97327..7c7deb29b735308eaed26900f2f= 54a838382c255 100644 --- a/drivers/gpu/drm/imagination/pvr_mmu.c +++ b/drivers/gpu/drm/imagination/pvr_mmu.c @@ -259,6 +259,7 @@ pvr_mmu_backing_page_init(struct pvr_mmu_backing_page *= page, struct device *dev =3D from_pvr_device(pvr_dev)->dev; =20 struct page *raw_page; + pgprot_t prot; int err; =20 dma_addr_t dma_addr; @@ -268,7 +269,11 @@ pvr_mmu_backing_page_init(struct pvr_mmu_backing_page = *page, if (!raw_page) return -ENOMEM; =20 - host_ptr =3D vmap(&raw_page, 1, VM_MAP, pgprot_writecombine(PAGE_KERNEL)); + prot =3D PAGE_KERNEL; + if (!PVR_HAS_OVERRIDE(pvr_dev, device_memory_force_cpu_cached)) + prot =3D pgprot_writecombine(prot); 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Mon, 18 Nov 2024 13:02:44 +0000 From: Matt Coster Date: Mon, 18 Nov 2024 13:02:12 +0000 Subject: [PATCH v2 20/21] drm/imagination: Add support for TI AM68 GPU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241118-sets-bxs-4-64-patch-v1-v2-20-3fd45d9fb0cf@imgtec.com> References: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> In-Reply-To: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1758; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=fHj5SUJX98oTI0Lq7eQ/770V1/Ls+9Q5P+UrUicuRrc=; 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Signed-off-by: Matt Coster --- Changes in v2: - None - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 20-4ed30e865892@imgtec.com --- drivers/gpu/drm/imagination/pvr_drv.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/imagination/pvr_drv.c b/drivers/gpu/drm/imagin= ation/pvr_drv.c index e074cfb0d2055b5387dbb142ca972108977f9854..044321cab1114864aefa2ca0024= f326ac52d4dd6 100644 --- a/drivers/gpu/drm/imagination/pvr_drv.c +++ b/drivers/gpu/drm/imagination/pvr_drv.c @@ -44,6 +44,7 @@ * This driver supports the following PowerVR/IMG graphics cores from Imag= ination Technologies: * * * AXE-1-16M (found in Texas Instruments AM62) + * * BXS-4-64 MC1 (found in Texas Instruments J721S2/AM68) */ =20 /** @@ -1501,6 +1502,12 @@ static const struct of_device_id dt_match[] =3D { =20 /* All supported GPU models */ { .compatible =3D "img,img-axe-1-16m", .data =3D &pvr_device_overrides_de= fault }, + { .compatible =3D "img,img-bxs-4-64", .data =3D &pvr_device_overrides_def= ault }, + + /* Vendor integrations which require overrides */ + { .compatible =3D "ti,j721s2-gpu", .data =3D &(struct pvr_device_override= s){ + .device_memory_force_cpu_cached =3D true, + } }, =20 /* * This legacy compatible string was introduced early on before the more = specific GPU @@ -1532,3 +1539,4 @@ MODULE_DESCRIPTION(PVR_DRIVER_DESC); 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Mon, 18 Nov 2024 13:02:45 +0000 From: Matt Coster Date: Mon, 18 Nov 2024 13:02:13 +0000 Subject: [PATCH v2 21/21] arm64: dts: ti: k3-j721s2: Add GPU node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241118-sets-bxs-4-64-patch-v1-v2-21-3fd45d9fb0cf@imgtec.com> References: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> In-Reply-To: <20241118-sets-bxs-4-64-patch-v1-v2-0-3fd45d9fb0cf@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1741; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=Ntq50dzXPF1u84iPH0ii+gq7ncmvQWESeBQmF/KzVcI=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaRbWz2btX9to+2i67x3vJyCXPg61z4sFS810jhWrNvyT DL0zvJFHaUsDGIcDLJiiiw7VliuUPujpiVx41cxzBxWJpAhDFycAjCRKgWG/1mFuvzdj1vKHF+n vdV5/WNm6U+RvVe8pOP7uNMjP/s69DMyXGWKcpa/1ubv5zVDa7tOqtizHWu3rFRrlxCIe+mVUXS GAQA= X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Proofpoint-ORIG-GUID: y9THFNVnkJv49gUP9ineJIyRJ3fKU6fj X-Authority-Analysis: v=2.4 cv=E4efprdl c=1 sm=1 tr=0 ts=673b3af6 cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=hzDjp0mCheYA:10 a=IkcTkHD0fZMA:10 a=VlfZXiiP6vEA:10 a=sozttTNsAAAA:8 a=VwQbUJbxAAAA:8 a=r_1tXGB3AAAA:8 a=rLJv8WYccUdZFC7c5UsA:9 a=QEXdDO2ut3YA:10 a=S-JV1fTmrHgA:10 a=j2-svP0xy3wA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: y9THFNVnkJv49gUP9ineJIyRJ3fKU6fj The J721S2 binding is based on the TI downstream binding in 54b0f2a00d92 ("arm64: dts: ti: k3-j721s2-main: add gpu node") from [1] but with updated compatible strings. The clock[2] and power[3] indices were verified from docs, but the source of the interrupt index remains elusive. References for indices: clocks[1], interrupts[2], power[3]. [1]: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel [2]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/clocks.html [3]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/devices.html Signed-off-by: Matt Coster --- Changes in v2: - Use normal reg syntax for 64-bit values - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 21-4ed30e865892@imgtec.com --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 9ed6949b40e9dfafdaf6861944b0b128b053a44f..9adc2c704ba4b38d1a0e7c9ded0= 35fe79630451d 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -2047,4 +2047,16 @@ watchdog8: watchdog@23f0000 { /* reserved for MAIN_R5F1_1 */ status =3D "reserved"; }; + + gpu: gpu@4e20000000 { + compatible =3D "ti,j721s2-gpu", "img,img-bxs-4-64", "img,img-rogue"; + reg =3D <0x4e 0x20000000 0x00 0x80000>; + clocks =3D <&k3_clks 130 1>; + clock-names =3D "core"; + interrupts =3D ; + power-domains =3D <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 373 TI_SCI_PD_EXCLUSIVE>; + power-domain-names =3D "a", "b"; + dma-coherent; + }; }; --=20 2.47.0