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Mon, 18 Nov 2024 06:45:50 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AI6jnb5005711 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 18 Nov 2024 06:45:49 GMT Received: from yijiyang-gv.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 17 Nov 2024 22:45:46 -0800 From: Yijie Yang Date: Mon, 18 Nov 2024 14:44:02 +0800 Subject: [PATCH v2 2/2] arm64: dts: qcom: qcs615-ride: Enable ethernet node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241118-dts_qcs615-v2-2-e62b924a3cbd@quicinc.com> References: <20241118-dts_qcs615-v2-0-e62b924a3cbd@quicinc.com> In-Reply-To: <20241118-dts_qcs615-v2-0-e62b924a3cbd@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran CC: , , , , Yijie Yang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Signed-off-by: Yijie Yang --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 106 +++++++++++++++++++++++++++= ++++ 1 file changed, 106 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts= /qcom/qcs615-ride.dts index ee6cab3924a6d71f29934a8debba3a832882abdd..299be3aa17a0633d808f4b5d32a= ed946f07d5dfd 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -5,6 +5,7 @@ /dts-v1/; =20 #include +#include #include "qcs615.dtsi" / { model =3D "Qualcomm Technologies, Inc. QCS615 Ride"; @@ -196,6 +197,60 @@ vreg_l17a: ldo17 { }; }; =20 +ðernet { + status =3D "okay"; + + pinctrl-0 =3D <ðernet_defaults>; + pinctrl-names =3D "default"; + + phy-handle =3D <&rgmii_phy>; + phy-mode =3D "rgmii"; + max-speed =3D <1000>; + + snps,mtl-rx-config =3D <&mtl_rx_setup>; + snps,mtl-tx-config =3D <&mtl_tx_setup>; + + mdio: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + rgmii_phy: phy@7 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x7>; + + interrupts-extended =3D <&tlmm 121 IRQ_TYPE_EDGE_FALLING>; + device_type =3D "ethernet-phy"; + reset-gpios =3D <&tlmm 104 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <11000>; + reset-deassert-us =3D <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <1>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + snps,route-up; + snps,priority =3D <0x1>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <1>; + snps,tx-sched-wrr; + + queue0 { + snps,weight =3D <0x10>; + snps,dcb-algorithm; + snps,priority =3D <0x0>; + }; + }; +}; + &gcc { clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, @@ -210,6 +265,57 @@ &rpmhcc { clocks =3D <&xo_board_clk>; }; =20 +&tlmm { + ethernet_defaults: ethernet-defaults-state { + mdc-pins { + pins =3D "gpio113"; + function =3D "rgmii"; + bias-pull-up; + }; + + mdio-pins { + pins =3D "gpio114"; + function =3D "rgmii"; + bias-pull-up; + }; + + rgmii-rx-pins { + pins =3D "gpio81", "gpio82", "gpio83", "gpio102", "gpio103", "gpio112"; + function =3D "rgmii"; + bias-disable; + drive-strength =3D <2>; + }; + + rgmii-tx-pins { + pins =3D "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97"; + function =3D "rgmii"; + bias-pull-up; + drive-strength =3D <16>; + }; + + phy-intr-pins { + pins =3D "gpio121"; + function =3D "gpio"; + bias-disable; + drive-strength =3D <8>; + }; + + pps-pins { + pins =3D "gpio91"; + function =3D "rgmii"; + bias-disable; + drive-strength =3D <8>; + }; + + phy-reset-pins { + pins =3D "gpio104"; + function =3D "gpio"; + bias-pull-up; + drive-strength =3D <16>; + }; + }; +}; + &uart0 { status =3D "okay"; }; --=20 2.34.1