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Mon, 18 Nov 2024 01:34:05 -0800 (PST) Received: from lschyi-p920.tpe.corp.google.com ([2401:fa00:1:10:e40d:fa29:75db:2caa]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e9f1e24ce4sm8333500a91.0.2024.11.18.01.34.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2024 01:34:04 -0800 (PST) From: "Sung-Chi, Li" Date: Mon, 18 Nov 2024 17:33:46 +0800 Subject: [PATCH 1/3] platform/chrome: cros_ec_charge_state: add new driver to control charge Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241118-add_charger_state-v1-1-94997079f35a@chromium.org> References: <20241118-add_charger_state-v1-0-94997079f35a@chromium.org> In-Reply-To: <20241118-add_charger_state-v1-0-94997079f35a@chromium.org> To: Benson Leung , Tzung-Bi Shih , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones Cc: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev, devicetree@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1731922439; l=8745; i=lschyi@chromium.org; s=20241113; h=from:subject:message-id; bh=mr78STc32F6NVAyA04kXqtWn3/4JDgdZRTo0Intr1/Y=; b=6ULQoZs/+Ku8qgFPy2ll+3sbBufLGITxaWVjTEpjxIL63t2VI1Y0t3aFvm4E40JZQBd1AtoeV eG9syX/9SIPApVJKwygVB32YxlGxhGybsHb1hEf1sacGf5LwTgWwJGU X-Developer-Key: i=lschyi@chromium.org; a=ed25519; pk=nE3PJlqSK35GdWfB4oVLOwi4njfaUZRhM66HGos9P6o= Implement the new platform driver cros_ec_charge_state to have low finer control over the charge current flow through the charge chip connected on ChromeOS Embedded Controller (EC). The driver reads configured charge chip configurations from the device tree, and register these chip controls as thermal zone devices, so they are controllable from the thermal subsystem. As such, corresponding DTS changes are needed, and here is a sample DTS configuration: ``` &cros_ec { charge-chip-battery { compatible =3D "google,cros-ec-charge-state"; type =3D "charge"; min-milliamp =3D <150>; max-milliamp =3D <5000>; }; }; ``` Signed-off-by: Sung-Chi, Li --- drivers/platform/chrome/Kconfig | 11 ++ drivers/platform/chrome/Makefile | 1 + drivers/platform/chrome/cros_ec_charge_state.c | 215 +++++++++++++++++++++= ++++ 3 files changed, 227 insertions(+) diff --git a/drivers/platform/chrome/Kconfig b/drivers/platform/chrome/Kcon= fig index 7dbeb786352a..34d00d8823cb 100644 --- a/drivers/platform/chrome/Kconfig +++ b/drivers/platform/chrome/Kconfig @@ -297,6 +297,17 @@ config CROS_TYPEC_SWITCH To compile this driver as a module, choose M here: the module will be called cros_typec_switch. =20 +config CROS_CHARGE_STATE + tristate "ChromeOS EC Charger Chip Control" + depends on MFD_CROS_EC_DEV + default MFD_CROS_EC_DEV + help + If you say Y here, you get support for configuring the battery + charging and system input current. + + To compile this driver as a module, choose M here: the module will be + called cros-ec-charge-state. + source "drivers/platform/chrome/wilco_ec/Kconfig" =20 # Kunit test cases diff --git a/drivers/platform/chrome/Makefile b/drivers/platform/chrome/Mak= efile index 2dcc6ccc2302..01c7154ae119 100644 --- a/drivers/platform/chrome/Makefile +++ b/drivers/platform/chrome/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_CROS_EC_SYSFS) +=3D cros_ec_sysfs.o obj-$(CONFIG_CROS_HPS_I2C) +=3D cros_hps_i2c.o obj-$(CONFIG_CROS_USBPD_LOGGER) +=3D cros_usbpd_logger.o obj-$(CONFIG_CROS_USBPD_NOTIFY) +=3D cros_usbpd_notify.o +obj-$(CONFIG_CROS_CHARGE_STATE) +=3D cros_ec_charge_state.o =20 obj-$(CONFIG_WILCO_EC) +=3D wilco_ec/ =20 diff --git a/drivers/platform/chrome/cros_ec_charge_state.c b/drivers/platf= orm/chrome/cros_ec_charge_state.c new file mode 100644 index 000000000000..3fed5b48bc92 --- /dev/null +++ b/drivers/platform/chrome/cros_ec_charge_state.c @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Charge state driver for ChromeOS Embedded Controller + * + * Copyright 2024 Google LLC + * + * This driver exports the low level control over charge chip connected to= EC + * which allows to manipulate the current used to charge the battery, and = also + * manipulate the current input to the whole system. + * This driver also registers that charge chip as a thermal cooling device. + */ + +#include +#include +#include +#include +#include + +#define DRV_NAME "cros-ec-charge-state" +#define CHARGE_TYPE_CHARGE "charge" +#define CHARGE_TYPE_INPUT "input" + +struct cros_ec_charge_state_data { + struct cros_ec_device *ec_dev; + struct device *dev; + enum charge_state_params charge_type; + uint32_t min_milliamp; + uint32_t max_milliamp; +}; + +static int +cros_ec_charge_state_get_current_limit(struct cros_ec_device *ec_dev, + enum charge_state_params charge_type, + uint32_t *limit) +{ + struct ec_params_charge_state param; + struct ec_response_charge_state state; + int ret; + + param.cmd =3D CHARGE_STATE_CMD_GET_PARAM; + param.get_param.param =3D charge_type; + ret =3D cros_ec_cmd(ec_dev, 0, EC_CMD_CHARGE_STATE, ¶m, sizeof(param), + &state, sizeof(state)); + if (ret < 0) + return ret; + + *limit =3D cpu_to_le32(state.get_param.value); + return 0; +} + +static int +cros_ec_charge_state_set_current_limit(struct cros_ec_device *ec_dev, + enum charge_state_params charge_type, + uint32_t limit) +{ + struct ec_params_charge_state param; + int ret; + + param.cmd =3D CHARGE_STATE_CMD_SET_PARAM; + param.set_param.param =3D charge_type; + param.set_param.value =3D cpu_to_le32(limit); + ret =3D cros_ec_cmd(ec_dev, 0, EC_CMD_CHARGE_STATE, ¶m, sizeof(param), + NULL, 0); + return (ret < 0) ? ret : 0; +} + +static int +cros_ec_charge_state_get_max_state(struct thermal_cooling_device *cdev, + unsigned long *state) +{ + struct cros_ec_charge_state_data *data =3D cdev->devdata; + *state =3D data->max_milliamp; + return 0; +} + +static int +cros_ec_charge_state_get_cur_state(struct thermal_cooling_device *cdev, + unsigned long *state) +{ + struct cros_ec_charge_state_data *data =3D cdev->devdata; + uint32_t limit; + int ret; + + ret =3D cros_ec_charge_state_get_current_limit(data->ec_dev, + data->charge_type, &limit); + if (ret) { + dev_err(data->dev, "failed to get current state: %d", ret); + return ret; + } + + *state =3D data->max_milliamp - limit; + return 0; +} + +static int +cros_ec_charge_state_set_cur_state(struct thermal_cooling_device *cdev, + unsigned long state) +{ + struct cros_ec_charge_state_data *data =3D cdev->devdata; + uint32_t limit =3D data->max_milliamp - state; + + if (limit < data->min_milliamp) { + dev_warn( + data->dev, + "failed to set current %u lower than minimum %d; set to minimum", + limit, data->min_milliamp); + limit =3D data->min_milliamp; + } + + state =3D data->max_milliamp - limit; + return cros_ec_charge_state_set_current_limit( + data->ec_dev, data->charge_type, (uint32_t)state); +} + +static const struct thermal_cooling_device_ops + cros_ec_charge_state_cooling_device_ops =3D { + .get_max_state =3D cros_ec_charge_state_get_max_state, + .get_cur_state =3D cros_ec_charge_state_get_cur_state, + .set_cur_state =3D cros_ec_charge_state_set_cur_state, + }; + +static int +cros_ec_charge_state_register_charge_chip(struct device *dev, + struct device_node *node, + struct cros_ec_device *cros_ec) +{ + struct cros_ec_charge_state_data *data; + struct thermal_cooling_device *cdev; + const char *type_val =3D NULL; + int ret; + + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + ret =3D of_property_read_string(node, "type", &type_val); + if (ret) { + dev_err(dev, "failed to get charge type: %d", ret); + return ret; + } + + if (!strcmp(type_val, CHARGE_TYPE_CHARGE)) { + data->charge_type =3D CS_PARAM_CHG_CURRENT; + } else if (!strcmp(type_val, CHARGE_TYPE_INPUT)) { + data->charge_type =3D CS_PARAM_CHG_INPUT_CURRENT; + } else { + dev_err(dev, "unknown charge type: %s", type_val); + return -1; + } + + ret =3D of_property_read_u32(node, "min-milliamp", &data->min_milliamp); + if (ret) { + dev_err(dev, "failed to get min-milliamp data: %d", ret); + return ret; + } + + ret =3D of_property_read_u32(node, "max-milliamp", &data->max_milliamp); + if (ret) { + dev_err(dev, "failed to get max-milliamp data: %d", ret); + return ret; + } + + data->ec_dev =3D cros_ec; + data->dev =3D dev; + + cdev =3D devm_thermal_of_cooling_device_register( + dev, node, node->name, data, + &cros_ec_charge_state_cooling_device_ops); + if (IS_ERR_VALUE(cdev)) { + dev_err(dev, + "failed to register charge chip %s as cooling device: %pe", + node->name, cdev); + return PTR_ERR(cdev); + } + + return 0; +} + +static int cros_ec_charge_state_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; 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Mon, 18 Nov 2024 01:34:07 -0800 (PST) Received: from lschyi-p920.tpe.corp.google.com ([2401:fa00:1:10:e40d:fa29:75db:2caa]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e9f1e24ce4sm8333500a91.0.2024.11.18.01.34.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2024 01:34:07 -0800 (PST) From: "Sung-Chi, Li" Date: Mon, 18 Nov 2024 17:33:47 +0800 Subject: [PATCH 2/3] dt-bindings: chrome: add new binding google,cros-ec-chrage-state Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241118-add_charger_state-v1-2-94997079f35a@chromium.org> References: <20241118-add_charger_state-v1-0-94997079f35a@chromium.org> In-Reply-To: <20241118-add_charger_state-v1-0-94997079f35a@chromium.org> To: Benson Leung , Tzung-Bi Shih , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones Cc: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev, devicetree@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1731922439; l=3165; i=lschyi@chromium.org; s=20241113; h=from:subject:message-id; bh=oQBa+arFToImvygLUmykUiqwBnm+r3Jm6b2xiExq89A=; b=0hwa6pWnShfMj5+1Y8nbF73R9eB01LMvqC0LFFyIM02SGd4i0fyCG/90SbVomYPRHIFQIKrSq W9v3H7Xh9w7DOhL9VIqxgvkH4oSz1CMwyOOjNMwi0Y9hSDb15MCQCZw X-Developer-Key: i=lschyi@chromium.org; a=ed25519; pk=nE3PJlqSK35GdWfB4oVLOwi4njfaUZRhM66HGos9P6o= Add new dt bindings for charge chip control. The charge chip control dt configuration is used by the driver 'cros-ec-charge-state', which is added in the commit "platform/chrome: cros_ec_charge_state: add new driver to control charge". As these charge chip controls are connected under the ChromeOS Embedded Controller (EC), also add the patternProperties to the mfd/google,cros-ec bindings. Signed-off-by: Sung-Chi, Li --- .../bindings/chrome/google,cros-charge-state.yaml | 62 ++++++++++++++++++= ++++ .../devicetree/bindings/mfd/google,cros-ec.yaml | 4 ++ 2 files changed, 66 insertions(+) diff --git a/Documentation/devicetree/bindings/chrome/google,cros-charge-st= ate.yaml b/Documentation/devicetree/bindings/chrome/google,cros-charge-stat= e.yaml new file mode 100644 index 000000000000..40e8f6988769 --- /dev/null +++ b/Documentation/devicetree/bindings/chrome/google,cros-charge-state.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/chrome/google,cros-charge-state.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google Chrome OS EC(Embedded Controller) charge state driver. + +maintainers: + - Sung-Chi, Li + +description: + Chrome OS devices have an Embedded Controller(EC) which has access to + battery charger IC. This node is intended to allow the host to read and + control the charger current. The node for this device should be under a + cros-ec node like google,cros-ec-spi. + +properties: + compatible: + const: google,cros-ec-charge-state + + min-milliamp: + description: min current in milliamp. + $ref: /schemas/types.yaml#/definitions/uint32 + + max-milliamp: + description: max current in milliamp. + $ref: /schemas/types.yaml#/definitions/uint32 + + type: + description: current limit type. + enum: + - charge + - input + +required: + - compatible + - min-milliamp + - man-milliamp + - type + +additionalProperties: false + +examples: + - |+ + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cros_ec: ec@0 { + compatible =3D "google,cros-ec-spi"; + reg =3D <0>; + interrupts =3D <35 0>; + + charge_chip_battery_current: charge-chip-battery { + compatible =3D "google,cros-ec-charge"; + type =3D "charge"; + min-milliamp =3D <150>; + max-milliamp =3D <5000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml b/Do= cumentation/devicetree/bindings/mfd/google,cros-ec.yaml index aac8819bd00b..3db4a48d5176 100644 --- a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml +++ b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml @@ -166,6 +166,10 @@ patternProperties: type: object $ref: /schemas/extcon/extcon-usbc-cros-ec.yaml# =20 + "^charge-chip-*": + type: object + $ref: /schemas/chrome/google,cros-charge-state.yaml# + required: - compatible =20 --=20 2.47.0.338.g60cca15819-goog From nobody Tue Feb 10 09:43:04 2026 Received: from mail-pj1-f45.google.com (mail-pj1-f45.google.com [209.85.216.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78641193060 for ; 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Mon, 18 Nov 2024 01:34:10 -0800 (PST) Received: from lschyi-p920.tpe.corp.google.com ([2401:fa00:1:10:e40d:fa29:75db:2caa]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e9f1e24ce4sm8333500a91.0.2024.11.18.01.34.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2024 01:34:10 -0800 (PST) From: "Sung-Chi, Li" Date: Mon, 18 Nov 2024 17:33:48 +0800 Subject: [PATCH 3/3] mfd: cros_ec: Add charge state control cell Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241118-add_charger_state-v1-3-94997079f35a@chromium.org> References: <20241118-add_charger_state-v1-0-94997079f35a@chromium.org> In-Reply-To: <20241118-add_charger_state-v1-0-94997079f35a@chromium.org> To: Benson Leung , Tzung-Bi Shih , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones Cc: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev, devicetree@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1731922439; l=1453; i=lschyi@chromium.org; s=20241113; h=from:subject:message-id; bh=uAG+q77If4uu42qh15gAWVauifcVeZPLI5R8Z0hp1us=; b=w4UcQxVgEZXHMCl9ZfUByBz4hpcE6oLHmGnYGMAyCfy29Q31/pkyHjtwS/WdcFDy/n4DbMxgt UgelA/S3WGbAYMdCVwNS8dtLFkYxQjx3GC2nRh8IwDJIXPMf5LFCzXB X-Developer-Key: i=lschyi@chromium.org; a=ed25519; pk=nE3PJlqSK35GdWfB4oVLOwi4njfaUZRhM66HGos9P6o= The driver of controlling the charge chip connected on the ChromeOS Embedded Controller (EC) is added in the commit "platform/chrome: cros_ec_charge_state: add new driver to control charge". To register the charge state sub-devices, add mfd cells in the cros-ec-dev mfd driver, and register charge state sub-devices based on whether the EC supports battery feature. Signed-off-by: Sung-Chi, Li --- drivers/mfd/cros_ec_dev.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/mfd/cros_ec_dev.c b/drivers/mfd/cros_ec_dev.c index 9f84a52b48d6..fcb4deac3bf3 100644 --- a/drivers/mfd/cros_ec_dev.c +++ b/drivers/mfd/cros_ec_dev.c @@ -112,6 +112,10 @@ static const struct mfd_cell cros_ec_ucsi_cells[] =3D { { .name =3D "cros_ec_ucsi", }, }; =20 +static const struct mfd_cell cros_ec_charge_state_cells[] =3D { + { .name =3D "cros-ec-charge-state", }, +}; + static const struct cros_feature_to_cells cros_subdevices[] =3D { { .id =3D EC_FEATURE_CEC, @@ -148,6 +152,11 @@ static const struct cros_feature_to_cells cros_subdevi= ces[] =3D { .mfd_cells =3D cros_ec_keyboard_leds_cells, .num_cells =3D ARRAY_SIZE(cros_ec_keyboard_leds_cells), }, + { + .id =3D EC_FEATURE_BATTERY, + .mfd_cells =3D cros_ec_charge_state_cells, + .num_cells =3D ARRAY_SIZE(cros_ec_charge_state_cells), + }, }; =20 static const struct mfd_cell cros_ec_platform_cells[] =3D { --=20 2.47.0.338.g60cca15819-goog