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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3823f72441bsm3028137f8f.101.2024.11.17.10.28.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Nov 2024 10:28:33 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v2 18/22] iio: accel: adxl345: start measure at buffer en/disable Date: Sun, 17 Nov 2024 18:26:47 +0000 Message-Id: <20241117182651.115056-19-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241117182651.115056-1-l.rubusch@gmail.com> References: <20241117182651.115056-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add and initialize the buffer options to use the FIFO and watermark feature of the adxl345 sensor. In this way measure enable will happen in at enabling the buffer. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 105 +++++++++++++++++++++++++++++-- 1 file changed, 101 insertions(+), 4 deletions(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_c= ore.c index a653774db8..b57a123ac9 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -181,6 +181,28 @@ static const struct iio_chan_spec adxl34x_channels[] = =3D { ADXL34x_CHANNEL(2, chan_z, Z), }; =20 +static int adxl345_set_interrupts(struct adxl34x_state *st) +{ + int ret; + unsigned int int_enable =3D st->int_map; + unsigned int int_map; + + /* Any bits set to 0 in the INT map register send their respective + * interrupts to the INT1 pin, whereas bits set to 1 send their respective + * interrupts to the INT2 pin. The intio shall convert this accordingly. + */ + int_map =3D 0xFF & (st->intio ? st->int_map : ~st->int_map); + pr_debug("%s(): Setting INT_MAP 0x%02X\n", __func__, int_map); + + ret =3D regmap_write(st->regmap, ADXL345_REG_INT_MAP, int_map); + if (ret) + return ret; + + pr_debug("%s(): Setting INT_ENABLE 0x%02X\n", __func__, int_enable); + ret =3D regmap_write(st->regmap, ADXL345_REG_INT_ENABLE, int_enable); + return ret; +} + static int adxl345_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) @@ -330,6 +352,41 @@ static const struct attribute_group adxl345_attrs_grou= p =3D { .attrs =3D adxl345_attrs, }; =20 +static int adxl345_set_fifo(struct adxl34x_state *st) +{ + struct adxl34x_platform_data *data =3D &st->data; + u8 fifo_ctl; + int ret; + + /* FIFO should be configured while in standby mode */ + adxl345_set_measure_en(st, false); + + /* The watermark bit is set when the number of samples in FIFO + * equals the value stored in the samples bits (register + * FIFO_CTL). The watermark bit is cleared automatically when + * FIFO is read, and the content returns to a value below the + * value stored in the samples bits. + */ + fifo_ctl =3D 0x00 | + ADXL345_FIFO_CTL_SAMLPES(data->watermark) | + ADXL345_FIFO_CTL_TRIGGER(st->intio) | + ADXL345_FIFO_CTL_MODE(data->fifo_mode); + + pr_debug("%s(): fifo_ctl 0x%02X\n", __func__, fifo_ctl); + + /* The watermark bit is set when the number of samples in FIFO + * equals the value stored in the samples bits (register + * FIFO_CTL). The watermark bit is cleared automatically when + * FIFO is read, and the content returns to a value below the + * value stored in the samples bits. + */ + ret =3D regmap_write(st->regmap, ADXL345_REG_FIFO_CTL, fifo_ctl); + if (ret < 0) + return ret; + + return adxl345_set_measure_en(st, true); +} + /** * adxl345_get_fifo_entries() - Read number of FIFO entries into *fifo_ent= ries. * @st: The initialized state instance of this driver. @@ -416,7 +473,50 @@ static void adxl345_empty_fifo(struct adxl34x_state *s= t) regmap_read(st->regmap, ADXL345_REG_INT_SOURCE, ®val); } =20 +static int adxl345_buffer_postenable(struct iio_dev *indio_dev) +{ + struct adxl34x_state *st =3D iio_priv(indio_dev); + struct adxl34x_platform_data *data =3D &st->data; + int ret; + + ret =3D adxl345_set_interrupts(st); + if (ret) + return -EINVAL; + + /* Default to FIFO mode: STREAM, since it covers the general usage + * and does not bypass the FIFO + */ + data->fifo_mode =3D ADXL_FIFO_STREAM; + adxl345_set_fifo(st); + + return 0; +} + +static int adxl345_buffer_predisable(struct iio_dev *indio_dev) +{ + struct adxl34x_state *st =3D iio_priv(indio_dev); + struct adxl34x_platform_data *data =3D &st->data; + int ret; + + /* Turn off interrupts */ + st->int_map =3D 0x00; + + ret =3D adxl345_set_interrupts(st); + if (ret) { + pr_warn("%s(): Failed to disable INTs\n", __func__); + return -EINVAL; + } + + /* Set FIFO mode: BYPASS, according to the situation */ + data->fifo_mode =3D ADXL_FIFO_BYPASS; + adxl345_set_fifo(st); + + return 0; +} + static const struct iio_buffer_setup_ops adxl345_buffer_ops =3D { + .postenable =3D adxl345_buffer_postenable, + .predisable =3D adxl345_buffer_predisable, }; =20 static int adxl345_get_status(struct adxl34x_state *st, u8 *int_stat) @@ -625,7 +725,7 @@ int adxl345_core_probe(struct device *dev, struct regma= p *regmap, =20 indio_dev->name =3D st->info->name; indio_dev->info =3D &adxl345_info; - indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->modes =3D INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE; indio_dev->channels =3D adxl34x_channels; indio_dev->num_channels =3D ARRAY_SIZE(adxl34x_channels); =20 @@ -685,9 +785,6 @@ int adxl345_core_probe(struct device *dev, struct regma= p *regmap, ret =3D regmap_write(st->regmap, ADXL345_REG_FIFO_CTL, fifo_ctl); if (ret < 0) return ret; - - /* Enable measurement mode */ - adxl345_set_measure_en(st, true); } dev_dbg(dev, "Driver operational\n"); return devm_iio_device_register(dev, indio_dev); --=20 2.39.5