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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3823f72441bsm3028137f8f.101.2024.11.17.10.28.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Nov 2024 10:28:32 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v2 16/22] iio: accel: adxl345: register trigger ops Date: Sun, 17 Nov 2024 18:26:45 +0000 Message-Id: <20241117182651.115056-17-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241117182651.115056-1-l.rubusch@gmail.com> References: <20241117182651.115056-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add trigger options to the sensor driver. Reacting to the sensor events communicated by IRQ, the FIFO handling and the trigger will be core events for further feature implementation. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 34 ++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_c= ore.c index 82bd5c2b78..d58e1994ff 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -15,6 +15,9 @@ =20 #include #include +#include +#include +#include #include #include #include @@ -140,11 +143,13 @@ struct adxl34x_state { const struct adxl345_chip_info *info; struct regmap *regmap; struct adxl34x_platform_data data; /* watermark, fifo_mode, etc */ + struct iio_trigger *trig_dready; =20 __le16 fifo_buf[3 * ADXL34x_FIFO_SIZE] __aligned(IIO_DMA_MINALIGN); u8 int_map; bool fifo_delay; /* delay: delay is needed for SPI */ u8 intio; + bool watermark_en; }; =20 #define ADXL34x_CHANNEL(index, reg, axis) { \ @@ -432,6 +437,35 @@ static int adxl345_get_status(struct adxl34x_state *st= , u8 *int_stat) return 0; } =20 +/* data ready trigger */ + +static int adxl345_trig_dready(struct iio_trigger *trig, bool state) +{ + struct iio_dev *indio_dev =3D iio_trigger_get_drvdata(trig); + struct adxl34x_state *st =3D iio_priv(indio_dev); + + st->int_map =3D 0x00; + if (state) { + /* Setting also ADXL345_INT_DATA_READY results in just a single + * generated interrupt, and no continuously re-generation. NB that the + * INT_DATA_READY as well as the INT_OVERRUN are managed automatically, + * setting their bits here is not needed. + */ + if (st->watermark_en) + st->int_map |=3D ADXL345_INT_WATERMARK; + + pr_debug("%s(): preparing st->int_map 0x%02X\n", + __func__, st->int_map); + } + + return 0; +} + +static const struct iio_trigger_ops adxl34x_trig_dready_ops =3D { + .validate_device =3D &iio_trigger_validate_own_device, + .set_trigger_state =3D adxl345_trig_dready, +}; + /** * irqreturn_t adxl345_trigger_handler() - Interrupt handler used for seve= ral * features of the ADXL345. --=20 2.39.5