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And also move config space, DBI, ELBI, IATU to upper PCIe region and use lower PCIe region entierly for BAR region. Signed-off-by: Krishna chaitanya chundru --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 3d8410683402..a7e3d3e9d034 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2196,10 +2196,10 @@ wifi: wifi@17a10040 { pcie1: pcie@1c08000 { compatible =3D "qcom,pcie-sc7280"; reg =3D <0 0x01c08000 0 0x3000>, - <0 0x40000000 0 0xf1d>, - <0 0x40000f20 0 0xa8>, - <0 0x40001000 0 0x1000>, - <0 0x40100000 0 0x100000>; + <4 0x00000000 0 0xf1d>, + <4 0x00000f20 0 0xa8>, + <4 0x10000000 0 0x1000>, + <4 0x00000000 0 0x10000000>; =20 reg-names =3D "parf", "dbi", "elbi", "atu", "config"; device_type =3D "pci"; @@ -2210,8 +2210,8 @@ pcie1: pcie@1c08000 { #address-cells =3D <3>; #size-cells =3D <2>; =20 - ranges =3D <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, - <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x40000000 0x0 0x100000>, + <0x02000000 0x0 0x40100000 0x0 0x40100000 0x0 0x1ff00000>; =20 interrupts =3D , , --=20 2.34.1