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And also move config space, DBI, ELBI, IATU to upper PCIe region and use lower PCIe region entierly for BAR region. Signed-off-by: Krishna chaitanya chundru --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 3d8410683402..a7e3d3e9d034 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2196,10 +2196,10 @@ wifi: wifi@17a10040 { pcie1: pcie@1c08000 { compatible =3D "qcom,pcie-sc7280"; reg =3D <0 0x01c08000 0 0x3000>, - <0 0x40000000 0 0xf1d>, - <0 0x40000f20 0 0xa8>, - <0 0x40001000 0 0x1000>, - <0 0x40100000 0 0x100000>; + <4 0x00000000 0 0xf1d>, + <4 0x00000f20 0 0xa8>, + <4 0x10000000 0 0x1000>, + <4 0x00000000 0 0x10000000>; =20 reg-names =3D "parf", "dbi", "elbi", "atu", "config"; device_type =3D "pci"; @@ -2210,8 +2210,8 @@ pcie1: pcie@1c08000 { #address-cells =3D <3>; #size-cells =3D <2>; =20 - ranges =3D <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, - <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 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a=ed25519-sha256; t=1731794424; l=8047; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=pvMr8lq/Mb8Gknmhhljff2OQb8275sOKyFDvAfAIH8U=; b=QArXG/eRKX+OiOO+z6FguI14vwRaO1c1xJ1PjVopxzPKW/wpMh482CdaDlxThDJ9zekkY4f6z DAF2fYE/03VB70UgS0cGAfJ/FGN2bWlmZGvkGWWZBrHUpgijAtfaNtk X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: R6O9Mfq1Mrd8gC6Jnlm8qBljqEpUhksp X-Proofpoint-ORIG-GUID: R6O9Mfq1Mrd8gC6Jnlm8qBljqEpUhksp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 impostorscore=0 adultscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 phishscore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411160192 The current implementation requires iATU for every configuration space access which increases latency & cpu utilization. Configuring iATU in config shift mode enables ECAM feature to access the config space, which avoids iATU configuration for every config access. Add "ctrl2" into struct dw_pcie_ob_atu_cfg to enable config shift mode. As DBI comes under config space, this avoids remapping of DBI space separately. Instead, it uses the mapped config space address returned from ECAM initialization. Change the order of dw_pcie_get_resources() execution to acheive this. Introduce new ecam_init() function op for the clients to configure after ecam window creation has been done. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 114 ++++++++++++++++++= ---- drivers/pci/controller/dwc/pcie-designware.c | 2 +- drivers/pci/controller/dwc/pcie-designware.h | 6 ++ 3 files changed, 102 insertions(+), 20 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 3e41865c7290..e98cc841a2a9 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -418,6 +418,62 @@ static void dw_pcie_host_request_msg_tlp_res(struct dw= _pcie_rp *pp) } } =20 +static int dw_pcie_config_ecam_iatu(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct dw_pcie_ob_atu_cfg atu =3D {0}; + struct resource_entry *bus; + int ret, bus_range_max; + + bus =3D resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS); + + /* + * Bus 1 config space needs type 0 atu configuration + * Remaining buses need type 1 atu configuration + */ + atu.index =3D 0; + atu.type =3D PCIE_ATU_TYPE_CFG0; + atu.cpu_addr =3D pp->cfg0_base + SZ_1M; + atu.size =3D SZ_1M; + atu.ctrl2 =3D PCIE_ATU_CFG_SHIFT_MODE_ENABLE; + ret =3D dw_pcie_prog_outbound_atu(pci, &atu); + if (ret) + return ret; + + bus_range_max =3D bus->res->end - bus->res->start + 1; + + /* Configure for bus 2 - bus_range_max in type 1 */ + atu.index =3D 1; + atu.type =3D PCIE_ATU_TYPE_CFG1; + atu.cpu_addr =3D pp->cfg0_base + SZ_2M; + atu.size =3D (SZ_1M * (bus_range_max - 2)); + atu.ctrl2 =3D PCIE_ATU_CFG_SHIFT_MODE_ENABLE; + return dw_pcie_prog_outbound_atu(pci, &atu); +} + +static int dw_pcie_create_ecam_window(struct dw_pcie_rp *pp, struct resour= ce *res) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct device *dev =3D pci->dev; + struct resource_entry *bus; + + bus =3D resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS); + if (!bus) + return -ENODEV; + + pp->cfg =3D pci_ecam_create(dev, res, bus->res, &pci_generic_ecam_ops); + if (IS_ERR(pp->cfg)) + return PTR_ERR(pp->cfg); + + pci->dbi_base =3D pp->cfg->win; + pci->dbi_phys_addr =3D res->start; + + if (pp->ops->ecam_init) + pp->ops->ecam_init(pci, pp->cfg); + + return 0; +} + int dw_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); @@ -431,19 +487,8 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) =20 raw_spin_lock_init(&pp->lock); =20 - ret =3D dw_pcie_get_resources(pci); - if (ret) - return ret; - res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); - if (res) { - pp->cfg0_size =3D resource_size(res); - pp->cfg0_base =3D res->start; - - pp->va_cfg0_base =3D devm_pci_remap_cfg_resource(dev, res); - if (IS_ERR(pp->va_cfg0_base)) - return PTR_ERR(pp->va_cfg0_base); - } else { + if (!res) { dev_err(dev, "Missing *config* reg space\n"); return -ENODEV; } @@ -454,6 +499,30 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) =20 pp->bridge =3D bridge; =20 + pp->cfg0_size =3D resource_size(res); + pp->cfg0_base =3D res->start; + + if (!pp->enable_ecam) { + pp->va_cfg0_base =3D devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(pp->va_cfg0_base)) + return PTR_ERR(pp->va_cfg0_base); + + /* Set default bus ops */ + bridge->ops =3D &dw_pcie_ops; + bridge->child_ops =3D &dw_child_pcie_ops; + bridge->sysdata =3D pp; + } else { + ret =3D dw_pcie_create_ecam_window(pp, res); + if (ret) + return ret; + bridge->ops =3D (struct pci_ops *)&pci_generic_ecam_ops.pci_ops; + pp->bridge->sysdata =3D pp->cfg; + } + + ret =3D dw_pcie_get_resources(pci); + if (ret) + goto err_free_ecam; + /* Get the I/O range from DT */ win =3D resource_list_first_type(&bridge->windows, IORESOURCE_IO); if (win) { @@ -462,14 +531,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) pp->io_base =3D pci_pio_to_address(win->res->start); } =20 - /* Set default bus ops */ - bridge->ops =3D &dw_pcie_ops; - bridge->child_ops =3D &dw_child_pcie_ops; - if (pp->ops->init) { ret =3D pp->ops->init(pp); if (ret) - return ret; + goto err_free_ecam; } =20 if (pci_msi_enabled()) { @@ -504,6 +569,12 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) =20 dw_pcie_iatu_detect(pci); =20 + if (pp->enable_ecam) { + ret =3D dw_pcie_config_ecam_iatu(pp); + if (ret) + goto err_free_msi; + } + /* * Allocate the resource for MSG TLP before programming the iATU * outbound window in dw_pcie_setup_rc(). Since the allocation depends @@ -533,8 +604,6 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) /* Ignore errors, the link may come up later */ dw_pcie_wait_for_link(pci); =20 - bridge->sysdata =3D pp; - ret =3D pci_host_probe(bridge); if (ret) goto err_stop_link; @@ -558,6 +627,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) if (pp->ops->deinit) pp->ops->deinit(pp); =20 +err_free_ecam: + if (pp->cfg) + pci_ecam_free(pp->cfg); + return ret; } EXPORT_SYMBOL_GPL(dw_pcie_host_init); @@ -578,6 +651,9 @@ void dw_pcie_host_deinit(struct dw_pcie_rp *pp) =20 if (pp->ops->deinit) pp->ops->deinit(pp); + + if (pp->cfg) + pci_ecam_free(pp->cfg); } EXPORT_SYMBOL_GPL(dw_pcie_host_deinit); =20 diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 6d6cbc8b5b2c..63d36676f858 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -509,7 +509,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, val =3D dw_pcie_enable_ecrc(val); dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val); =20 - val =3D PCIE_ATU_ENABLE; + val =3D PCIE_ATU_ENABLE | atu->ctrl2; if (atu->type =3D=3D PCIE_ATU_TYPE_MSG) { /* The data-less messages only for now */ val |=3D PCIE_ATU_INHIBIT_PAYLOAD | atu->code; diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 347ab74ac35a..33afa91b402c 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -20,6 +20,7 @@ #include #include #include +#include #include =20 #include @@ -171,6 +172,7 @@ #define PCIE_ATU_REGION_CTRL2 0x004 #define PCIE_ATU_ENABLE BIT(31) #define PCIE_ATU_BAR_MODE_ENABLE BIT(30) +#define PCIE_ATU_CFG_SHIFT_MODE_ENABLE BIT(28) #define PCIE_ATU_INHIBIT_PAYLOAD BIT(22) #define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19) #define PCIE_ATU_LOWER_BASE 0x008 @@ -342,6 +344,7 @@ struct dw_pcie_ob_atu_cfg { u8 func_no; u8 code; u8 routing; + u32 ctrl2; u64 cpu_addr; u64 pci_addr; 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Sat, 16 Nov 2024 22:00:50 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sat, 16 Nov 2024 14:00:43 -0800 From: Krishna chaitanya chundru Date: Sun, 17 Nov 2024 03:30:20 +0530 Subject: [PATCH 3/3] PCI: qcom: Enable ECAM feature based on config size Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241117-ecam-v1-3-6059faf38d07@quicinc.com> References: <20241117-ecam-v1-0-6059faf38d07@quicinc.com> In-Reply-To: <20241117-ecam-v1-0-6059faf38d07@quicinc.com> To: , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jingoo Han , "Manivannan Sadhasivam" , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas CC: , , , , , , , , , , , Krishna chaitanya chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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The ELBI registers falls after the DBI space, so use the cfg win returned from the ecam init to map these regions instead of doing the ioremap again. ELBI starts at offset 0xf20 from dbi. On bus 0, we have only the root complex. Any access other than that should not go out of the link and should return all F's. Since the IATU is configured for bus 1 onwards, block the transactions for bus 0:0:1 to 0:31:7 (i.e., from dbi_base + 4KB to dbi_base + 1MB) from going outside the link through ecam blocker through parf registers. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 104 +++++++++++++++++++++++++++++= ++-- 1 file changed, 100 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index ef44a82be058..266de2aa3a71 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -61,6 +61,17 @@ #define PARF_DBI_BASE_ADDR_V2_HI 0x354 #define PARF_SLV_ADDR_SPACE_SIZE_V2 0x358 #define PARF_SLV_ADDR_SPACE_SIZE_V2_HI 0x35c +#define PARF_BLOCK_SLV_AXI_WR_BASE 0x360 +#define PARF_BLOCK_SLV_AXI_WR_BASE_HI 0x364 +#define PARF_BLOCK_SLV_AXI_WR_LIMIT 0x368 +#define PARF_BLOCK_SLV_AXI_WR_LIMIT_HI 0x36c +#define PARF_BLOCK_SLV_AXI_RD_BASE 0x370 +#define PARF_BLOCK_SLV_AXI_RD_BASE_HI 0x374 +#define PARF_BLOCK_SLV_AXI_RD_LIMIT 0x378 +#define PARF_BLOCK_SLV_AXI_RD_LIMIT_HI 0x37c +#define PARF_ECAM_BASE 0x380 +#define PARF_ECAM_BASE_HI 0x384 + #define PARF_NO_SNOOP_OVERIDE 0x3d4 #define PARF_ATU_BASE_ADDR 0x634 #define PARF_ATU_BASE_ADDR_HI 0x638 @@ -68,6 +79,8 @@ #define PARF_BDF_TO_SID_TABLE_N 0x2000 #define PARF_BDF_TO_SID_CFG 0x2c00 =20 +#define ELBI_OFFSET 0xf20 + /* ELBI registers */ #define ELBI_SYS_CTRL 0x04 =20 @@ -84,6 +97,7 @@ =20 /* PARF_SYS_CTRL register fields */ #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29) +#define PCIE_ECAM_BLOCKER_EN BIT(26) #define MST_WAKEUP_EN BIT(13) #define SLV_WAKEUP_EN BIT(12) #define MSTR_ACLK_CGC_DIS BIT(10) @@ -293,15 +307,68 @@ static void qcom_ep_reset_deassert(struct qcom_pcie *= pcie) usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); } =20 +static int qcom_pci_config_ecam_blocker(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct qcom_pcie *pcie =3D to_qcom_pcie(pci); + u64 addr, addr_end; + u32 val; + + /* Set the ECAM base */ + writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE); + writel(upper_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE_HI); + + /* + * On bus 0, we have only the root complex. Any access other than that + * should not go out of the link and should return all F's. Since the + * IATU is configured for bus 1 onwards, block the transactions for + * bus 0:0:1 to 0:31:7 (i.e from dbi_base + 4kb to dbi_base + 1MB) from + * going outside the link. + */ + addr =3D pci->dbi_phys_addr + SZ_4K; + writel(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE); + writel(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE_HI); + + writel(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE); + writel(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE_HI); + + addr_end =3D pci->dbi_phys_addr + SZ_1M - 1; + + writel(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT); + writel(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT_= HI); + + writel(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT); + writel(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT_= HI); + + val =3D readl(pcie->parf + PARF_SYS_CTRL); + val |=3D PCIE_ECAM_BLOCKER_EN; + writel(val, pcie->parf + PARF_SYS_CTRL); + return 0; +} + +static int qcom_pcie_ecam_init(struct dw_pcie *pci, struct pci_config_wind= ow *cfg) +{ + struct qcom_pcie *pcie =3D to_qcom_pcie(pci); + + pcie->elbi =3D pci->dbi_base + ELBI_OFFSET; + return 0; +} + static int qcom_pcie_start_link(struct dw_pcie *pci) { struct qcom_pcie *pcie =3D to_qcom_pcie(pci); + int ret; =20 if (pcie_link_speed[pci->max_link_speed] =3D=3D PCIE_SPEED_16_0GT) { qcom_pcie_common_set_16gt_equalization(pci); qcom_pcie_common_set_16gt_lane_margining(pci); } =20 + if (pci->pp.enable_ecam) { + ret =3D qcom_pci_config_ecam_blocker(&pci->pp); + if (ret) + return ret; + } /* Enable Link Training state machine */ if (pcie->cfg->ops->ltssm_enable) pcie->cfg->ops->ltssm_enable(pcie); @@ -1297,6 +1364,7 @@ static const struct dw_pcie_host_ops qcom_pcie_dw_ops= =3D { .init =3D qcom_pcie_host_init, .deinit =3D qcom_pcie_host_deinit, .post_init =3D qcom_pcie_host_post_init, + .ecam_init =3D qcom_pcie_ecam_init, }; =20 /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */ @@ -1566,6 +1634,31 @@ static irqreturn_t qcom_pcie_global_irq_thread(int i= rq, void *data) return IRQ_HANDLED; } =20 +static bool qcom_pcie_check_ecam_support(struct device *dev) +{ + struct platform_device *pdev =3D to_platform_device(dev); + struct resource bus_range, *config_res; + u64 bus_config_space_count; + int ret; + + /* If bus range is not present, keep the bus range as maximum value */ + ret =3D of_pci_parse_bus_range(dev->of_node, &bus_range); + if (ret) { + bus_range.start =3D 0x0; + bus_range.end =3D 0xff; + } + + config_res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "config= "); + if (!config_res) + return false; + + bus_config_space_count =3D resource_size(config_res) >> PCIE_ECAM_BUS_SHI= FT; + if (resource_size(&bus_range) > bus_config_space_count) + return false; + + return true; +} + static int qcom_pcie_probe(struct platform_device *pdev) { const struct qcom_pcie_cfg *pcie_cfg; @@ -1600,6 +1693,7 @@ static int qcom_pcie_probe(struct platform_device *pd= ev) =20 pci->dev =3D dev; pci->ops =3D &dw_pcie_ops; + pci->pp.enable_ecam =3D qcom_pcie_check_ecam_support(dev); pp =3D &pci->pp; =20 pcie->pci =3D pci; @@ -1618,10 +1712,12 @@ static int qcom_pcie_probe(struct platform_device *= pdev) goto err_pm_runtime_put; } =20 - pcie->elbi =3D devm_platform_ioremap_resource_byname(pdev, "elbi"); - if (IS_ERR(pcie->elbi)) { - ret =3D PTR_ERR(pcie->elbi); - goto err_pm_runtime_put; + if (!pp->enable_ecam) { + pcie->elbi =3D devm_platform_ioremap_resource_byname(pdev, "elbi"); + if (IS_ERR(pcie->elbi)) { + ret =3D PTR_ERR(pcie->elbi); + goto err_pm_runtime_put; + } } =20 /* MHI region is optional */ --=20 2.34.1