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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da28ba80sm92424375e9.29.2024.11.16.05.10.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Nov 2024 05:10:29 -0800 (PST) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org Cc: marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 02/11] ARM: dts: socfpga: add Enclustra base-board dtsi Date: Sat, 16 Nov 2024 13:10:16 +0000 Message-Id: <20241116131025.114542-3-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241116131025.114542-1-l.rubusch@gmail.com> References: <20241116131025.114542-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add generic Enclustra base-board support for the Mercury+ PE1, the Mercury+ PE3 and the Mercury+ ST1 board. The carrier boards can be freely combined with the SoMs Mercury+ AA1, Mercury SA1 and Mercury+ SA2. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- .../socfpga_enclustra_mercury_pe1.dtsi | 33 +++++++++++ .../socfpga_enclustra_mercury_pe3.dtsi | 55 +++++++++++++++++++ .../socfpga_enclustra_mercury_st1.dtsi | 15 +++++ 3 files changed, 103 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercu= ry_pe1.dtsi create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercu= ry_pe3.dtsi create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercu= ry_st1.dtsi diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.= dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi new file mode 100644 index 000000000..abc4bfb7f --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&i2c_encl { + status =3D "okay"; + + eeprom@57 { + status =3D "okay"; + compatible =3D "microchip,24c128"; + reg =3D <0x57>; + pagesize =3D <64>; + label =3D "user eeprom"; + address-width =3D <16>; + }; + + lm96080: temperature-sensor@2f { + status =3D "okay"; + compatible =3D "national,lm80"; + reg =3D <0x2f>; + }; + + si5338: clock-controller@70 { + compatible =3D "silabs,si5338"; + reg =3D <0x70>; + }; + +}; + +&i2c_encl_fpga { + status =3D "okay"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.= dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi new file mode 100644 index 000000000..bc57b0680 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&i2c_encl { + i2c-mux@74 { + status =3D "okay"; + compatible =3D "nxp,pca9547"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x74>; + + i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + + eeprom@56 { + status =3D "okay"; + compatible =3D "microchip,24c128"; + reg =3D <0x56>; + pagesize =3D <64>; + label =3D "user eeprom"; + address-width =3D <16>; + }; + + lm96080: temperature-sensor@2f { + status =3D "okay"; + compatible =3D "national,lm80"; + reg =3D <0x2f>; + }; + + pcal6416: gpio@20 { + status =3D "okay"; + compatible =3D "nxp,pcal6416"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + }; + }; + }; +}; + +&i2c_encl_fpga { + status =3D "okay"; + + i2c-mux@75 { + status =3D "okay"; + compatible =3D "nxp,pca9547"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x75>; + }; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.= dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi new file mode 100644 index 000000000..4c00475f4 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&i2c_encl { + si5338: clock-controller@70 { + compatible =3D "silabs,si5338"; + reg =3D <0x70>; + }; +}; + +&i2c_encl_fpga { + status =3D "okay"; +}; --=20 2.39.2