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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da28ba80sm92424375e9.29.2024.11.16.05.10.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Nov 2024 05:10:27 -0800 (PST) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org Cc: marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 01/11] ARM: dts: socfpga: add Enclustra boot-mode dtsi Date: Sat, 16 Nov 2024 13:10:15 +0000 Message-Id: <20241116131025.114542-2-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241116131025.114542-1-l.rubusch@gmail.com> References: <20241116131025.114542-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add generic boot-mode support to Enclustra Arria10 and Cyclone5 boards. Some Enclustra carrier boards need hardware adjustments specific to the selected boot-mode. Enclustra's Arria10 SoMs allow for booting from different media. By muxing certain IO pins, the media can be selected. This muxing can be done by gpios at runtime e.g. when flashing QSPI from off the bootloader. But also to have statically certain boot media available, certain adjustments to the DT are needed: - SD: QSPI must be disabled - eMMC: QSPI must be disabled, bus width can be doubled to 8 byte - QSPI: any mmc is disabled, QSPI then defaults to be enabled The boot media must be accessible to the bootloader, e.g. to load a bitstream file, but also to the system to mount the rootfs and to use the specific performance. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- .../socfpga_enclustra_mercury_bootmode_emmc.dtsi | 12 ++++++++++++ .../socfpga_enclustra_mercury_bootmode_qspi.dtsi | 8 ++++++++ .../socfpga_enclustra_mercury_bootmode_sdmmc.dtsi | 8 ++++++++ 3 files changed, 28 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercu= ry_bootmode_emmc.dtsi create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercu= ry_bootmode_qspi.dtsi create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercu= ry_bootmode_sdmmc.dtsi diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_boot= mode_emmc.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_= bootmode_emmc.dtsi new file mode 100644 index 000000000..d79cb64da --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_em= mc.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&qspi { + status =3D "disabled"; +}; + +&mmc { + bus-width =3D <8>; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_boot= mode_qspi.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_= bootmode_qspi.dtsi new file mode 100644 index 000000000..5ba21dd8f --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_qs= pi.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&mmc { + status =3D "disabled"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_boot= mode_sdmmc.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury= _bootmode_sdmmc.dtsi new file mode 100644 index 000000000..2b102e0b6 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_sd= mmc.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&qspi { + status =3D "disabled"; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da28ba80sm92424375e9.29.2024.11.16.05.10.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Nov 2024 05:10:29 -0800 (PST) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org Cc: marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 02/11] ARM: dts: socfpga: add Enclustra base-board dtsi Date: Sat, 16 Nov 2024 13:10:16 +0000 Message-Id: <20241116131025.114542-3-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241116131025.114542-1-l.rubusch@gmail.com> References: <20241116131025.114542-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add generic Enclustra base-board support for the Mercury+ PE1, the Mercury+ PE3 and the Mercury+ ST1 board. The carrier boards can be freely combined with the SoMs Mercury+ AA1, Mercury SA1 and Mercury+ SA2. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- .../socfpga_enclustra_mercury_pe1.dtsi | 33 +++++++++++ .../socfpga_enclustra_mercury_pe3.dtsi | 55 +++++++++++++++++++ .../socfpga_enclustra_mercury_st1.dtsi | 15 +++++ 3 files changed, 103 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercu= ry_pe1.dtsi create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercu= ry_pe3.dtsi create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercu= ry_st1.dtsi diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.= dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi new file mode 100644 index 000000000..abc4bfb7f --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&i2c_encl { + status =3D "okay"; + + eeprom@57 { + status =3D "okay"; + compatible =3D "microchip,24c128"; + reg =3D <0x57>; + pagesize =3D <64>; + label =3D "user eeprom"; + address-width =3D <16>; + }; + + lm96080: temperature-sensor@2f { + status =3D "okay"; + compatible =3D "national,lm80"; + reg =3D <0x2f>; + }; + + si5338: clock-controller@70 { + compatible =3D "silabs,si5338"; + reg =3D <0x70>; + }; + +}; + +&i2c_encl_fpga { + status =3D "okay"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.= dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi new file mode 100644 index 000000000..bc57b0680 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&i2c_encl { + i2c-mux@74 { + status =3D "okay"; + compatible =3D "nxp,pca9547"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x74>; + + i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + + eeprom@56 { + status =3D "okay"; + compatible =3D "microchip,24c128"; + reg =3D <0x56>; + pagesize =3D <64>; + label =3D "user eeprom"; + address-width =3D <16>; + }; + + lm96080: temperature-sensor@2f { + status =3D "okay"; + compatible =3D "national,lm80"; + reg =3D <0x2f>; + }; + + pcal6416: gpio@20 { + status =3D "okay"; + compatible =3D "nxp,pcal6416"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + }; + }; + }; +}; + +&i2c_encl_fpga { + status =3D "okay"; + + i2c-mux@75 { + status =3D "okay"; + compatible =3D "nxp,pca9547"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x75>; + }; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.= dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi new file mode 100644 index 000000000..4c00475f4 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +&i2c_encl { + si5338: clock-controller@70 { + compatible =3D "silabs,si5338"; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da28ba80sm92424375e9.29.2024.11.16.05.10.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Nov 2024 05:10:30 -0800 (PST) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org Cc: marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 03/11] ARM: dts: socfpga: add Enclustra Mercury SA1 Date: Sat, 16 Nov 2024 13:10:17 +0000 Message-Id: <20241116131025.114542-4-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241116131025.114542-1-l.rubusch@gmail.com> References: <20241116131025.114542-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce support for Enclustra's Mercury SA1 SoM based on Intel Cyclone5 technology as a .dtsi file. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- .../socfpga/socfpga_cyclone5_mercury_sa1.dtsi | 143 ++++++++++++++++++ 1 file changed, 143 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1.dtsi diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1.d= tsi b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1.dtsi new file mode 100644 index 000000000..2041088b7 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1.dtsi @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model =3D "Enclustra Mercury SA1"; + compatible =3D "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + aliases { + ethernet0 =3D &gmac1; + }; + + /* Adjusted the i2c labels to use generic base-board dtsi files for + * Enclustra Arria10 and Cyclone5 SoMs. + * + * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in + * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi + * fragments. Thus define generic labels here to match the correct i2c + * bus in a generic base-board .dtsi file. + */ + soc { + i2c_encl: i2c@ffc04000 { + }; + i2c_encl_fpga: i2c@ffc05000 { + }; + }; + + memory { + name =3D "memory"; + device_type =3D "memory"; + reg =3D <0x0 0x40000000>; /* 1GB */ + }; +}; + +&osc1 { + clock-frequency =3D <50000000>; +}; + +&i2c_encl { + i2c-sda-hold-time-ns =3D <300>; + clock-frequency =3D <100000>; + status =3D "okay"; + + isl12020: rtc@6f { + compatible =3D "isil,isl12022"; + reg =3D <0x6f>; + }; +}; + +&i2c_encl_fpga { + i2c-sda-hold-time-ns =3D <300>; + status =3D "disabled"; +}; + +&uart0 { + clock-frequency =3D <100000000>; +}; + +&mmc0 { + status =3D "okay"; + /delete-property/ cap-mmc-highspeed; + /delete-property/ cap-sd-highspeed; +}; + +&qspi { + status =3D "okay"; + + flash0: flash@0 { + u-boot,dm-pre-reloc; + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "spansion,s25fl512s", "jedec,spi-nor"; + reg =3D <0>; + + spi-rx-bus-width =3D <4>; + spi-tx-bus-width =3D <4>; + spi-max-frequency =3D <10000000>; + + cdns,read-delay =3D <4>; + cdns,tshsl-ns =3D <50>; + cdns,tsd2d-ns =3D <50>; + cdns,tchsh-ns =3D <4>; + cdns,tslch-ns =3D <4>; + + partition@raw { + label =3D "Flash Raw"; + reg =3D <0x0 0x4000000>; + }; + }; +}; + +&gpio0 { + status =3D "okay"; +}; + +&gpio1 { + status =3D "okay"; +}; + +&gmac1 { + status =3D "okay"; + /delete-property/ mac-address; + phy-mode =3D "rgmii"; + phy-handle =3D <&phy3>; + + mdio0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + + phy3: ethernet-phy@3 { + reg =3D <3>; + + /* Add 2ns RX clock delay (1.2ns + 0.78ns)*/ + rxc-skew-ps =3D <1680>; + rxd0-skew-ps =3D <420>; + rxd1-skew-ps =3D <420>; + rxd2-skew-ps =3D <420>; + rxd3-skew-ps =3D <420>; + rxdv-skew-ps =3D <420>; + + /* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/ + txc-skew-ps =3D <1860>; + txd0-skew-ps =3D <0>; + txd1-skew-ps =3D <0>; + txd2-skew-ps =3D <0>; + txd3-skew-ps =3D <0>; + txen-skew-ps =3D <0>; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da28ba80sm92424375e9.29.2024.11.16.05.10.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Nov 2024 05:10:31 -0800 (PST) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org Cc: marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v5 04/11] dt-bindings: altera: add Enclustra Mercury SA1 Date: Sat, 16 Nov 2024 13:10:18 +0000 Message-Id: <20241116131025.114542-5-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241116131025.114542-1-l.rubusch@gmail.com> References: <20241116131025.114542-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update the DT binding for the Enclustra Mercury+ SA1 SoM Signed-off-by: Lothar Rubusch Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/altera.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentat= ion/devicetree/bindings/arm/altera.yaml index 8c7575455..87a22d2a4 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -51,6 +51,16 @@ properties: - const: altr,socfpga-cyclone5 - const: altr,socfpga =20 + - description: Mercury SA1 boards + items: + - enum: + - enclustra,mercury-sa1-pe1 + - enclustra,mercury-sa1-pe3 + - enclustra,mercury-sa1-st1 + - const: enclustra,mercury-sa1 + - const: altr,socfpga-cyclone5 + - const: altr,socfpga + - description: Stratix 10 boards items: - enum: --=20 2.39.2 From nobody Fri Nov 22 11:46:30 2024 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D50B1ADFE4; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da28ba80sm92424375e9.29.2024.11.16.05.10.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Nov 2024 05:10:33 -0800 (PST) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org Cc: marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 05/11] ARM: dts: socfpga: add Enclustra Mercury+ SA2 Date: Sat, 16 Nov 2024 13:10:19 +0000 Message-Id: <20241116131025.114542-6-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241116131025.114542-1-l.rubusch@gmail.com> References: <20241116131025.114542-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce Enclustra's Mercury+ SA2 SoM based on Intel Cyclone5 technology as a .dtsi file. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- .../socfpga/socfpga_cyclone5_mercury_sa2.dtsi | 146 ++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2.dtsi diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.d= tsi b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.dtsi new file mode 100644 index 000000000..f46f1410f --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.dtsi @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2"; + compatible =3D "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + aliases { + ethernet0 =3D &gmac1; + }; + + /* Adjusted the i2c labels to use generic base-board dtsi files for + * Enclustra Arria10 and Cyclone5 SoMs. + * + * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in + * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi + * fragments. Thus define generic labels here to match the correct i2c + * bus in a generic base-board .dtsi file. + */ + soc { + i2c_encl: i2c@ffc04000 { + }; + i2c_encl_fpga: i2c@ffc05000 { + }; + }; + + memory { + name =3D "memory"; + device_type =3D "memory"; + reg =3D <0x0 0x80000000>; /* 2GB */ + }; +}; + +&osc1 { + clock-frequency =3D <50000000>; +}; + +&i2c_encl { + i2c-sda-hold-time-ns =3D <300>; + clock-frequency =3D <100000>; + status =3D "okay"; + + isl12020: rtc@6f { + compatible =3D "isil,isl12022"; + reg =3D <0x6f>; + }; + + atsha204a: crypto@64 { + compatible =3D "atmel,atsha204a"; + reg =3D <0x64>; + }; +}; + +&i2c_encl_fpga { + i2c-sda-hold-time-ns =3D <300>; + status =3D "disabled"; +}; + +&uart0 { + clock-frequency =3D <100000000>; +}; + +&mmc0 { + status =3D "okay"; +}; + +&qspi { + status =3D "okay"; + + flash0: flash@0 { + u-boot,dm-pre-reloc; + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "spansion,s25fl512s", "jedec,spi-nor"; + reg =3D <0>; + + spi-rx-bus-width =3D <4>; + spi-tx-bus-width =3D <4>; + spi-max-frequency =3D <10000000>; + + cdns,read-delay =3D <4>; + cdns,tshsl-ns =3D <50>; + cdns,tsd2d-ns =3D <50>; + cdns,tchsh-ns =3D <4>; + cdns,tslch-ns =3D <4>; + + partition@raw { + label =3D "Flash Raw"; + reg =3D <0x0 0x4000000>; + }; + }; +}; + +&gpio0 { + status =3D "okay"; +}; + +&gpio1 { + status =3D "okay"; +}; + +&gmac1 { + status =3D "okay"; + /delete-property/ mac-address; + phy-mode =3D "rgmii"; + phy-handle =3D <&phy3>; + + mdio0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + + phy3: ethernet-phy@3 { + reg =3D <3>; + + /* Add 2ns RX clock delay (1.2ns + 0.78ns)*/ + rxc-skew-ps =3D <1680>; + rxd0-skew-ps =3D <420>; + rxd1-skew-ps =3D <420>; + rxd2-skew-ps =3D <420>; + rxd3-skew-ps =3D <420>; + rxdv-skew-ps =3D <420>; + + /* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/ + txc-skew-ps =3D <1860>; + txd0-skew-ps =3D <0>; + txd1-skew-ps =3D <0>; + txd2-skew-ps =3D <0>; + txd3-skew-ps =3D <0>; + txen-skew-ps =3D <0>; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da28ba80sm92424375e9.29.2024.11.16.05.10.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Nov 2024 05:10:34 -0800 (PST) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org Cc: marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v5 06/11] dt-bindings: altera: add binding for Mercury+ SA2 Date: Sat, 16 Nov 2024 13:10:20 +0000 Message-Id: <20241116131025.114542-7-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241116131025.114542-1-l.rubusch@gmail.com> References: <20241116131025.114542-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update the device-tree binding for the Enclustra Mercury+ SA2 SoM. Signed-off-by: Lothar Rubusch Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/altera.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentat= ion/devicetree/bindings/arm/altera.yaml index 87a22d2a4..31af6859d 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -61,6 +61,16 @@ properties: - const: altr,socfpga-cyclone5 - const: altr,socfpga =20 + - description: Mercury+ SA2 boards + items: + - enum: + - enclustra,mercury-sa2-pe1 + - enclustra,mercury-sa2-pe3 + - enclustra,mercury-sa2-st1 + - const: enclustra,mercury-sa2 + - const: altr,socfpga-cyclone5 + - const: altr,socfpga + - description: Stratix 10 boards items: - enum: --=20 2.39.2 From nobody Fri Nov 22 11:46:30 2024 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A6E8195985; Sat, 16 Nov 2024 13:10:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731762639; cv=none; b=BSg0MXfTkdlyV6NDjgvrjmxRrgCj6+8DR90T+VRvY+9uHHvhrBGIuMtANsJzc4uPX3cuCDTCNS3IuuIGtCyde03CJ7oqaBSAfFtKOTJEk8MgSkrJlqtP8EDWj8RlDJS9XtJglH1fTc5+3BgPzuKz+XWEK/3kzyRovTgzLpp47H0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731762639; c=relaxed/simple; bh=VSX6Tupea+lveH5OF2V660luvXroshLKhKowGY60eC0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=EPPNy6ONifcC4+36iJ2FFnegmomLcqH78pCg2sxtP20g/7dTSYvG1PBwnwGrjz2ceYKGbjDDqK+j7UtOhjg7sF6ANjARRYteehb6ggqjpCWEY8xSK6Zu6k1gMccdgoI6cZdI4uWQelLkeDd0W3erG+B9Et73yt6uQUlBe6MRUVQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=PXHo6KTW; arc=none smtp.client-ip=209.85.221.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PXHo6KTW" Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-37d5045987dso258805f8f.1; Sat, 16 Nov 2024 05:10:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1731762636; x=1732367436; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gB3ulxCecmsW7fjuWD1ocrPoiUFrXT+TWPSU1MrEKrA=; b=PXHo6KTWkBn3fYBQ8azJKCHmdgsdMD+BtWDMostP2Hlx05RGBFiKQN4nFRs5OYZbTW Wo8ScPcjUP4URdqmWB/CgOF00YjjIWd6KZotOVwR9OU3GxmrT4W5XKd95LOaZ5aEcx6V HyummuQ2gHtGZPtaYx2rTq+bxIbYxF6WtChVDx1QF2NEu3DoFtXbaAMavTXtdehCB3JR pb7AssmhTM3K7eJn7F5ek/PuqyUOihceh46Ut3mIEUsgewCcvvPAwBPD8Cxc4+TdahlG wzGIlNn1rfC43Re/y+jfayQZ0vwIBLgYBcMhCQkHVREnp6GqxnIeqQI7PITY2GkXudJ7 r4zA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731762636; x=1732367436; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gB3ulxCecmsW7fjuWD1ocrPoiUFrXT+TWPSU1MrEKrA=; b=LB/EtIJW8vEkzbx86YF5Nx+IyDMtWjs8YUF0/7UcgSPw25qQQ3h1GYuMpnOZl/hVF4 7KYKt7M88pUgAhOShUZlPS1s+rqx2nn3Q5dl8VZDeeLxQEto5/yOtdiK0fYYVDLQzkRF Cb+TOJYqKpr2HVQEfLR0knCuOwp71ALrLRQuHsl+Yb55a/vHi1guXyvklv8delFPxhhq vdlfjX3+MAYbybgN20b2vgnuPv2N3/kXRpCOAKCk7Q4K9RGemi+d8te/3OctxQiKehS8 6ZLCRI74uMG115g1XIOKzwY68GgaUcQ14jV1C2VZpEpeuNetkRMDqvQ06WVSmC47bYUG SxnQ== X-Forwarded-Encrypted: i=1; AJvYcCU8TXLIaE7AOFgf4GkmvAD3s3hTielgj3Bn8H+E38M/iX+JDfVq3BWHR2/jejCbFMVlSCBnn53exbGy@vger.kernel.org, AJvYcCXwYuBy0WkeG4E4p000g4yIjFdqiZHMvFKeHkgJ7I+YcSYKl1ibu8uEG1SQ6ATija/6pXNVtWxvdMGWpmRd@vger.kernel.org X-Gm-Message-State: AOJu0YyDxUr4yHZ3ijEOkGMaoBEa/aWmWi1oI4wo69n9V1S6fBX7Enw7 PxVu+N+1V2DQP6Ar2evJBnXTfSFFMRtUR33nri8eDeYH5OvaqIkF X-Google-Smtp-Source: AGHT+IEj0WfYDhjcOKOoyiKe++NDFUW6QqxTyrv7WCpZdG/AbHV6ZXBJ8Nm61tf5WL0/2POhCgssIg== X-Received: by 2002:a05:600c:4710:b0:42c:ba6c:d9a7 with SMTP id 5b1f17b1804b1-432df7878bcmr22275335e9.4.1731762636000; Sat, 16 Nov 2024 05:10:36 -0800 (PST) Received: from 5dfbf0f66296.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da28ba80sm92424375e9.29.2024.11.16.05.10.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Nov 2024 05:10:35 -0800 (PST) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org Cc: marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 07/11] ARM: dts: socfpga: add Mercury AA1 combinations Date: Sat, 16 Nov 2024 13:10:21 +0000 Message-Id: <20241116131025.114542-8-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241116131025.114542-1-l.rubusch@gmail.com> References: <20241116131025.114542-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce support for Enclustra's Mercury+ AA1 SoM, based on Intel Arria10. This is a flexible approach to allow for combining SoM with carrier board .dtsi and boot-mode .dtsi in a device-tree file. Signed-off-by: Andreas Buerkler Signed-off-by: Lothar Rubusch --- .../socfpga/socfpga_arria10_mercury_aa1.dtsi | 141 +++++++++++++++--- 1 file changed, 120 insertions(+), 21 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dt= si b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi index 41f865c8c..41351d58f 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi @@ -7,12 +7,14 @@ =20 / { =20 - model =3D "Enclustra Mercury AA1"; - compatible =3D "enclustra,mercury-aa1", "altr,socfpga-arria10", "altr,soc= fpga"; + model =3D "Enclustra Mercury+ AA1"; + compatible =3D "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; =20 aliases { ethernet0 =3D &gmac0; serial1 =3D &uart1; + spi0 =3D &qspi; }; =20 memory@0 { @@ -24,52 +26,102 @@ memory@0 { chosen { stdout-path =3D "serial1:115200n8"; }; + + /* Adjusted the i2c labels to use generic base-board dtsi files for + * Enclustra Arria10 and Cyclone5 SoMs. + * + * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in + * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi + * fragments. Thus define generic labels here to match the correct i2c + * bus in a generic base-board .dtsi file. + */ + soc { + i2c_encl: i2c@ffc02300 { + }; + i2c_encl_fpga: i2c@ffc02200 { + }; + }; +}; + +&i2c_encl { + status =3D "okay"; + i2c-sda-hold-time-ns =3D <300>; + clock-frequency =3D <100000>; + + atsha204a: crypto@64 { + compatible =3D "atmel,atsha204a"; + reg =3D <0x64>; + }; + + isl12022: rtc@6f { + compatible =3D "isil,isl12022"; + reg =3D <0x6f>; + }; +}; + +&i2c_encl_fpga { + i2c-sda-hold-time-ns =3D <300>; + status =3D "disabled"; }; =20 &gmac0 { + status =3D "okay"; phy-mode =3D "rgmii"; phy-addr =3D <0xffffffff>; /* probe for phy addr */ - max-frame-size =3D <3800>; - phy-handle =3D <&phy3>; =20 + /delete-property/ mac-address; + mdio { #address-cells =3D <1>; #size-cells =3D <0>; compatible =3D "snps,dwmac-mdio"; phy3: ethernet-phy@3 { - txd0-skew-ps =3D <0>; /* -420ps */ - txd1-skew-ps =3D <0>; /* -420ps */ - txd2-skew-ps =3D <0>; /* -420ps */ - txd3-skew-ps =3D <0>; /* -420ps */ + reg =3D <3>; + + /* Add 2ns RX clock delay (1.2ns + 0.78ns)*/ + rxc-skew-ps =3D <1680>; /* 780ps */ rxd0-skew-ps =3D <420>; /* 0ps */ rxd1-skew-ps =3D <420>; /* 0ps */ rxd2-skew-ps =3D <420>; /* 0ps */ rxd3-skew-ps =3D <420>; /* 0ps */ - txen-skew-ps =3D <0>; /* -420ps */ - txc-skew-ps =3D <1860>; /* 960ps */ rxdv-skew-ps =3D <420>; /* 0ps */ - rxc-skew-ps =3D <1680>; /* 780ps */ - reg =3D <3>; + + /* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/ + txc-skew-ps =3D <1860>; /* 960ps */ + txd0-skew-ps =3D <0>; /* -420ps */ + txd1-skew-ps =3D <0>; /* -420ps */ + txd2-skew-ps =3D <0>; /* -420ps */ + txd3-skew-ps =3D <0>; /* -420ps */ + txen-skew-ps =3D <0>; /* -420ps */ }; }; }; =20 -&i2c1 { - atsha204a: crypto@64 { - compatible =3D "atmel,atsha204a"; - reg =3D <0x64>; - }; +&gpio0 { + status =3D "okay"; +}; =20 - isl12022: isl12022@6f { - compatible =3D "isil,isl12022"; - reg =3D <0x6f>; - }; +&gpio1 { + status =3D "okay"; +}; + +&gpio2 { + status =3D "okay"; +}; + +&uart0 { + status =3D "disabled"; +}; + +&uart1 { + status =3D "okay"; }; =20 /* Following mappings are taken from arria10 socdk dts */ &mmc { + status =3D "okay"; cap-sd-highspeed; broken-cd; bus-width =3D <4>; @@ -79,3 +131,50 @@ &mmc { &osc1 { clock-frequency =3D <33330000>; }; + +&eccmgr { + sdmmca-ecc@ff8c2c00 { + compatible =3D "altr,socfpga-sdmmc-ecc"; + reg =3D <0xff8c2c00 0x400>; + altr,ecc-parent =3D <&mmc>; + interrupts =3D <15 IRQ_TYPE_LEVEL_HIGH>, + <47 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>, + <48 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&qspi { + status =3D "okay"; + flash0: flash@0 { + u-boot,dm-pre-reloc; + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "spansion,s25fl512s", "jedec,spi-nor"; + reg =3D <0>; + + spi-rx-bus-width =3D <4>; + spi-tx-bus-width =3D <4>; + spi-max-frequency =3D <10000000>; + + cdns,read-delay =3D <4>; + cdns,tshsl-ns =3D <50>; + cdns,tsd2d-ns =3D <50>; + cdns,tchsh-ns =3D <4>; + cdns,tslch-ns =3D <4>; + + partition@raw { + label =3D "Flash Raw"; + reg =3D <0x0 0x4000000>; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da28ba80sm92424375e9.29.2024.11.16.05.10.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Nov 2024 05:10:36 -0800 (PST) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org Cc: marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v5 08/11] dt-bindings: altera: add Mercury AA1 combinations Date: Sat, 16 Nov 2024 13:10:22 +0000 Message-Id: <20241116131025.114542-9-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241116131025.114542-1-l.rubusch@gmail.com> References: <20241116131025.114542-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update binding with combined .dts for the Mercury+ PE1, PE3 and ST1 carrier boards with the Mercury+ AA1 SoM. Signed-off-by: Lothar Rubusch Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/altera.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentat= ion/devicetree/bindings/arm/altera.yaml index 31af6859d..51f10ff8e 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -32,6 +32,9 @@ properties: items: - enum: - enclustra,mercury-pe1 + - enclustra,mercury-aa1-pe1 + - enclustra,mercury-aa1-pe3 + - enclustra,mercury-aa1-st1 - google,chameleon-v3 - const: enclustra,mercury-aa1 - const: altr,socfpga-arria10 --=20 2.39.2 From nobody Fri Nov 22 11:46:30 2024 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0D601BD003; Sat, 16 Nov 2024 13:10:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731762643; cv=none; b=iG9jI+0GawMyngwZH5GP3NjKJHhlFNvzYWyyECtBfEP3yFvDmWoygw295lTM2mUZX3Yp3YFaoqQ6qKmtGmupp4t0bV8qV5/kW7qLn38H7fXoIIQGm9i2pvP9s2uwNuuTY92vG/YwuBJRRL36w7MOfquqOsj7QQfg97PeJLbdzGY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731762643; c=relaxed/simple; bh=Mok9Eqm2R+qKa9UoCehjK4ygp/HkMoEY0E+Vkh2yLJM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Iif56APWv1dA1pONwHXgUk76B41UUHWOZoMWYNjEWZcD33nonqQc7jxSJP5eHekHnFmtgXOFXVkvFU7Pkcv7W0NGsdNjxRh19EOy93MPkaGpiFcodmB9qKYX/nnXNQ3/QU/XFo1KQ0EIQzkfA19r1EA+alAoGuPwj8P4Lin//x8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=cP7+GAwj; arc=none smtp.client-ip=209.85.221.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="cP7+GAwj" Received: by mail-wr1-f49.google.com with SMTP id ffacd0b85a97d-38226e899feso189739f8f.1; Sat, 16 Nov 2024 05:10:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1731762639; x=1732367439; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DSxbet86oEBicVxt3ZGD+YsYIZpnYVjjludJtf8eu7M=; b=cP7+GAwj9vd1QpwEjuX88P/qupmVYFfnEmTg6ycw969fJC/6vM1595MpAaISfWaauq +0fPfvmt74Cs2becRRIgWaWefdlG34C6vOLCsXzvK98ihlNhcuT+0INai9Ap4Xja0l+X X86fWfZ/fafcwttDJKm2BrgVLWZL32lC+ueDX4llrd75uPea9z2s3JBlSkKdYWLoNi1X 0TKMKZU+KXUwkj7JkqKO+h8MCl8pmCcn2qZ5ujh/bfiImwRyz+Ehy7qlC9fCVk05ZQLs jxKnCEUWTIRq3i9KWQHisGkuxuTysJtPnVEt+5AuE/xB0JZHbRCPU72Oy/LYzzWkjh1W v2Fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731762639; x=1732367439; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DSxbet86oEBicVxt3ZGD+YsYIZpnYVjjludJtf8eu7M=; b=lHdi0QJTSTIkGElm1rY06T5YVMmsMwLwEWCJprHr6pfB+SqJoujMeo659JXAGCrSQX rog++ciENFYSjRw/z3CuJQSEqbnUwUXbKlw/FvEAVwm9LluTyQzkMHjb/DthTqJ3n8Do XGghjcqx9U5PTRtVHrFsK2p1RYuNoix+s6NM7GkQLlhX05PwKZ8K1C95HHW1xgV4SGlr PWapI2KYk6h0bMIYW6tz8EE9aUKn5G+d77cx/aYnR/E+wOAPuqdQNgvN08OKVFAX4mTH Ziru8O6dLf5ry6HdfMMB1tjsfBmKXxXCF9eJ/4Kr6SUL8lN/ZZfl07dDA7USTkJkhASA 0Xvg== X-Forwarded-Encrypted: i=1; AJvYcCVY5Se35ayBJzDyA6d6oTDrN6eC2YlRJL61V8dgs/keINRWVh6y4buxxDJ/vkvfLH/wLM4++R5TuFP26fjH@vger.kernel.org, AJvYcCXKlVQBteCyFWEqL153ZJEdCW2K0S45J0E+4CVX/JcGerF6/KxVpc1q5GhmwKo4Yj+WEwjjbog4n+W8@vger.kernel.org X-Gm-Message-State: AOJu0YwjG/UKdcB3hR6FWPQJEEx56baBDzbyZXu2zfK/KdywJ+imGpL/ laXYmytJBwzMp/HIsBC7pnwAGQ+ekPGwFde0yiBKolArxExZP8fw X-Google-Smtp-Source: AGHT+IEruRvbEDZVwSwuDlE4FyNnKYTYWwQBbXGEj5nH4+i6uSd2yEmET9Ob1bzvVOof2hE1POgiDA== X-Received: by 2002:a05:600c:1d0f:b0:42c:ba6c:d9b1 with SMTP id 5b1f17b1804b1-432df78abf8mr22708075e9.4.1731762638826; Sat, 16 Nov 2024 05:10:38 -0800 (PST) Received: from 5dfbf0f66296.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da28ba80sm92424375e9.29.2024.11.16.05.10.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Nov 2024 05:10:38 -0800 (PST) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org Cc: marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 09/11] ARM: dts: socfpga: removal of generic PE1 dts Date: Sat, 16 Nov 2024 13:10:23 +0000 Message-Id: <20241116131025.114542-10-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241116131025.114542-1-l.rubusch@gmail.com> References: <20241116131025.114542-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove the older socfpga_arria10_mercury_pe1.dts, since it is duplicate, the hardware is covered by the combination of Enclustra's .dtsi files. The older .dts was limited to only the case of having an Enclustra Mercury+ AA1 on a Mercury+ PE1 base board, booting from sdmmc. This functionality is provided also by the generic Enclustra dtsi and dts files, in particular socfpga_arria10_mercury_aa1_pe1_sdmmc.dts. Since both .dts files cover the same, the older one is to e replaced in favor of the more modularized approach. Signed-off-by: Lothar Rubusch Acked-by: Steffen Trumtrar --- arch/arm/boot/dts/intel/socfpga/Makefile | 1 - .../socfpga/socfpga_arria10_mercury_pe1.dts | 55 ------------------- 2 files changed, 56 deletions(-) delete mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _pe1.dts diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/i= ntel/socfpga/Makefile index c467828ae..d95862e34 100644 --- a/arch/arm/boot/dts/intel/socfpga/Makefile +++ b/arch/arm/boot/dts/intel/socfpga/Makefile @@ -2,7 +2,6 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) +=3D \ socfpga_arria5_socdk.dtb \ socfpga_arria10_chameleonv3.dtb \ - socfpga_arria10_mercury_pe1.dtb \ socfpga_arria10_socdk_nand.dtb \ socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dt= s b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dts deleted file mode 100644 index cf533f76a..000000000 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dts +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2023 Steffen Trumtrar - */ -/dts-v1/; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da28ba80sm92424375e9.29.2024.11.16.05.10.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Nov 2024 05:10:39 -0800 (PST) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org Cc: marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v5 10/11] dt-bindings: altera: removal of generic PE1 dts Date: Sat, 16 Nov 2024 13:10:24 +0000 Message-Id: <20241116131025.114542-11-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241116131025.114542-1-l.rubusch@gmail.com> References: <20241116131025.114542-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove the binding for the generic Mercury+ AA1 on PE1 carrier board. The removed Mercury+ AA1 on PE1 carrier board is just a particular setup case, which is actually replaced by the set of generic Mercury+ AA1 combinations patch. In other words a combination of a Mercury+ AA1 on a PE1 base board, with boot mode SD card is already covered by the generic AA1 combinations. There is no further reason to keep this particular case now in a redundantly. Thus the redundant DT setup is removed. Signed-off-by: Lothar Rubusch Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/altera.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentat= ion/devicetree/bindings/arm/altera.yaml index 51f10ff8e..1561f0164 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -31,7 +31,6 @@ properties: - description: Mercury+ AA1 boards items: - enum: - - enclustra,mercury-pe1 - enclustra,mercury-aa1-pe1 - enclustra,mercury-aa1-pe3 - enclustra,mercury-aa1-st1 --=20 2.39.2 From nobody Fri Nov 22 11:46:30 2024 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CEE561C07D8; Sat, 16 Nov 2024 13:10:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731762647; cv=none; b=HwwZ9mzBSRjmJmGYBIYYVXKrS8J6iRALXp7CTH4t4exXqftmXTpkfA217j7ps9C8ofeeUpcw0d+e9KICJDY3N/ca9sl2GDaUF1eHlAlzLpVvoLiLGVCLQWvTfS8/WYa1Qz5oj5BylOb092Z2tWK5DRQpGHh35bos93GiMmfColg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731762647; c=relaxed/simple; bh=5bm6zAYPQwHlOLQO5GKytRA+RLHffvDpOHPgwKlGfvE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Ma7qMAZAY3uqlwJCQlWh1oyYd3WiBbzVx85eqOpKMIlmEF20Z9wSHOmPnlLx1/u30Ylz8aGJuW4ewOYr2x3b1naXotmFWDsy0tWL9ZBL1IGQMJcG9KVOLWOsxlKtOW0TRjStertinkeEYJPsScWZZbm2b+b/3vZGMQkbqTk4tVY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=RkANBOJu; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="RkANBOJu" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-43152fa76aaso2754435e9.1; Sat, 16 Nov 2024 05:10:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1731762643; x=1732367443; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G6mt2x7HIFOx4MTaB8/TH87mFym2+YiqB6QlCAqPVnE=; b=RkANBOJuDONHtL/Ka1ELujwemyhshNWzAJ/4e+lwJigUex300a80yJabvLZ55FQgvx T5vFee8zZvkqrDk1mvG47g5rEI/uoCeA5/QfZuv4cU9dzVufmMCS1v5ejkf0AFpEiB28 ZvPu43SA36nTm4bZ4WwNVTmfLrVdzcmzl4YYQQUSemUMWR0F9pFpnUSQU58vG9kq+7jR wkucdMb857jVvjU7Hojw4E4LPV04pXxhlU07PEB8Dqj5gYTC0d3hrGC3o6I/0d8YChDL eQXUXWK7VE60iXKgjehA5Ev9acVjgyN/+H442jHBnQtsiIU9qeBxTxBg9Q5bASEwQzHY FS9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731762643; x=1732367443; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G6mt2x7HIFOx4MTaB8/TH87mFym2+YiqB6QlCAqPVnE=; b=bLf7aRvIot0BDtNJhlRLy2vRdODVGhRdwLJEmFrnIRtCKEv0yUhLyVO1ueUVnUA0r2 rj/94NKljIJw2uUGDsTK/eUua+xikfnIdZOvxNJGMoTd0nNBXhU100SMJPMiR+VACWMC I2LCyTLONCg+/UQ+OrrMI5ETFqCbmYVISG9+Zx6TKbo64gvdc+aFrBmZY7gW4Bz4aRgq dxfBKkXZ8depXvwk/i1hiaCmhfcNS3sl6kf8OZxT32RDYzk3vWkjKCpqlTDPZ1vrSIlv Mgj/ZV2myqcen4YKKJAujfQ4f90VkAGNa4k9GH+LvdWNR0DLVtZU+RaKXHY71wN+beR5 myCg== X-Forwarded-Encrypted: i=1; AJvYcCUkgA4WQClBYH+UPneYTYqj82Wd39DoWHSohUbJU82b3axCgOydPVedXJen4IozlJe+BqQQanVTS+sH@vger.kernel.org, AJvYcCXpJy/epO6K/wRjtX0kG9D0JR62xXL/1Y277CB/L0HiRHg50SkZWHKgY4ZDp6ZXaRD0icxy/jFMIw+kmSlF@vger.kernel.org X-Gm-Message-State: AOJu0Yxo0tdiLs3+6unz+MotCtnbOsKOJO3iqDXgpAOwrl/Hi5DrVjc9 ZJah3cT7tz29aLyPmZm2nzrAMcnCmBBOFOPC5/TSfVEa65awJ4jM X-Gm-Gg: ASbGncv6/F7+tECZDlpIWSdZYTdgPn5JwUbqUlSW/zL/QjqKwEXJpZnOgaH2CAL30ZZ wSfhona+7G71yPKm8djuuRQ3ZgNVQ0tw/xH0ft60YXh2cBcJsT43NWf0iTdVOtcfkVEPrrqn7S5 OYhMi69btsK8Wv1nfgkO4Hh31UkTHPa8TK4k5IgV1QgWftUCe8mSHjkXueDET5bEUkVzBew6d9p EZuxE6tairUQP+Bnp9O7H6lgs20tK3A6zkrs/tbvkKwpXOJKSn+4+pKdasN4s6pI/29Ujv7NZeq yv5WwM4PwRSfA7PDOB7S6OnusSFC X-Google-Smtp-Source: AGHT+IF14UYiFyr/5Z+V3uJ/L5DllHwSPXpjCSY9CJbyH7T4SIz/KKzmYNJT4SgTobsb/uQhrefVRQ== X-Received: by 2002:a05:6000:2a7:b0:37d:5436:415e with SMTP id ffacd0b85a97d-38225a94559mr2188674f8f.12.1731762641700; Sat, 16 Nov 2024 05:10:41 -0800 (PST) Received: from 5dfbf0f66296.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da28ba80sm92424375e9.29.2024.11.16.05.10.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Nov 2024 05:10:41 -0800 (PST) From: Lothar Rubusch To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dinguyen@kernel.org Cc: marex@denx.de, s.trumtrar@pengutronix.de, l.rubusch@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 11/11] ARM: dts: socfpga: add Enclustra SoM dts files Date: Sat, 16 Nov 2024 13:10:25 +0000 Message-Id: <20241116131025.114542-12-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241116131025.114542-1-l.rubusch@gmail.com> References: <20241116131025.114542-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the approach to set up a combination of Enclustra's SoM on a carrier board and corresponding boot-mode as single device-tree target. Signed-off-by: Lothar Rubusch --- arch/arm/boot/dts/intel/socfpga/Makefile | 24 +++++++++++++++++++ .../socfpga_arria10_mercury_aa1_pe1_emmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe1_qspi.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe1_sdmmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe3_emmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe3_qspi.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_pe3_sdmmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_st1_emmc.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_st1_qspi.dts | 16 +++++++++++++ .../socfpga_arria10_mercury_aa1_st1_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_pe1_emmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_pe1_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_pe3_emmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_pe3_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_st1_emmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa1_st1_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa2_pe1_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa2_pe3_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts | 16 +++++++++++++ .../socfpga_cyclone5_mercury_sa2_st1_qspi.dts | 16 +++++++++++++ ...socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts | 16 +++++++++++++ 25 files changed, 408 insertions(+) create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe1_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe3_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe3_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_pe3_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_st1_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_st1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury= _aa1_st1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe1_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe3_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe3_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_pe3_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_st1_emmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_st1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa1_st1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_pe1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_pe1_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_pe3_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_pe3_sdmmc.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_st1_qspi.dts create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercur= y_sa2_st1_sdmmc.dts diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/i= ntel/socfpga/Makefile index d95862e34..861880560 100644 --- a/arch/arm/boot/dts/intel/socfpga/Makefile +++ b/arch/arm/boot/dts/intel/socfpga/Makefile @@ -2,6 +2,30 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) +=3D \ socfpga_arria5_socdk.dtb \ socfpga_arria10_chameleonv3.dtb \ + socfpga_arria10_mercury_aa1_pe1_emmc.dtb \ + socfpga_arria10_mercury_aa1_pe1_qspi.dtb \ + socfpga_arria10_mercury_aa1_pe1_sdmmc.dtb \ + socfpga_arria10_mercury_aa1_pe3_emmc.dtb \ + socfpga_arria10_mercury_aa1_pe3_qspi.dtb \ + socfpga_arria10_mercury_aa1_pe3_sdmmc.dtb \ + socfpga_arria10_mercury_aa1_st1_emmc.dtb \ + socfpga_arria10_mercury_aa1_st1_qspi.dtb \ + socfpga_arria10_mercury_aa1_st1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe1_emmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe1_qspi.dtb \ + socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe3_emmc.dtb \ + socfpga_cyclone5_mercury_sa1_pe3_qspi.dtb \ + socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa1_st1_emmc.dtb \ + socfpga_cyclone5_mercury_sa1_st1_qspi.dtb \ + socfpga_cyclone5_mercury_sa1_st1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa2_pe1_qspi.dtb \ + socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa2_pe3_qspi.dtb \ + socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dtb \ + socfpga_cyclone5_mercury_sa2_st1_qspi.dtb \ + socfpga_cyclone5_mercury_sa2_st1_sdmmc.dtb \ socfpga_arria10_socdk_nand.dtb \ socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 1_emmc.dts new file mode 100644 index 000000000..b6cca0b5f --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_emmc.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 1_qspi.dts new file mode 100644 index 000000000..6ad023477 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_qspi.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-aa1-pe1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_p= e1_sdmmc.dts new file mode 100644 index 000000000..653c9a865 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_sdmmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-aa1-pe1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 3_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 3_emmc.dts new file mode 100644 index 000000000..ae9c7c6a2 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_emmc.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 3_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 3_qspi.dts new file mode 100644 index 000000000..c3a0c30a0 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_qspi.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe= 3_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_p= e3_sdmmc.dts new file mode 100644 index 000000000..dc1e1ad20 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_sdmmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-aa1-pe3", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st= 1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st= 1_emmc.dts new file mode 100644 index 000000000..61d5e4c85 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_emmc.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st= 1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st= 1_qspi.dts new file mode 100644 index 000000000..a3b99c9b1 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_qspi.= dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st= 1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_s= t1_sdmmc.dts new file mode 100644 index 000000000..5deb289e2 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_sdmmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_arria10_mercury_aa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ AA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-aa1-st1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= pe1_emmc.dts new file mode 100644 index 000000000..85d6146da --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_emmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= pe1_qspi.dts new file mode 100644 index 000000000..770ab680a --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1= _pe1_sdmmc.dts new file mode 100644 index 000000000..990ca0fec --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e3_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= pe3_emmc.dts new file mode 100644 index 000000000..6c8fd5b0d --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_emmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e3_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= pe3_qspi.dts new file mode 100644 index 000000000..329242607 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_p= e3_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1= _pe3_sdmmc.dts new file mode 100644 index 000000000..1eb10b524 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-sa1-pe3", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_s= t1_emmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= st1_emmc.dts new file mode 100644 index 000000000..8c97b5b3a --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_emmc= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_emmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_s= t1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_= st1_qspi.dts new file mode 100644 index 000000000..e6d14b22e --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_s= t1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1= _st1_sdmmc.dts new file mode 100644 index 000000000..beaeca94d --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa1.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury SA1 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-sa1-st1", "enclustra,mercury-sa1", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_p= e1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_= pe1_qspi.dts new file mode 100644 index 000000000..6f79d9ed1 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa2-pe1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_p= e1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2= _pe1_sdmmc.dts new file mode 100644 index 000000000..b94bd8baf --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ PE1 Base Board"; + compatible =3D "enclustra,mercury-sa2-pe1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_p= e3_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_= pe3_qspi.dts new file mode 100644 index 000000000..51fc4a229 --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-sa2-pe3", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_p= e3_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2= _pe3_sdmmc.dts new file mode 100644 index 000000000..e4209209f --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_pe3.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ PE3 Base Board"; + compatible =3D "enclustra,mercury-sa2-pe3", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_s= t1_qspi.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_= st1_qspi.dts new file mode 100644 index 000000000..ab4549a0d --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_qspi= .dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_qspi.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-sa2-st1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_s= t1_sdmmc.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2= _st1_sdmmc.dts new file mode 100644 index 000000000..ebe62879c --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_sdmm= c.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com + */ + +/dts-v1/; + +#include "socfpga_cyclone5_mercury_sa2.dtsi" +#include "socfpga_enclustra_mercury_st1.dtsi" +#include "socfpga_enclustra_mercury_bootmode_sdmmc.dtsi" + +/ { + model =3D "Enclustra Mercury+ SA2 on Mercury+ ST1 Base Board"; + compatible =3D "enclustra,mercury-sa2-st1", "enclustra,mercury-sa2", + "altr,socfpga-cyclone5", "altr,socfpga"; +}; --=20 2.39.2