From nobody Fri Nov 22 10:20:47 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E941191F70; Sat, 16 Nov 2024 03:16:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731726996; cv=none; b=cXrpmi8cabjxd61U/7lBVqM4WMNccXFpCYhyh6NhmCRdw2ap/EgdSgFgKEh4tpr2Snz222fXK9tihTecgILfGKP30cnYOWsZ+028gUIuq/4v9MyJwVPlMdxHOwc6S0+oFt+Y/x/KgKS4hDn0QeltmXkq03jZcqQpeEe8M2jijsY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731726996; c=relaxed/simple; bh=CUG0eH52NDidE/PJoAe9+/rx8o9cypiJmxEjyAm+45g=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=REuekgKkJh1qLfsUF6ziuNoZY8Y1vzHcd19DEnOMoUMFYiyFy875qmRX6RsD61EYJ0SFgB4tlH2vdXKtr87zhx7aGcQ+83EUsDrkQdoGtjZx0c03QWpuz76cdCiVjDEIvL/JGea4O4LxL1Aack+f+9YbDLoq9AuuNWTlsHEyxMc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=YHs8HPHh; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="YHs8HPHh" X-UUID: 2793de9ea3c911efbd192953cf12861f-20241116 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=W3c8PQN0aKUh7AVCyHAfN1JQE1bSoAJDK4PFKOUhuj4=; b=YHs8HPHhr/Vs2pAbU3gNHonwvMbVmhOWeTCBZagAH4bHhqsW4pyA2yAT3jT5gSZ8ujpN2dTMmtZbBFu95srUoMVjhYKL4VCT3uMbuGchj/4+AcQofylCBFyvZ5Ha2i8IuuJSrhTj04qDGNZN7KTm9Moxi9WSH+HOiRhnMZIoL1w=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.43,REQID:0b4ea149-55ba-4714-af3e-053923d57cba,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:ce19b8a,CLOUDID:89162a07-6ce0-4172-9755-bd2287e50583,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0,EDM:-3,IP :nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0, LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 2793de9ea3c911efbd192953cf12861f-20241116 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 321106510; Sat, 16 Nov 2024 11:16:21 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N2.mediatek.inc (172.21.101.76) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Sat, 16 Nov 2024 11:16:19 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Sat, 16 Nov 2024 11:16:18 +0800 From: Yunfei Dong To: =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= , Sebastian Fricke , Nicolas Dufresne , Hans Verkuil , AngeloGioacchino Del Regno , Benjamin Gaignard , Nathan Hebert , Daniel Almeida CC: Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , Steve Cho , "Yunfei Dong" , , , , , , Subject: [PATCH v6 1/3] media: mediatek: vcodec: remove vsi operation in common interface Date: Sat, 16 Nov 2024 11:16:10 +0800 Message-ID: <20241116031616.15656-2-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20241116031616.15656-1-yunfei.dong@mediatek.com> References: <20241116031616.15656-1-yunfei.dong@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--5.636800-8.000000 X-TMASE-MatchedRID: UFXUgs0G7u/htVvI3rIgyY+YSzwl92XTwx0jRRxcQfMnzvR+mP3cvgk2 ecCxHxhdshXHqIHwr0x7qnmUi7ghZcRBLZ5x+SkX4pdq9sdj8LXaoFJAcCHymBL6MU7t349bFYy XyKH+1Ua88mZorBs3kAMd5687Yqxynuh7s4XRTZaeAiCmPx4NwBnUJ0Ek6yhjxEHRux+uk8jHUU +U0ACZwO9iEYY1HiwIV6/Wd2nP0OjWUdoD23ScTMluaFmq/SYXnqg/VrSZEiM= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--5.636800-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: C950FD71F43B12320562034B56135C6C5351C74965BBD7DBE5EA1A3093CBB0B02000:8 X-MTK: N Content-Type: text/plain; charset="utf-8" Extend struct video shared information (vsi) to send different parameters to scp for mt8188 architecture is changed. Remove vsi related operation in common interface to make sure the interface can be called by extended and non extended architecture at the same time. The new extended interfaces with new vsi will be introduced in later patches. Signed-off-by: Yunfei Dong Reviewed-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- .../vcodec/decoder/vdec/vdec_h264_req_multi_if.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_= req_multi_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h= 264_req_multi_if.c index 1ed0ccec5665..ab192ce0b851 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_mul= ti_if.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_mul= ti_if.c @@ -171,9 +171,9 @@ struct vdec_h264_slice_inst { }; =20 static int vdec_h264_slice_fill_decode_parameters(struct vdec_h264_slice_i= nst *inst, - struct vdec_h264_slice_share_info *share_info) + struct vdec_h264_slice_share_info *share_info, + struct vdec_h264_slice_lat_dec_param *slice_param) { - struct vdec_h264_slice_lat_dec_param *slice_param =3D &inst->vsi->h264_sl= ice_params; const struct v4l2_ctrl_h264_decode_params *dec_params; const struct v4l2_ctrl_h264_scaling_matrix *src_matrix; const struct v4l2_ctrl_h264_sps *sps; @@ -266,9 +266,6 @@ static int get_vdec_sig_decode_parameters(struct vdec_h= 264_slice_inst *inst) mtk_vdec_h264_get_ref_list(b0_reflist, v4l2_b0_reflist, reflist_builder.n= um_valid); mtk_vdec_h264_get_ref_list(b1_reflist, v4l2_b1_reflist, reflist_builder.n= um_valid); =20 - memcpy(&inst->vsi_ctx.h264_slice_params, slice_param, - sizeof(inst->vsi_ctx.h264_slice_params)); - return 0; } =20 @@ -608,7 +605,8 @@ static int vdec_h264_slice_lat_decode(void *h_vdec, str= uct mtk_vcodec_mem *bs, lat_buf->src_buf_req =3D src_buf_info->m2m_buf.vb.vb2_buf.req_obj.req; v4l2_m2m_buf_copy_metadata(&src_buf_info->m2m_buf.vb, &lat_buf->ts_info, = true); =20 - err =3D vdec_h264_slice_fill_decode_parameters(inst, share_info); + err =3D vdec_h264_slice_fill_decode_parameters(inst, share_info, + &inst->vsi->h264_slice_params); if (err) goto err_free_fb_out; =20 @@ -749,6 +747,9 @@ static int vdec_h264_slice_single_decode(void *h_vdec, = struct mtk_vcodec_mem *bs if (err) goto err_free_fb_out; =20 + memcpy(&inst->vsi_ctx.h264_slice_params, &inst->h264_slice_param, + sizeof(inst->vsi_ctx.h264_slice_params)); + buf =3D (unsigned char *)bs->va; nal_start_idx =3D mtk_vdec_h264_find_start_code(buf, bs->size); if (nal_start_idx < 0) { --=20 2.46.0 From nobody Fri Nov 22 10:20:47 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20226191F92; Sat, 16 Nov 2024 03:16:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731726997; cv=none; b=qMY4yNJLgr5i2DIn4STEZlBRNL8Hdn0O0h+hkmnBF8ZluL8rCufbw/GoEgxAg9qV0pZrzTIcfxCXyEoSppYmuKNhODWjyjNH530CpEHCdWLu7J1B4fs989+EaJ5ZvV+zEZtom9Pl0MC1wPWNVlN5qBUWiNfztRpSH/gsluzOTcs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731726997; c=relaxed/simple; bh=MOD1EeaU9mm8ZVgYWdnwKAjwYBBgvaVmA8vPkQSw9P4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=njGLnniU94tcz35lGTm9vru/M7pejEp+i18/d4ZafyCwXtvLb77fxMfhTVYYmnR+EHZ66nBxNJn1l88gE9808gogFqqaXvSA39hMFvP+uR5bc0PUI//QZr4E/eSU8Gp+3kKkhwLBPaLlsrfTQEB2/8zWE81jBS+33VbGSZyqVm0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=Wkxto+OX; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Wkxto+OX" X-UUID: 2774a5c4a3c911efbd192953cf12861f-20241116 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=qfaqg+X6Tm9aljV+olG150kQG1XtkjPcPNgW+iJeTVY=; b=Wkxto+OX2D4KBxPBnCAefz7NrnyuJVo8HatEf27J0SIrFeGgCmspcr0Tx7Fw1MKz8YKnSvvWleJ771CjZ/TArl0Z0bg9QN0+JQAWkr4KcdF98ZVNy4ZWVFz0CScZvijccJXb+mTSeGe2MbMFVjHvslmOPQKuXK3dxL8n0VC9kVQ=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.43,REQID:2eda4b99-b745-43b6-9398-0184e223599b,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:ce19b8a,CLOUDID:a4ebb85c-f18b-4d56-b49c-93279ee09144,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0,EDM:-3,IP :nil,URL:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV :0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: 2774a5c4a3c911efbd192953cf12861f-20241116 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 50792410; Sat, 16 Nov 2024 11:16:21 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 15 Nov 2024 19:16:20 -0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Sat, 16 Nov 2024 11:16:19 +0800 From: Yunfei Dong To: =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= , Sebastian Fricke , Nicolas Dufresne , Hans Verkuil , AngeloGioacchino Del Regno , Benjamin Gaignard , Nathan Hebert , Daniel Almeida CC: Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , Steve Cho , Yunfei Dong , , , , , , Subject: [PATCH v6 2/3] media: mediatek: vcodec: support extended h264 decode Date: Sat, 16 Nov 2024 11:16:11 +0800 Message-ID: <20241116031616.15656-3-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20241116031616.15656-1-yunfei.dong@mediatek.com> References: <20241116031616.15656-1-yunfei.dong@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" The address end of working buffer can't be calculated directly with buffer size in kernel for some special architecture. Adding new extend vsi_ex to calculate the address end in firmware. Adding capability to separate extend and non extend driver for different platform. At last, hardware can parse the syntax to get nal information in firmware for extend architecture, needn't to parse it again in kernel. Signed-off-by: Yunfei Dong Reviewed-by: AngeloGioacchino Del Regno --- .../vcodec/decoder/mtk_vcodec_dec_drv.h | 2 + .../decoder/vdec/vdec_h264_req_multi_if.c | 575 ++++++++++++++++-- 2 files changed, 518 insertions(+), 59 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= drv.h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h index ac568ed14fa2..a0bb23962209 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h @@ -17,6 +17,7 @@ =20 #define IS_VDEC_LAT_ARCH(hw_arch) ((hw_arch) >=3D MTK_VDEC_LAT_SINGLE_CORE) #define IS_VDEC_INNER_RACING(capability) ((capability) & MTK_VCODEC_INNER_= RACING) +#define IS_VDEC_SUPPORT_EX(capability) ((capability) & MTK_VDEC_IS_SUPPORT= _EX) =20 enum mtk_vcodec_dec_chip_name { MTK_VDEC_INVAL =3D 0, @@ -42,6 +43,7 @@ enum mtk_vdec_format_types { MTK_VDEC_FORMAT_HEVC_FRAME =3D 0x1000, MTK_VCODEC_INNER_RACING =3D 0x20000, MTK_VDEC_IS_SUPPORT_10BIT =3D 0x40000, + MTK_VDEC_IS_SUPPORT_EX =3D 0x80000, }; =20 /* diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_= req_multi_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h= 264_req_multi_if.c index ab192ce0b851..a7de95b9a7c0 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_mul= ti_if.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_mul= ti_if.c @@ -128,6 +128,83 @@ struct vdec_h264_slice_share_info { u16 nal_info; }; =20 +/* + * struct vdec_h264_slice_mem - memory address and size (shared interface = with firmware) + */ +struct vdec_h264_slice_mem { + union { + u64 buf; + u64 dma_addr; + }; + union { + size_t size; + u64 dma_addr_end; + }; +}; + +/** + * struct vdec_h264_slice_fb - frame buffer for decoding (shared interface= with firmware) + * + * @y: current y buffer address info + * @c: current c buffer address info + */ +struct vdec_h264_slice_fb { + struct vdec_h264_slice_mem y; + struct vdec_h264_slice_mem c; +}; + +/** + * struct vdec_h264_slice_info_ex - extend decode information (shared inte= rface with firmware) + * + * @wdma_end_addr_offset: offset from buffer start + * @nal_info: nal info of current picture + * @timeout: Decode timeout: 1 timeout, 0 no timeout + * @reserved: reserved + * @vdec_fb_va: VDEC frame buffer struct virtual address + * @crc: Used to check whether hardware's status is right + */ +struct vdec_h264_slice_info_ex { + u64 wdma_end_addr_offset; + u16 nal_info; + u16 timeout; + u32 reserved; + u64 vdec_fb_va; + u32 crc[8]; +}; + +/** + * struct vdec_h264_slice_vsi_ex - extend shared memory for decode informa= tion exchange + * between SCP and Host (shared interface with firmware). + * + * @bs: input buffer info + * @fb: current y/c buffer + * + * @ube: ube buffer + * @trans: transcoded buffer + * @row_info: row info buffer + * @err_map: err map buffer + * @slice_bc: slice buffer + * + * @mv_buf_dma: HW working motion vector buffer + * @dec: decode information (AP-R, VPU-W) + * @h264_slice_params: decode parameters for hw used + */ +struct vdec_h264_slice_vsi_ex { + /* LAT dec addr */ + struct vdec_h264_slice_mem bs; + struct vdec_h264_slice_fb fb; + + struct vdec_h264_slice_mem ube; + struct vdec_h264_slice_mem trans; + struct vdec_h264_slice_mem row_info; + struct vdec_h264_slice_mem err_map; + struct vdec_h264_slice_mem slice_bc; + + struct vdec_h264_slice_mem mv_buf_dma[H264_MAX_MV_NUM]; + struct vdec_h264_slice_info_ex dec; + struct vdec_h264_slice_lat_dec_param h264_slice_params; +}; + /** * struct vdec_h264_slice_inst - h264 decoder instance * @@ -138,8 +215,10 @@ struct vdec_h264_slice_share_info { * @vpu: VPU instance * @vsi: vsi used for lat * @vsi_core: vsi used for core - * - * @vsi_ctx: Local VSI data for this decoding context + * @vsi_ctx: Local vsi data for this decoding context + * @vsi_ex: extend vsi used for lat + * @vsi_core_ex: extend vsi used for core + * @vsi_ctx_ex: Local extend vsi data for this decoding context * @h264_slice_param: the parameters that hardware use to decode * * @resolution_changed:resolution changed @@ -148,7 +227,9 @@ struct vdec_h264_slice_share_info { * * @dpb: decoded picture buffer used to store reference * buffer information - *@is_field_bitstream: is field bitstream + * @is_field_bitstream: is field bitstream + * + * @decode: lat decoder pointer for different architecture */ struct vdec_h264_slice_inst { unsigned int slice_dec_num; @@ -156,10 +237,18 @@ struct vdec_h264_slice_inst { struct mtk_vcodec_mem pred_buf; struct mtk_vcodec_mem mv_buf[H264_MAX_MV_NUM]; struct vdec_vpu_inst vpu; - struct vdec_h264_slice_vsi *vsi; - struct vdec_h264_slice_vsi *vsi_core; - - struct vdec_h264_slice_vsi vsi_ctx; + union { + struct { + struct vdec_h264_slice_vsi *vsi; + struct vdec_h264_slice_vsi *vsi_core; + struct vdec_h264_slice_vsi vsi_ctx; + }; + struct { + struct vdec_h264_slice_vsi_ex *vsi_ex; + struct vdec_h264_slice_vsi_ex *vsi_core_ex; + struct vdec_h264_slice_vsi_ex vsi_ctx_ex; + }; + }; struct vdec_h264_slice_lat_dec_param h264_slice_param; =20 unsigned int resolution_changed; @@ -168,6 +257,9 @@ struct vdec_h264_slice_inst { =20 struct v4l2_h264_dpb_entry dpb[16]; bool is_field_bitstream; + + int (*decode)(void *h_vdec, struct mtk_vcodec_mem *bs, + struct vdec_fb *unused, bool *res_chg); }; =20 static int vdec_h264_slice_fill_decode_parameters(struct vdec_h264_slice_i= nst *inst, @@ -389,62 +481,143 @@ static void vdec_h264_slice_get_crop_info(struct vde= c_h264_slice_inst *inst, cr->left, cr->top, cr->width, cr->height); } =20 -static int vdec_h264_slice_init(struct mtk_vcodec_dec_ctx *ctx) +static void vdec_h264_slice_setup_lat_buffer_ex(struct vdec_h264_slice_ins= t *inst, + struct mtk_vcodec_mem *bs, + struct vdec_lat_buf *lat_buf) { - struct vdec_h264_slice_inst *inst; - int err, vsi_size; + struct mtk_vcodec_mem *mem; + int i; =20 - inst =3D kzalloc(sizeof(*inst), GFP_KERNEL); - if (!inst) - return -ENOMEM; + inst->vsi_ex->bs.dma_addr =3D (u64)bs->dma_addr; + inst->vsi_ex->bs.size =3D bs->size; =20 - inst->ctx =3D ctx; + for (i =3D 0; i < H264_MAX_MV_NUM; i++) { + mem =3D &inst->mv_buf[i]; + inst->vsi_ex->mv_buf_dma[i].dma_addr =3D mem->dma_addr; + inst->vsi_ex->mv_buf_dma[i].size =3D mem->size; + } + inst->vsi_ex->ube.dma_addr =3D lat_buf->ctx->msg_queue.wdma_addr.dma_addr; + inst->vsi_ex->ube.size =3D lat_buf->ctx->msg_queue.wdma_addr.size; =20 - inst->vpu.id =3D SCP_IPI_VDEC_LAT; - inst->vpu.core_id =3D SCP_IPI_VDEC_CORE; - inst->vpu.ctx =3D ctx; - inst->vpu.codec_type =3D ctx->current_codec; - inst->vpu.capture_type =3D ctx->capture_fourcc; + inst->vsi_ex->row_info.dma_addr =3D 0; + inst->vsi_ex->row_info.size =3D 0; =20 - err =3D vpu_dec_init(&inst->vpu); - if (err) { - mtk_vdec_err(ctx, "vdec_h264 init err=3D%d", err); - goto error_free_inst; + inst->vsi_ex->err_map.dma_addr =3D lat_buf->wdma_err_addr.dma_addr; + inst->vsi_ex->err_map.size =3D lat_buf->wdma_err_addr.size; + + inst->vsi_ex->slice_bc.dma_addr =3D lat_buf->slice_bc_addr.dma_addr; + inst->vsi_ex->slice_bc.size =3D lat_buf->slice_bc_addr.size; + + inst->vsi_ex->trans.dma_addr_end =3D inst->ctx->msg_queue.wdma_rptr_addr; + inst->vsi_ex->trans.dma_addr =3D inst->ctx->msg_queue.wdma_wptr_addr; +} + +static int vdec_h264_slice_setup_core_buffer_ex(struct vdec_h264_slice_ins= t *inst, + struct vdec_h264_slice_share_info *share_info, + struct vdec_lat_buf *lat_buf) +{ + struct mtk_vcodec_mem *mem; + struct mtk_vcodec_dec_ctx *ctx =3D inst->ctx; + struct vb2_v4l2_buffer *vb2_v4l2; + struct vdec_fb *fb; + u64 y_fb_dma, c_fb_dma =3D 0; + int i; + + fb =3D ctx->dev->vdec_pdata->get_cap_buffer(ctx); + if (!fb) { + mtk_vdec_err(ctx, "fb buffer is NULL"); + return -EBUSY; } =20 - vsi_size =3D round_up(sizeof(struct vdec_h264_slice_vsi), VCODEC_DEC_ALIG= NED_64); - inst->vsi =3D inst->vpu.vsi; - inst->vsi_core =3D - (struct vdec_h264_slice_vsi *)(((char *)inst->vpu.vsi) + vsi_size); - inst->resolution_changed =3D true; - inst->realloc_mv_buf =3D true; + y_fb_dma =3D (u64)fb->base_y.dma_addr; + if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes =3D=3D 1) + c_fb_dma =3D + y_fb_dma + inst->ctx->picinfo.buf_w * inst->ctx->picinfo.buf_h; + else + c_fb_dma =3D (u64)fb->base_c.dma_addr; =20 - mtk_vdec_debug(ctx, "lat struct size =3D %d,%d,%d,%d vsi: %d\n", - (int)sizeof(struct mtk_h264_sps_param), - (int)sizeof(struct mtk_h264_pps_param), - (int)sizeof(struct vdec_h264_slice_lat_dec_param), - (int)sizeof(struct mtk_h264_dpb_info), - vsi_size); - mtk_vdec_debug(ctx, "lat H264 instance >> %p, codec_type =3D 0x%x", - inst, inst->vpu.codec_type); + mtk_vdec_debug(ctx, "[h264-core] y/c addr =3D 0x%llx 0x%llx", y_fb_dma, c= _fb_dma); =20 - ctx->drv_handle =3D inst; - return 0; + inst->vsi_core_ex->fb.y.dma_addr =3D y_fb_dma; + inst->vsi_core_ex->fb.y.size =3D ctx->picinfo.fb_sz[0]; + inst->vsi_core_ex->fb.c.dma_addr =3D c_fb_dma; + inst->vsi_core_ex->fb.c.size =3D ctx->picinfo.fb_sz[1]; =20 -error_free_inst: - kfree(inst); - return err; + inst->vsi_core_ex->dec.vdec_fb_va =3D (unsigned long)fb; + inst->vsi_core_ex->dec.nal_info =3D share_info->nal_info; + + inst->vsi_core_ex->ube.dma_addr =3D lat_buf->ctx->msg_queue.wdma_addr.dma= _addr; + inst->vsi_core_ex->ube.size =3D lat_buf->ctx->msg_queue.wdma_addr.size; + + inst->vsi_core_ex->err_map.dma_addr =3D lat_buf->wdma_err_addr.dma_addr; + inst->vsi_core_ex->err_map.size =3D lat_buf->wdma_err_addr.size; + + inst->vsi_core_ex->slice_bc.dma_addr =3D lat_buf->slice_bc_addr.dma_addr; + inst->vsi_core_ex->slice_bc.size =3D lat_buf->slice_bc_addr.size; + + inst->vsi_core_ex->row_info.dma_addr =3D 0; + inst->vsi_core_ex->row_info.size =3D 0; + + inst->vsi_core_ex->trans.dma_addr =3D share_info->trans_start; + inst->vsi_core_ex->trans.dma_addr_end =3D share_info->trans_end; + + for (i =3D 0; i < H264_MAX_MV_NUM; i++) { + mem =3D &inst->mv_buf[i]; + inst->vsi_core_ex->mv_buf_dma[i].dma_addr =3D mem->dma_addr; + inst->vsi_core_ex->mv_buf_dma[i].size =3D mem->size; + } + + vb2_v4l2 =3D v4l2_m2m_next_dst_buf(ctx->m2m_ctx); + v4l2_m2m_buf_copy_metadata(&lat_buf->ts_info, vb2_v4l2, true); + + return 0; } =20 -static void vdec_h264_slice_deinit(void *h_vdec) +static int vdec_h264_slice_core_decode_ex(struct vdec_lat_buf *lat_buf) { - struct vdec_h264_slice_inst *inst =3D h_vdec; + int err, timeout; + struct mtk_vcodec_dec_ctx *ctx =3D lat_buf->ctx; + struct vdec_h264_slice_inst *inst =3D ctx->drv_handle; + struct vdec_h264_slice_share_info *share_info =3D lat_buf->private_data; + struct vdec_vpu_inst *vpu =3D &inst->vpu; =20 - vpu_dec_deinit(&inst->vpu); - vdec_h264_slice_free_mv_buf(inst); - vdec_msg_queue_deinit(&inst->ctx->msg_queue, inst->ctx); + mtk_vdec_debug(ctx, "[h264-core] vdec_h264 core decode"); + memcpy(&inst->vsi_core_ex->h264_slice_params, &share_info->h264_slice_par= ams, + sizeof(share_info->h264_slice_params)); =20 - kfree(inst); + err =3D vdec_h264_slice_setup_core_buffer_ex(inst, share_info, lat_buf); + if (err) + goto vdec_dec_end; + + vdec_h264_slice_fill_decode_reflist(inst, &inst->vsi_core_ex->h264_slice_= params, + share_info); + err =3D vpu_dec_core(vpu); + if (err) { + mtk_vdec_err(ctx, "core decode err=3D%d", err); + goto vdec_dec_end; + } + + /* wait decoder done interrupt */ + timeout =3D mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED, + WAIT_INTR_TIMEOUT_MS, MTK_VDEC_CORE); + if (timeout) + mtk_vdec_err(ctx, "core decode timeout: pic_%d", ctx->decoded_frame_cnt); + inst->vsi_core_ex->dec.timeout =3D !!timeout; + + vpu_dec_core_end(vpu); + mtk_vdec_debug(ctx, "pic[%d] crc: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x= ", + ctx->decoded_frame_cnt, + inst->vsi_core_ex->dec.crc[0], inst->vsi_core_ex->dec.crc[1], + inst->vsi_core_ex->dec.crc[2], inst->vsi_core_ex->dec.crc[3], + inst->vsi_core_ex->dec.crc[4], inst->vsi_core_ex->dec.crc[5], + inst->vsi_core_ex->dec.crc[6], inst->vsi_core_ex->dec.crc[7]); + +vdec_dec_end: + vdec_msg_queue_update_ube_rptr(&lat_buf->ctx->msg_queue, share_info->tran= s_end); + ctx->dev->vdec_pdata->cap_to_disp(ctx, !!err, lat_buf->src_buf_req); + mtk_vdec_debug(ctx, "core decode done err=3D%d", err); + ctx->decoded_frame_cnt++; + return 0; } =20 static int vdec_h264_slice_core_decode(struct vdec_lat_buf *lat_buf) @@ -559,6 +732,127 @@ static void vdec_h264_insert_startcode(struct mtk_vco= dec_dec_dev *vcodec_dev, un (*bs_size) +=3D 4; } =20 +static int vdec_h264_slice_lat_decode_ex(void *h_vdec, struct mtk_vcodec_m= em *bs, + struct vdec_fb *fb, bool *res_chg) +{ + struct vdec_h264_slice_inst *inst =3D h_vdec; + struct vdec_vpu_inst *vpu =3D &inst->vpu; + struct mtk_video_dec_buf *src_buf_info; + int err, timeout =3D 0; + unsigned int data[2]; + struct vdec_lat_buf *lat_buf; + struct vdec_h264_slice_share_info *share_info; + + if (vdec_msg_queue_init(&inst->ctx->msg_queue, inst->ctx, + vdec_h264_slice_core_decode_ex, + sizeof(*share_info))) + return -ENOMEM; + + /* bs NULL means flush decoder */ + if (!bs) { + vdec_msg_queue_wait_lat_buf_full(&inst->ctx->msg_queue); + return vpu_dec_reset(vpu); + } + + if (inst->is_field_bitstream) + return -EINVAL; + + lat_buf =3D vdec_msg_queue_dqbuf(&inst->ctx->msg_queue.lat_ctx); + if (!lat_buf) { + mtk_vdec_debug(inst->ctx, "failed to get lat buffer"); + return -EAGAIN; + } + share_info =3D lat_buf->private_data; + src_buf_info =3D container_of(bs, struct mtk_video_dec_buf, bs_buffer); + + lat_buf->src_buf_req =3D src_buf_info->m2m_buf.vb.vb2_buf.req_obj.req; + v4l2_m2m_buf_copy_metadata(&src_buf_info->m2m_buf.vb, &lat_buf->ts_info, = true); + + err =3D vdec_h264_slice_fill_decode_parameters(inst, share_info, + &inst->vsi_ex->h264_slice_params); + if (err) + goto err_free_fb_out; + + vdec_h264_insert_startcode(inst->ctx->dev, bs->va, &bs->size, + &share_info->h264_slice_params.pps); + + *res_chg =3D inst->resolution_changed; + if (inst->resolution_changed) { + mtk_vdec_debug(inst->ctx, "- resolution changed -"); + if (inst->realloc_mv_buf) { + err =3D vdec_h264_slice_alloc_mv_buf(inst, &inst->ctx->picinfo); + inst->realloc_mv_buf =3D false; + if (err) + goto err_free_fb_out; + } + inst->resolution_changed =3D false; + } + + vdec_h264_slice_setup_lat_buffer_ex(inst, bs, lat_buf); + mtk_vdec_debug(inst->ctx, "lat:trans(0x%llx 0x%lx) err:0x%llx", + inst->vsi_ex->ube.dma_addr, (unsigned long)inst->vsi_ex->ube.size, + inst->vsi_ex->err_map.dma_addr); + + mtk_vdec_debug(inst->ctx, "slice(0x%llx 0x%lx) rprt((0x%llx 0x%llx))", + inst->vsi_ex->slice_bc.dma_addr, (unsigned long)inst->vsi_ex->sli= ce_bc.size, + inst->vsi_ex->trans.dma_addr, inst->vsi_ex->trans.dma_addr_end); + + err =3D vpu_dec_start(vpu, data, 2); + if (err) { + mtk_vdec_debug(inst->ctx, "lat decode err: %d", err); + goto err_free_fb_out; + } + + share_info->trans_end =3D inst->ctx->msg_queue.wdma_addr.dma_addr + + inst->vsi_ex->dec.wdma_end_addr_offset; + + share_info->trans_start =3D inst->ctx->msg_queue.wdma_wptr_addr; + share_info->nal_info =3D inst->vsi_ex->dec.nal_info; + + if (IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability)) { + memcpy(&share_info->h264_slice_params, &inst->vsi_ex->h264_slice_params, + sizeof(share_info->h264_slice_params)); + vdec_msg_queue_qbuf(&inst->ctx->msg_queue.core_ctx, lat_buf); + } + + /* wait decoder done interrupt */ + timeout =3D mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED, + WAIT_INTR_TIMEOUT_MS, MTK_VDEC_LAT0); + if (timeout) + mtk_vdec_err(inst->ctx, "lat decode timeout: pic_%d", inst->slice_dec_nu= m); + inst->vsi_ex->dec.timeout =3D !!timeout; + + err =3D vpu_dec_end(vpu); + if (err =3D=3D SLICE_HEADER_FULL || err =3D=3D TRANS_BUFFER_FULL) { + if (!IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability)) + vdec_msg_queue_qbuf(&inst->ctx->msg_queue.lat_ctx, lat_buf); + inst->slice_dec_num++; + mtk_vdec_err(inst->ctx, "lat dec fail: pic_%d err:%d", inst->slice_dec_n= um, err); + return -EINVAL; + } + + share_info->trans_end =3D inst->ctx->msg_queue.wdma_addr.dma_addr + + inst->vsi_ex->dec.wdma_end_addr_offset; + + vdec_msg_queue_update_ube_wptr(&lat_buf->ctx->msg_queue, share_info->tran= s_end); + + if (!IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability)) { + memcpy(&share_info->h264_slice_params, &inst->vsi_ex->h264_slice_params, + sizeof(share_info->h264_slice_params)); + vdec_msg_queue_qbuf(&inst->ctx->msg_queue.core_ctx, lat_buf); + } + mtk_vdec_debug(inst->ctx, "dec num: %d lat crc: 0x%x 0x%x 0x%x", inst->sl= ice_dec_num, + inst->vsi_ex->dec.crc[0], inst->vsi_ex->dec.crc[1], + inst->vsi_ex->dec.crc[2]); + + inst->slice_dec_num++; + return 0; +err_free_fb_out: + vdec_msg_queue_qbuf(&inst->ctx->msg_queue.lat_ctx, lat_buf); + mtk_vdec_err(inst->ctx, "slice dec number: %d err: %d", inst->slice_dec_n= um, err); + return err; +} + static int vdec_h264_slice_lat_decode(void *h_vdec, struct mtk_vcodec_mem = *bs, struct vdec_fb *fb, bool *res_chg) { @@ -704,18 +998,17 @@ static int vdec_h264_slice_lat_decode(void *h_vdec, s= truct mtk_vcodec_mem *bs, return err; } =20 -static int vdec_h264_slice_single_decode(void *h_vdec, struct mtk_vcodec_m= em *bs, - struct vdec_fb *unused, bool *res_chg) +static int vdec_h264_slice_single_decode_ex(void *h_vdec, struct mtk_vcode= c_mem *bs, + struct vdec_fb *unused, bool *res_chg) { struct vdec_h264_slice_inst *inst =3D h_vdec; struct vdec_vpu_inst *vpu =3D &inst->vpu; struct mtk_video_dec_buf *src_buf_info, *dst_buf_info; struct vdec_fb *fb; - unsigned char *buf; unsigned int data[2], i; u64 y_fb_dma, c_fb_dma; struct mtk_vcodec_mem *mem; - int err, nal_start_idx; + int err; =20 /* bs NULL means flush decoder */ if (!bs) @@ -735,6 +1028,96 @@ static int vdec_h264_slice_single_decode(void *h_vdec= , struct mtk_vcodec_mem *bs mtk_vdec_debug(inst->ctx, "[h264-dec] [%d] y_dma=3D%llx c_dma=3D%llx", inst->ctx->decoded_frame_cnt, y_fb_dma, c_fb_dma); =20 + inst->vsi_ctx_ex.bs.dma_addr =3D (u64)bs->dma_addr; + inst->vsi_ctx_ex.bs.size =3D bs->size; + inst->vsi_ctx_ex.fb.y.dma_addr =3D y_fb_dma; + inst->vsi_ctx_ex.fb.c.dma_addr =3D c_fb_dma; + inst->vsi_ctx_ex.dec.vdec_fb_va =3D (u64)(uintptr_t)fb; + + v4l2_m2m_buf_copy_metadata(&src_buf_info->m2m_buf.vb, + &dst_buf_info->m2m_buf.vb, true); + err =3D get_vdec_sig_decode_parameters(inst); + if (err) + goto err_free_fb_out; + + memcpy(&inst->vsi_ctx_ex.h264_slice_params, &inst->h264_slice_param, + sizeof(inst->vsi_ctx_ex.h264_slice_params)); + + *res_chg =3D inst->resolution_changed; + if (inst->resolution_changed) { + mtk_vdec_debug(inst->ctx, "- resolution changed -"); + if (inst->realloc_mv_buf) { + err =3D vdec_h264_slice_alloc_mv_buf(inst, &inst->ctx->picinfo); + inst->realloc_mv_buf =3D false; + if (err) + goto err_free_fb_out; + } + inst->resolution_changed =3D false; + + for (i =3D 0; i < H264_MAX_MV_NUM; i++) { + mem =3D &inst->mv_buf[i]; + inst->vsi_ctx_ex.mv_buf_dma[i].dma_addr =3D mem->dma_addr; + } + } + + memcpy(inst->vpu.vsi, &inst->vsi_ctx_ex, sizeof(inst->vsi_ctx_ex)); + err =3D vpu_dec_start(vpu, data, 2); + if (err) + goto err_free_fb_out; + + /* wait decoder done interrupt */ + err =3D mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED, + WAIT_INTR_TIMEOUT_MS, MTK_VDEC_CORE); + if (err) + mtk_vdec_err(inst->ctx, "decode timeout: pic_%d", inst->ctx->decoded_fra= me_cnt); + + inst->vsi_ex->dec.timeout =3D !!err; + err =3D vpu_dec_end(vpu); + if (err) + goto err_free_fb_out; + + memcpy(&inst->vsi_ctx_ex, inst->vpu.vsi, sizeof(inst->vsi_ctx_ex)); + mtk_vdec_debug(inst->ctx, "pic[%d] crc: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%= x 0x%x", + inst->ctx->decoded_frame_cnt, + inst->vsi_ctx_ex.dec.crc[0], inst->vsi_ctx_ex.dec.crc[1], + inst->vsi_ctx_ex.dec.crc[2], inst->vsi_ctx_ex.dec.crc[3], + inst->vsi_ctx_ex.dec.crc[4], inst->vsi_ctx_ex.dec.crc[5], + inst->vsi_ctx_ex.dec.crc[6], inst->vsi_ctx_ex.dec.crc[7]); + + inst->ctx->decoded_frame_cnt++; + return 0; + +err_free_fb_out: + mtk_vdec_err(inst->ctx, "dec frame number: %d err: %d", inst->ctx->decode= d_frame_cnt, err); + return err; +} + +static int vdec_h264_slice_single_decode(void *h_vdec, struct mtk_vcodec_m= em *bs, + struct vdec_fb *unused, bool *res_chg) +{ + struct vdec_h264_slice_inst *inst =3D h_vdec; + struct vdec_vpu_inst *vpu =3D &inst->vpu; + struct mtk_video_dec_buf *src_buf_info, *dst_buf_info; + struct vdec_fb *fb; + unsigned char *buf; + unsigned int data[2], i; + u64 y_fb_dma, c_fb_dma; + struct mtk_vcodec_mem *mem; + int err, nal_start_idx; + + /* bs NULL means flush decoder */ + if (!bs) + return vpu_dec_reset(vpu); + + fb =3D inst->ctx->dev->vdec_pdata->get_cap_buffer(inst->ctx); + src_buf_info =3D container_of(bs, struct mtk_video_dec_buf, bs_buffer); + dst_buf_info =3D container_of(fb, struct mtk_video_dec_buf, frame_buffer); + + y_fb_dma =3D fb ? (u64)fb->base_y.dma_addr : 0; + c_fb_dma =3D fb ? (u64)fb->base_c.dma_addr : 0; + mtk_vdec_debug(inst->ctx, "[h264-dec] [%d] y_dma=3D%llx c_dma=3D%llx", + inst->ctx->decoded_frame_cnt, y_fb_dma, c_fb_dma); + inst->vsi_ctx.dec.bs_buf_addr =3D (u64)bs->dma_addr; inst->vsi_ctx.dec.bs_buf_size =3D bs->size; inst->vsi_ctx.dec.y_fb_dma =3D y_fb_dma; @@ -807,21 +1190,95 @@ static int vdec_h264_slice_single_decode(void *h_vde= c, struct mtk_vcodec_mem *bs return err; } =20 +static int vdec_h264_slice_init(struct mtk_vcodec_dec_ctx *ctx) +{ + struct vdec_h264_slice_inst *inst; + int err, vsi_size; + unsigned char *temp; + + inst =3D kzalloc(sizeof(*inst), GFP_KERNEL); + if (!inst) + return -ENOMEM; + + inst->ctx =3D ctx; + + inst->vpu.id =3D SCP_IPI_VDEC_LAT; + inst->vpu.core_id =3D SCP_IPI_VDEC_CORE; + inst->vpu.ctx =3D ctx; + inst->vpu.codec_type =3D ctx->current_codec; + inst->vpu.capture_type =3D ctx->capture_fourcc; + + err =3D vpu_dec_init(&inst->vpu); + if (err) { + mtk_vdec_err(ctx, "vdec_h264 init err=3D%d", err); + goto error_free_inst; + } + + if (IS_VDEC_SUPPORT_EX(ctx->dev->dec_capability)) { + vsi_size =3D sizeof(struct vdec_h264_slice_vsi_ex); + + vsi_size =3D round_up(vsi_size, VCODEC_DEC_ALIGNED_64); + inst->vsi_ex =3D inst->vpu.vsi; + temp =3D (unsigned char *)inst->vsi_ex; + inst->vsi_core_ex =3D (struct vdec_h264_slice_vsi_ex *)(temp + vsi_size); + + if (inst->ctx->dev->vdec_pdata->hw_arch =3D=3D MTK_VDEC_PURE_SINGLE_CORE) + inst->decode =3D vdec_h264_slice_single_decode_ex; + else + inst->decode =3D vdec_h264_slice_lat_decode_ex; + } else { + vsi_size =3D sizeof(struct vdec_h264_slice_vsi); + + vsi_size =3D round_up(vsi_size, VCODEC_DEC_ALIGNED_64); + inst->vsi =3D inst->vpu.vsi; + temp =3D (unsigned char *)inst->vsi; + inst->vsi_core =3D (struct vdec_h264_slice_vsi *)(temp + vsi_size); + + if (inst->ctx->dev->vdec_pdata->hw_arch =3D=3D MTK_VDEC_PURE_SINGLE_CORE) + inst->decode =3D vdec_h264_slice_single_decode; + else + inst->decode =3D vdec_h264_slice_lat_decode; + } + inst->resolution_changed =3D true; + inst->realloc_mv_buf =3D true; + + mtk_vdec_debug(ctx, "lat struct size =3D %d,%d,%d,%d vsi: %d\n", + (int)sizeof(struct mtk_h264_sps_param), + (int)sizeof(struct mtk_h264_pps_param), + (int)sizeof(struct vdec_h264_slice_lat_dec_param), + (int)sizeof(struct mtk_h264_dpb_info), + vsi_size); + mtk_vdec_debug(ctx, "lat H264 instance >> %p, codec_type =3D 0x%x", + inst, inst->vpu.codec_type); + + ctx->drv_handle =3D inst; + return 0; + +error_free_inst: + kfree(inst); + return err; +} + +static void vdec_h264_slice_deinit(void *h_vdec) +{ + struct vdec_h264_slice_inst *inst =3D h_vdec; + + vpu_dec_deinit(&inst->vpu); + vdec_h264_slice_free_mv_buf(inst); + vdec_msg_queue_deinit(&inst->ctx->msg_queue, inst->ctx); + + kfree(inst); +} + static int vdec_h264_slice_decode(void *h_vdec, struct mtk_vcodec_mem *bs, struct vdec_fb *unused, bool *res_chg) { struct vdec_h264_slice_inst *inst =3D h_vdec; - int ret; =20 if (!h_vdec) return -EINVAL; =20 - if (inst->ctx->dev->vdec_pdata->hw_arch =3D=3D MTK_VDEC_PURE_SINGLE_CORE) - ret =3D vdec_h264_slice_single_decode(h_vdec, bs, unused, res_chg); - else - ret =3D vdec_h264_slice_lat_decode(h_vdec, bs, unused, res_chg); - - return ret; + return inst->decode(h_vdec, bs, unused, res_chg); } =20 static int vdec_h264_slice_get_param(void *h_vdec, enum vdec_get_param_typ= e type, --=20 2.46.0 From nobody Fri Nov 22 10:20:47 2024 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FA8F339AB; Sat, 16 Nov 2024 03:16:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731726994; cv=none; b=QwY1yk9fwa/IvECjQCLKMdEeluPlcqTakublLAbkxUuLSduQfm8lBg4g4p9uLksfGcoWAHVGSsKzM4Xk40MeLHiQoybRx9e2h0NDjToH/RAclTU4QDUpeUqYKm2FgUpZcfI2Zw0zrw48ISJNLTTbokDmC3fsVNtg4jtyr3vhTzc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731726994; c=relaxed/simple; bh=WDof65vLZPwrJ5o0RS7IojnmTrfQZQla3Ax9q5oxi3Y=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QFcSt1GvtxB9QtzAQitHjEtaNgviNN1+7cSTIUAZVFnhjjNMkC8AdZFLiF5w1sCP4XahEN3ti96DMtMVkBCU7PyHbbcjb2TrHk5oayiV/CdZff/0to+EUo+50D8q2ozIQZ0lonGuGLBZYbRg7w3E6Nq8pMA7T7HSQ17zFwIfPqQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=DKZNTauj; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="DKZNTauj" X-UUID: 2847a15ea3c911efbd192953cf12861f-20241116 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=nUUtronK2tOKVzyDfxFKwurj9xQ03TFrWa6ZOex8Ssg=; b=DKZNTauj2qtMGWlrxPVzNo/4tVn28XV4Vh2zJecALY6dxleelDM/IEcMUCGDPIzBj8/Xbm9f9phSd2KDYc1n9/pvGNGmotLpS2wVaMfvKwrk5tYOXWyQ4FTb616hMp3P11ZjFXRJ86h0uEmmuj//yProyDGhLMpQvf6gF1OZA4Y=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.43,REQID:3d3d35ed-5dab-41b0-8015-eb4163370401,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:ce19b8a,CLOUDID:9debb85c-f18b-4d56-b49c-93279ee09144,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0,EDM:-3,IP :nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0, LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 2847a15ea3c911efbd192953cf12861f-20241116 Received: from mtkmbs09n2.mediatek.inc [(172.21.101.94)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 593688281; Sat, 16 Nov 2024 11:16:23 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Sat, 16 Nov 2024 11:16:21 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Sat, 16 Nov 2024 11:16:20 +0800 From: Yunfei Dong To: =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= , Sebastian Fricke , Nicolas Dufresne , Hans Verkuil , AngeloGioacchino Del Regno , Benjamin Gaignard , Nathan Hebert , Daniel Almeida CC: Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , Steve Cho , "Yunfei Dong" , , , , , , Subject: [PATCH v6 3/3] media: mediatek: vcodec: add description for vsi struct Date: Sat, 16 Nov 2024 11:16:12 +0800 Message-ID: <20241116031616.15656-4-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20241116031616.15656-1-yunfei.dong@mediatek.com> References: <20241116031616.15656-1-yunfei.dong@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--5.545300-8.000000 X-TMASE-MatchedRID: QzgX5l08Brj4Q348LKfXODTV/B1Uu+XCIfZjRfGTydh30F1387KCPeFC 6BP4FUP+sHCh+gSvrNHxHXxxAO/d2TAo/rUTivG7ntCoZKs0mGVWOQQSa4vbHYrop5D7tDibo8W MkQWv6iUoTQl7wNH8Po2j49Ftap9EOwBXM346/+xg/+avkj9YHpxolbzzbs7jxv3fBrcyQljxpG XdoEJuf4ArO0ccm6/s X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--5.545300-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 2AED127212B07905FEECADE221F0410C89323E36A5ECA0D45753A2C32047CE352000:8 X-MTK: N Content-Type: text/plain; charset="utf-8" If the video shared information (vsi) is changed accidentally, will leading to play h264 bitstream fail if the firmware won't be changed at the same time. Marking the shared struct with "shared interface with firmware". Signed-off-by: Yunfei Dong Reviewed-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- .../mediatek/vcodec/decoder/vdec/vdec_h264_req_multi_if.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_= req_multi_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h= 264_req_multi_if.c index a7de95b9a7c0..5a202691e209 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_mul= ti_if.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_h264_req_mul= ti_if.c @@ -30,6 +30,7 @@ enum vdec_h264_core_dec_err_type { =20 /** * struct vdec_h264_slice_lat_dec_param - parameters for decode current f= rame + * (shared interface with firmware) * * @sps: h264 sps syntax parameters * @pps: h264 pps syntax parameters @@ -48,7 +49,7 @@ struct vdec_h264_slice_lat_dec_param { }; =20 /** - * struct vdec_h264_slice_info - decode information + * struct vdec_h264_slice_info - decode information (shared interface with= firmware) * * @nal_info: nal info of current picture * @timeout: Decode timeout: 1 timeout, 0 no timeout @@ -72,7 +73,7 @@ struct vdec_h264_slice_info { =20 /** * struct vdec_h264_slice_vsi - shared memory for decode information excha= nge - * between SCP and Host. + * between SCP and Host (shared interface with firmware). * * @wdma_err_addr: wdma error dma address * @wdma_start_addr: wdma start dma address --=20 2.46.0