From nobody Fri Nov 22 20:41:53 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 797032F2D; Sat, 16 Nov 2024 18:22:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731781371; cv=none; b=WXeXVfJmVqnk9uo9WBMdhsD5/IDxhftITCnG9oAuDD6ycJZnCwtqRB4bzgCu0DeaVmqfs5+0XrXUhmvPDQfh/RrQGlwB0kKiRPhGHDp/KRCvDM1C9fFCzKmBMIs37Requzh7LqHAgbPTalMobnBH68wueTQlfvb0dUcXMV/D8fc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731781371; c=relaxed/simple; bh=LM9pPGTp7aEnr4m+OjZM6CvE5/x0hk9Hpk+Ltg9gsoA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=c564g7X2DbuulMMMf2/8e+UWOWewtvxc28QsOgHpbC3hh+tEHXMtRdFCHLzk2bNAI51SIcglj0xiu0GDuslt0U2CXLt5z38Qd9YL6rLS7PPJ1tXMEiMrvrZJyAwhG3zcPwBLgbwwtYmR6MUKA6zycg76i97ThqQkOaJNj6Lc9RY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=THAD5DlD; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="THAD5DlD" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1731781362; bh=LM9pPGTp7aEnr4m+OjZM6CvE5/x0hk9Hpk+Ltg9gsoA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=THAD5DlDfMEE4ka+eb1K53htNf0/75tr6CJobRdrV0z9lwIZUM3bob9PdEL6rA836 T/BfujG+lglncPzIFhG1tv3kKrrNobc5KTbSHWFyY4K67Ov09Am6iPdNlfgJcWLskd zIHBySIkxCa0ZmeS+Q0aT9CKZ5IAtK9IAsuqaL9jObN1b0vneKMl48a5bQXFpsWHN0 t/VIYkVZrzgHpJ0n046i23OjCtxgHeZPrrrcQjTGyFoQghtSbg2EJHx2iS47DqJfxY V90Y1SiacyMzJ0OupDYxxJ4nxhe3iUV9KX+Bu+NxDbJ1nd+g2Z79qCkEvz9w8JMqTx joqoJZBftbP7A== Received: from localhost (unknown [86.120.21.57]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 5121A17E3778; Sat, 16 Nov 2024 19:22:42 +0100 (CET) From: Cristian Ciocaltea Date: Sat, 16 Nov 2024 20:22:32 +0200 Subject: [PATCH 1/5] dt-bindings: display: vop2: Add optional PLL clock properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241116-vop2-hdmi0-disp-modes-v1-1-2bca51db4898@collabora.com> References: <20241116-vop2-hdmi0-disp-modes-v1-0-2bca51db4898@collabora.com> In-Reply-To: <20241116-vop2-hdmi0-disp-modes-v1-0-2bca51db4898@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 On RK3588, HDMI PHY PLL can be used as an alternative and more accurate pixel clock source for VOP2 video ports 0, 1 and 2. Document the optional PLL clock properties corresponding to the two HDMI PHYs available on the SoC. Signed-off-by: Cristian Ciocaltea Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml | 4 = ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vo= p2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.= yaml index 2531726af306bd388c00c3c0a1785b2c7367e2bd..46d956e63338e196361483a668f= bf5597ebce24f 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml @@ -53,6 +53,8 @@ properties: - description: Pixel clock for video port 2. - description: Pixel clock for video port 3. - description: Peripheral(vop grf/dsi) clock. + - description: Alternative pixel clock provided by HDMI0 PHY PLL. + - description: Alternative pixel clock provided by HDMI1 PHY PLL. =20 clock-names: minItems: 5 @@ -64,6 +66,8 @@ properties: - const: dclk_vp2 - const: dclk_vp3 - const: pclk_vop + - const: pll_hdmiphy0 + - const: pll_hdmiphy1 =20 rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle --=20 2.47.0