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Sat, 16 Nov 2024 01:37:56 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AG1btlF010341 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 16 Nov 2024 01:37:55 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 15 Nov 2024 17:37:48 -0800 From: Krishna chaitanya chundru Date: Sat, 16 Nov 2024 07:07:31 +0530 Subject: [PATCH 2/4] PCI: of: Add API to retrieve equalization presets from device tree Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241116-presets-v1-2-878a837a4fee@quicinc.com> References: <20241116-presets-v1-0-878a837a4fee@quicinc.com> In-Reply-To: <20241116-presets-v1-0-878a837a4fee@quicinc.com> To: , , , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , "Manivannan Sadhasivam" , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= CC: , , , , "Krishna chaitanya chundru" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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As per PCIe spec 6.0.1 revision section 8.3.3.3 & 4.2.4 for data rates of 8.0 GT/s, 16.0 GT/s, 32.0 GT/s, and 64.0 GT/s, there is a way to configure lane equalization presets for each lane to enhance the PCIe link reliability. Each preset value represents a different combination of pre-shoot and de-emphasis values. For each data rate, different registers are defined: for 8.0 GT/s, registers are defined in section 7.7.3.4; for 16.0 GT/s, in section 7.7.5.9, etc. The 8.0 GT/s rate has an extra receiver preset hint, requiring 16 bits per lane, while the remaining data rates use 8 bits per lane. Based on the number of lanes and the supported data rate, this function reads the device tree property and stores in the presets structure. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/of.c | 62 +++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ drivers/pci/pci.h | 17 +++++++++++++-- 2 files changed, 77 insertions(+), 2 deletions(-) diff --git a/drivers/pci/of.c b/drivers/pci/of.c index dacea3fc5128..0d37bc231956 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -826,3 +826,65 @@ u32 of_pci_get_slot_power_limit(struct device_node *no= de, return slot_power_limit_mw; } EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit); + +int of_pci_get_equalization_presets(struct device *dev, + struct pci_eq_presets *presets, + int num_lanes) +{ + int ret; + + if (of_property_present(dev->of_node, "eq-presets-8gts")) { + presets->eq_presets_8gts =3D devm_kzalloc(dev, sizeof(u16) * num_lanes, = GFP_KERNEL); + if (!presets->eq_presets_8gts) + return -ENOMEM; + + ret =3D of_property_read_u16_array(dev->of_node, "eq-presets-8gts", + presets->eq_presets_8gts, num_lanes); + if (ret) { + dev_err(dev, "Error reading eq-presets-8gts %d\n", ret); + return ret; + } + } + + if (of_property_present(dev->of_node, "eq-presets-16gts")) { + presets->eq_presets_16gts =3D devm_kzalloc(dev, sizeof(u8) * num_lanes, = GFP_KERNEL); + if (!presets->eq_presets_16gts) + return -ENOMEM; + + ret =3D of_property_read_u8_array(dev->of_node, "eq-presets-16gts", + presets->eq_presets_16gts, num_lanes); + if (ret) { + dev_err(dev, "Error reading eq-presets-16gts %d\n", ret); + return ret; + } + } + + if (of_property_present(dev->of_node, "eq-presets-32gts")) { + presets->eq_presets_32gts =3D devm_kzalloc(dev, sizeof(u8) * num_lanes, = GFP_KERNEL); + if (!presets->eq_presets_32gts) + return -ENOMEM; + + ret =3D of_property_read_u8_array(dev->of_node, "eq-presets-32gts", + presets->eq_presets_32gts, num_lanes); + if (ret) { + dev_err(dev, "Error reading eq-presets-32gts %d\n", ret); + return ret; + } + } + + if (of_property_present(dev->of_node, "eq-presets-64gts")) { + presets->eq_presets_64gts =3D devm_kzalloc(dev, sizeof(u8) * num_lanes, = GFP_KERNEL); + if (!presets->eq_presets_64gts) + return -ENOMEM; + + ret =3D of_property_read_u8_array(dev->of_node, "eq-presets-64gts", + presets->eq_presets_64gts, num_lanes); + if (ret) { + dev_err(dev, "Error reading eq-presets-64gts %d\n", ret); + return ret; + } + } + + return 0; +} +EXPORT_SYMBOL_GPL(of_pci_get_equalization_presets); diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 14d00ce45bfa..757872f0cc35 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -731,7 +731,12 @@ static inline u64 pci_rebar_size_to_bytes(int size) } =20 struct device_node; - +struct pci_eq_presets { + u16 *eq_presets_8gts; + u8 *eq_presets_16gts; + u8 *eq_presets_32gts; + u8 *eq_presets_64gts; +}; #ifdef CONFIG_OF int of_pci_parse_bus_range(struct device_node *node, struct resource *res); int of_get_pci_domain_nr(struct device_node *node); @@ -746,7 +751,9 @@ void pci_set_bus_of_node(struct pci_bus *bus); void pci_release_bus_of_node(struct pci_bus *bus); =20 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *br= idge); - +int of_pci_get_equalization_presets(struct device *dev, + struct pci_eq_presets *presets, + int num_lanes); #else static inline int of_pci_parse_bus_range(struct device_node *node, struct resource *res) @@ -793,6 +800,12 @@ static inline int devm_of_pci_bridge_init(struct devic= e *dev, struct pci_host_br return 0; } =20 +static int of_pci_get_equalization_presets(struct device *dev, + struct pci_eq_presets *presets, + int num_lanes) +{ + return 0; +} #endif /* CONFIG_OF */ =20 struct of_changeset; --=20 2.34.1