From nobody Fri Nov 22 10:42:12 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 490AB19066D; Sat, 16 Nov 2024 01:38:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731721082; cv=none; b=Zo7Ov3FmTkYaWX67gs0NKT+0vBLu+8D2IGIeVlf1WEq6G8x2P1/IQ11/mVC5BBU48LOpM5U0nFwnpUK8FQWy8ULG4WuntwSgoIxhINYmGcU+w+3yv2eeHCw/glTbpP8qFwAiplogXx6d/eeTREWwWoB+gEsM3xFlLzTf6PIuipc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731721082; c=relaxed/simple; bh=pwZvnyv6qDCbpznbV8W3dD3o92sRzf62XzQBwDrGy+s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Sq68tdPzoO8r+3ylXsdTA3grmXPULKdTOyc0/H4bfbAo1rZ2A4D4CdkIIZ6eE4P+isszCCHBVfrqfJL02VK6OFFhpPRb2Iv6hvE43X0Zm/xk9Y+BrRBdmVdMD7CL9y5Xv48XoxS5KMW/WtPi1bHjSUAaHP25XE0e+zBo2RayTao= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=hWRoc7AA; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="hWRoc7AA" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4AFBmlrR014249; Sat, 16 Nov 2024 01:37:51 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= up93JY/54vUH41AYL6hMWDNcD057lk+BWeQKbhHzAl4=; b=hWRoc7AA6R5ioX+W qJqkRa9jerx7uHcgZ6nxznmAswsmZSaLDZNtFKoAae6qsZPN3sXVcYsAf+FGGIBF CVUoV8PcCo053dEyVOTg1xclukwqHsgafq06j7p1zXlCQRBcLNOqfnvCroUDv+wv mB5cPWfjS7j9KZ685wHCcVfZsJ077igmRUhHWt3v2qZZnN9xd4a5IrTVj3l4rt3h uNJBKUNTSnTnWD3glw2MzK7MKYlUzE2FcBN4EJzf+AlECAZN4PE0XjQLPIf1Icz8 IqlCcfUxA03tnrnsLVBm+hj7c286RIPOiFijyqsBqGynpoa+PUtsXZrbKIwPjWDi P354fg== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42wwddb8b3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 16 Nov 2024 01:37:50 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AG1bouV022885 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 16 Nov 2024 01:37:50 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 15 Nov 2024 17:37:43 -0800 From: Krishna chaitanya chundru Date: Sat, 16 Nov 2024 07:07:30 +0530 Subject: [PATCH 1/4] arm64: dts: qcom: x1e80100: Add PCIe lane equalization preset properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241116-presets-v1-1-878a837a4fee@quicinc.com> References: <20241116-presets-v1-0-878a837a4fee@quicinc.com> In-Reply-To: <20241116-presets-v1-0-878a837a4fee@quicinc.com> To: , , , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , "Manivannan Sadhasivam" , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= CC: , , , , "Krishna chaitanya chundru" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1731721058; l=1230; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=pwZvnyv6qDCbpznbV8W3dD3o92sRzf62XzQBwDrGy+s=; b=hTI2C00fhl3jD2Sgr/J0YQFzKPeHlIYaADTKl2A2Ot85f1Tm8Zwh2JX8NwSxyczP5HwstJ1iz uDXh55bf+s4AIm6fnhk7G4f2+J384avggN7+8lTcPGpFxGorer1GxQ6 X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: OavDK87WgCuZo4qhvNWOIpY8xIhc8ktc X-Proofpoint-ORIG-GUID: OavDK87WgCuZo4qhvNWOIpY8xIhc8ktc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=732 mlxscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 phishscore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411160011 Add PCIe lane equalization preset properties for 8 GT/s and 16 GT/s data rates used in lane equalization procedure. Signed-off-by: Krishna chaitanya chundru --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index a36076e3c56b..6a2074297030 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2993,6 +2993,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys =3D <&pcie6a_phy>; phy-names =3D "pciephy"; =20 + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555>; + + eq-presets-16gts =3D /bits/ 8 <0x55 0x55>; + status =3D "disabled"; }; =20 @@ -3115,6 +3119,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys =3D <&pcie5_phy>; phy-names =3D "pciephy"; =20 + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555>; + status =3D "disabled"; }; =20 @@ -3235,6 +3241,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys =3D <&pcie4_phy>; phy-names =3D "pciephy"; =20 + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555>; + status =3D "disabled"; =20 pcie4_port0: pcie@0 { --=20 2.34.1 From nobody Fri Nov 22 10:42:12 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E52019066D; Sat, 16 Nov 2024 01:38:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731721087; cv=none; b=sh8R8HjmnHa9+79Agz2u7iyPDy+ZtXgeencN1vUj5XKT3s0bfwU+a3CpQZNGkO3zpVUUOlQMZZEHcJIxZiof9iLng5pGEL80UVyxoq6bUZUSbJTdiDmrZ8O4xRr79Lf7Y2/uDHLe1OS5YooVrr8tLi5GmsgV8w3YfFqci4mUKME= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731721087; c=relaxed/simple; bh=We7+mnLDPHlJfTjNDEFiooxDEJCUNFlOZ8XnnWervXg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=f7T8w9JWhuv3gsra/HvpnnlQkE7Yzzd0Tgyo4folfaOvKVikOjeR1ptaUAt3/ZHAnMBVy36TkJkvsf5y66Sfk4iil/I626qqsGM2NweHeGutRSSOSSGKiq7P069pu5BJ0IW2N0AoK1653xovomLGsAZlvxBcyQtxGKo1mFwGVb8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=kB6XNqMM; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="kB6XNqMM" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4AFI5SSV029678; Sat, 16 Nov 2024 01:37:57 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= vuTudi5/3YYxGx4jpAauoXilRSBGft4yh6bEdurqNtI=; b=kB6XNqMMgUsNwkzl yaWn7xsYQ9m1mI0fuc4zYKhS9CGbAHWT0kSFewEJwjd+m12CSqJd5GoCTY5CRPoM bJcqXRFemnp+QMnYWVdLgAHEO2FoUwI7p2UU9PA/FgFf8E89Mm9cc4gI78a4RqJE pDRqa7aiTsvLNu12hMYYCZ0HTIqH/Vczl3QtfmWxDKG2uFszZ5oYtLCQIVliI4Th YFV3zmeENYMQF8LsZoFs1rLC5FVkvrrXAfn9HtVxvnx757GemWRqTs2Cbc3ZAORj e+2juygz9nX5F4VMG6lxJMaza8DbHzlErsopWKW6erEG56d6Dv8aWhgtwcQ99ZRj E3LvCA== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42wjqan2y6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 16 Nov 2024 01:37:56 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AG1btlF010341 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 16 Nov 2024 01:37:55 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 15 Nov 2024 17:37:48 -0800 From: Krishna chaitanya chundru Date: Sat, 16 Nov 2024 07:07:31 +0530 Subject: [PATCH 2/4] PCI: of: Add API to retrieve equalization presets from device tree Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241116-presets-v1-2-878a837a4fee@quicinc.com> References: <20241116-presets-v1-0-878a837a4fee@quicinc.com> In-Reply-To: <20241116-presets-v1-0-878a837a4fee@quicinc.com> To: , , , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , "Manivannan Sadhasivam" , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= CC: , , , , "Krishna chaitanya chundru" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1731721058; l=4750; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=We7+mnLDPHlJfTjNDEFiooxDEJCUNFlOZ8XnnWervXg=; b=vwECHnCTXdvKttpyLRS3rsVUwRQDyhMaj96flJPS9ZHogUtD5GkGIEdKQc7XYuwMiCz4McIhs 8u0Dt1QDeBPDS788kNjcS4Yo3AzjvO7gdPY9kIs36ZhfH6ydr1Xk2Om X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: jWebHggDihbxmAY-0Efwn5gNMWI8AuW5 X-Proofpoint-ORIG-GUID: jWebHggDihbxmAY-0Efwn5gNMWI8AuW5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 mlxscore=0 mlxlogscore=999 bulkscore=0 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411160011 PCIe equalization presets are predefined settings used to optimize signal integrity by compensating for signal loss and distortion in high-speed data transmission. As per PCIe spec 6.0.1 revision section 8.3.3.3 & 4.2.4 for data rates of 8.0 GT/s, 16.0 GT/s, 32.0 GT/s, and 64.0 GT/s, there is a way to configure lane equalization presets for each lane to enhance the PCIe link reliability. Each preset value represents a different combination of pre-shoot and de-emphasis values. For each data rate, different registers are defined: for 8.0 GT/s, registers are defined in section 7.7.3.4; for 16.0 GT/s, in section 7.7.5.9, etc. The 8.0 GT/s rate has an extra receiver preset hint, requiring 16 bits per lane, while the remaining data rates use 8 bits per lane. Based on the number of lanes and the supported data rate, this function reads the device tree property and stores in the presets structure. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/of.c | 62 +++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ drivers/pci/pci.h | 17 +++++++++++++-- 2 files changed, 77 insertions(+), 2 deletions(-) diff --git a/drivers/pci/of.c b/drivers/pci/of.c index dacea3fc5128..0d37bc231956 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -826,3 +826,65 @@ u32 of_pci_get_slot_power_limit(struct device_node *no= de, return slot_power_limit_mw; } EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit); + +int of_pci_get_equalization_presets(struct device *dev, + struct pci_eq_presets *presets, + int num_lanes) +{ + int ret; + + if (of_property_present(dev->of_node, "eq-presets-8gts")) { + presets->eq_presets_8gts =3D devm_kzalloc(dev, sizeof(u16) * num_lanes, = GFP_KERNEL); + if (!presets->eq_presets_8gts) + return -ENOMEM; + + ret =3D of_property_read_u16_array(dev->of_node, "eq-presets-8gts", + presets->eq_presets_8gts, num_lanes); + if (ret) { + dev_err(dev, "Error reading eq-presets-8gts %d\n", ret); + return ret; + } + } + + if (of_property_present(dev->of_node, "eq-presets-16gts")) { + presets->eq_presets_16gts =3D devm_kzalloc(dev, sizeof(u8) * num_lanes, = GFP_KERNEL); + if (!presets->eq_presets_16gts) + return -ENOMEM; + + ret =3D of_property_read_u8_array(dev->of_node, "eq-presets-16gts", + presets->eq_presets_16gts, num_lanes); + if (ret) { + dev_err(dev, "Error reading eq-presets-16gts %d\n", ret); + return ret; + } + } + + if (of_property_present(dev->of_node, "eq-presets-32gts")) { + presets->eq_presets_32gts =3D devm_kzalloc(dev, sizeof(u8) * num_lanes, = GFP_KERNEL); + if (!presets->eq_presets_32gts) + return -ENOMEM; + + ret =3D of_property_read_u8_array(dev->of_node, "eq-presets-32gts", + presets->eq_presets_32gts, num_lanes); + if (ret) { + dev_err(dev, "Error reading eq-presets-32gts %d\n", ret); + return ret; + } + } + + if (of_property_present(dev->of_node, "eq-presets-64gts")) { + presets->eq_presets_64gts =3D devm_kzalloc(dev, sizeof(u8) * num_lanes, = GFP_KERNEL); + if (!presets->eq_presets_64gts) + return -ENOMEM; + + ret =3D of_property_read_u8_array(dev->of_node, "eq-presets-64gts", + presets->eq_presets_64gts, num_lanes); + if (ret) { + dev_err(dev, "Error reading eq-presets-64gts %d\n", ret); + return ret; + } + } + + return 0; +} +EXPORT_SYMBOL_GPL(of_pci_get_equalization_presets); diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 14d00ce45bfa..757872f0cc35 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -731,7 +731,12 @@ static inline u64 pci_rebar_size_to_bytes(int size) } =20 struct device_node; - +struct pci_eq_presets { + u16 *eq_presets_8gts; + u8 *eq_presets_16gts; + u8 *eq_presets_32gts; + u8 *eq_presets_64gts; +}; #ifdef CONFIG_OF int of_pci_parse_bus_range(struct device_node *node, struct resource *res); int of_get_pci_domain_nr(struct device_node *node); @@ -746,7 +751,9 @@ void pci_set_bus_of_node(struct pci_bus *bus); void pci_release_bus_of_node(struct pci_bus *bus); =20 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *br= idge); - +int of_pci_get_equalization_presets(struct device *dev, + struct pci_eq_presets *presets, + int num_lanes); #else static inline int of_pci_parse_bus_range(struct device_node *node, struct resource *res) @@ -793,6 +800,12 @@ static inline int devm_of_pci_bridge_init(struct devic= e *dev, struct pci_host_br return 0; } =20 +static int of_pci_get_equalization_presets(struct device *dev, + struct pci_eq_presets *presets, + int num_lanes) +{ + return 0; +} #endif /* CONFIG_OF */ =20 struct of_changeset; --=20 2.34.1 From nobody Fri Nov 22 10:42:12 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 841D1192B88; Sat, 16 Nov 2024 01:38:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731721091; cv=none; b=X7hymAbHS+NCDhSu+lJaW6m0O+SM7q1PJnjcz9c65L/LYYI+hEAw/AqeMwLQhfUyMWxWyA4ym8LOs4Mc6KR/YOkID886LXpmFB6z02rLgDDPzCSLP8gEl79OniJuFyiQE86Alb7OfdeGglvGVua8CzVijPh5/9kr2fZnMtmOXyg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731721091; c=relaxed/simple; bh=INlDbI9Z77ebEWUK4q3U5UBPWWiqwSrfQWVBSFpKZvA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=VZOpV3PzYN7xIvYOadexgkf/hCd1LGSoUixXil1uAsdrs9u5QWqPao3Sux/gblrJMhGNB2/hOGlwrbS9Og5oPUJPAl++jz51tsqs2hqw3Mj7baYzLJMRgTgCS6GJP9219EE2Tor6tDJb3VEgkHfUDOdcsm3Lhc1HyK3q0kIrQr4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=c2P7b8Hy; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="c2P7b8Hy" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4AFJYUEf023967; Sat, 16 Nov 2024 01:38:01 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 0iufXA7WJXSxa38lOaIl1kBEF/WsXCwCNtKAjO8hDSk=; b=c2P7b8HyAYpYjXIt kq6TJe3dGqyjV4aehQbe1r6IE4D693CI5o0u1KinXol1/Q+g9bkgZ9FD/I/cNW1L rLSG4kI81rviyc5GpkB/r1MoI+PKsknIpTkS6gmVxp+a1ZJTKCYij1MzyvHcw8tv Vs5cWdj5D9WeXW5ijjCCjwN+2nXcfZe7drrwStrsrxS639kAbM00qelgzA+UnthE w5HxcQcxUWB+/iKm2MW0xuNSzjrxE702jS1gtyJ1a73NFdSM97Z+nrAMu8o2RLIZ zzAVB434foP1panOQ26ISASu7rZKGSjlNkcu9Sx89Qjys+FpAMvVRHWpGqL7WzU6 9PSzRA== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42x3acj9us-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 16 Nov 2024 01:38:01 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AG1c0Vv010428 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 16 Nov 2024 01:38:00 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 15 Nov 2024 17:37:53 -0800 From: Krishna chaitanya chundru Date: Sat, 16 Nov 2024 07:07:32 +0530 Subject: [PATCH 3/4] PCI: dwc: Improve handling of PCIe lane configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241116-presets-v1-3-878a837a4fee@quicinc.com> References: <20241116-presets-v1-0-878a837a4fee@quicinc.com> In-Reply-To: <20241116-presets-v1-0-878a837a4fee@quicinc.com> To: , , , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , "Manivannan Sadhasivam" , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= CC: , , , , "Krishna chaitanya chundru" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1731721058; l=3440; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=INlDbI9Z77ebEWUK4q3U5UBPWWiqwSrfQWVBSFpKZvA=; b=imOzsGQ8DRuxXWhXeSnj04NbWjlmfhxeQEjh9G1crgi1M0igIlBr4u2TOXVQe3A+JN1uWFBri eAMzWKnCOPiCTrhh5Epm50Np6Q1O+JP8tW7RoEhEUFymzJ1hsW9RYbH X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 5yKZzfY72wIxIGR4vLBMxnfhyH6iQb6c X-Proofpoint-ORIG-GUID: 5yKZzfY72wIxIGR4vLBMxnfhyH6iQb6c X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 clxscore=1015 bulkscore=0 impostorscore=0 adultscore=0 malwarescore=0 mlxlogscore=984 lowpriorityscore=0 spamscore=0 phishscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411160011 Currently even if the number of lanes hardware supports is equal to the number lanes provided in the devicetree, the driver is trying to configure again the maximum number of lanes which is not needed. Update number of lanes only when it is not equal to hardware capability. And also if the num-lanes property is not present in the devicetree update the num_lanes with the maximum hardware supports. Introduce dw_pcie_link_get_max_link_width() to get the maximum lane width the hardware supports. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++ drivers/pci/controller/dwc/pcie-designware.c | 14 +++++++++++++- drivers/pci/controller/dwc/pcie-designware.h | 1 + 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 3e41865c7290..2cd0acbf9e18 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -504,6 +504,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) =20 dw_pcie_iatu_detect(pci); =20 + if (pci->num_lanes < 1) + pci->num_lanes =3D dw_pcie_link_get_max_link_width(pci); + /* * Allocate the resource for MSG TLP before programming the iATU * outbound window in dw_pcie_setup_rc(). Since the allocation depends diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 6d6cbc8b5b2c..acb2a963ae1a 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -736,6 +736,16 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie = *pci) =20 } =20 +int dw_pcie_link_get_max_link_width(struct dw_pcie *pci) +{ + u32 lnkcap; + u8 cap; + + cap =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + lnkcap =3D dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); + return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap); +} + static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_l= anes) { u32 lnkcap, lwsc, plc; @@ -1069,6 +1079,7 @@ void dw_pcie_edma_remove(struct dw_pcie *pci) =20 void dw_pcie_setup(struct dw_pcie *pci) { + int num_lanes =3D dw_pcie_link_get_max_link_width(pci); u32 val; =20 dw_pcie_link_set_max_speed(pci); @@ -1102,5 +1113,6 @@ void dw_pcie_setup(struct dw_pcie *pci) val |=3D PORT_LINK_DLL_LINK_EN; dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); =20 - dw_pcie_link_set_max_link_width(pci, pci->num_lanes); + if (num_lanes !=3D pci->num_lanes) + dw_pcie_link_set_max_link_width(pci, pci->num_lanes); } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 347ab74ac35a..500e793c9361 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -486,6 +486,7 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, s= ize_t size, u32 val); int dw_pcie_link_up(struct dw_pcie *pci); void dw_pcie_upconfig_setup(struct dw_pcie *pci); int dw_pcie_wait_for_link(struct dw_pcie *pci); +int dw_pcie_link_get_max_link_width(struct dw_pcie *pci); int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, const struct dw_pcie_ob_atu_cfg *atu); int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, --=20 2.34.1 From nobody Fri Nov 22 10:42:12 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D44E194096; Sat, 16 Nov 2024 01:38:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731721096; cv=none; b=ET6FgXnwwxZ6oRAOcNJ7xpu7rZqrRwBtc6J5bUNyTjoSEFJmbpEAvj7bh9q06Ru5JvD5CGhKJ8ySh0K5DQrBsbKt3eTzeAsqzOAtakXB8i07PmRIX4kXDLfEfsS8x8teDsnS02xzkRc/niuudCgwKp9MUDPle+caKrfvGi8V6eU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731721096; c=relaxed/simple; bh=8z3ERRkzjY1Ds+rRxELQ1hmtyibkEmRtY8UUbg0rG50=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=JXNOalF5wtlSychubv9HqvhFg4ZVaLqqfpDctWxgaoce/4HJbNa3uG6iEA21YXArTpPOyvNbEkJZlLisdURokRhQvMcBkW1SH/ArOODhxEKWClEFjYCA/8bEwjrQSHuT41BepsCpdzx0r1gV/fM2q/vrcflEOnxsFNgVq7TI/Wc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=YsiIcmyu; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="YsiIcmyu" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4AFBsrd5002407; Sat, 16 Nov 2024 01:38:07 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= IIC8Klt4v5fdxPicO9OA39Kj1uKHyXLclhhigzYL8Os=; b=YsiIcmyuIxmP+W2n B1mdfeJdpxxqqoW+UF7vq5d+6pySYsHJOdTWU+5dyanYfiUkZ7HNaayCbECWgNCd XeK4LGq3MKXih01VuvoQvxQPs+pFKomkDqeOaxOrX344keBWddaRl4w1kbLMWR+m cFvlV6fPdint0t2o0+5O6oV7mc4mX0xX0usE9ufFRSUsRgEyfHnU8mdTgUqwz4gc qIVMNeteEcV/Ym8lQXzEtAVwIDd1WQnKAXvOrdl07ZN3g/pJ9n4vvivHLT0CvD5w MYYyrmTLOzxypKs+iDaVCZRBuWLrOkw6C/NrpL2Gv2yrQ/T3kDAM+0W6SWbagNqr 2ipdvA== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42ww6duan2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 16 Nov 2024 01:38:06 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AG1c5nq010577 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 16 Nov 2024 01:38:05 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 15 Nov 2024 17:37:58 -0800 From: Krishna chaitanya chundru Date: Sat, 16 Nov 2024 07:07:33 +0530 Subject: [PATCH 4/4] PCI: dwc: Add support for configuring lane equalization presets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241116-presets-v1-4-878a837a4fee@quicinc.com> References: <20241116-presets-v1-0-878a837a4fee@quicinc.com> In-Reply-To: <20241116-presets-v1-0-878a837a4fee@quicinc.com> To: , , , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , "Manivannan Sadhasivam" , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= CC: , , , , "Krishna chaitanya chundru" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1731721058; l=4479; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=8z3ERRkzjY1Ds+rRxELQ1hmtyibkEmRtY8UUbg0rG50=; b=4YaiMjYOXtW8LVMtjeU+YEUrg4BJC/xt/iE9onhzvsPUYX/SDYQ7bfUUNGRrr2AClqAcTpY3k DStROwP+KAWBK87JEaz3k8VEa8RKTUlaB9KLmTtul9RPnrEmx2r8W27 X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: u1qz4OJ27PdUeMnkydVv8R8rlc6LIFvs X-Proofpoint-GUID: u1qz4OJ27PdUeMnkydVv8R8rlc6LIFvs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 phishscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 suspectscore=0 clxscore=1015 adultscore=0 mlxlogscore=999 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411160011 PCIe equalization presets are predefined settings used to optimize signal integrity by compensating for signal loss and distortion in high-speed data transmission. Based upon the number of lanes and the data rate supported, read the devicetree property and write it in to the lane equalization control registers. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 39 +++++++++++++++++++= ++++ drivers/pci/controller/dwc/pcie-designware.h | 3 ++ include/uapi/linux/pci_regs.h | 3 ++ 3 files changed, 45 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 2cd0acbf9e18..2e6abcafbd79 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -507,6 +507,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) if (pci->num_lanes < 1) pci->num_lanes =3D dw_pcie_link_get_max_link_width(pci); =20 + ret =3D of_pci_get_equalization_presets(dev, &pp->presets, pci->num_lanes= ); + if (ret) + goto err_free_msi; + /* * Allocate the resource for MSG TLP before programming the iATU * outbound window in dw_pcie_setup_rc(). Since the allocation depends @@ -802,6 +806,40 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) return 0; } =20 +static void dw_pcie_program_presets(struct dw_pcie *pci, u8 cap_id, u8 lan= e_eq_offset, + u8 lane_reg_size, u8 *presets, u8 num_lanes) +{ + u32 cap; + int i; + + cap =3D dw_pcie_find_ext_capability(pci, cap_id); + if (!cap) + return; + + /* + * Write preset values to the registers byte-by-byte for the given + * number of lanes and register size. + */ + for (i =3D 0; i < num_lanes * lane_reg_size; i++) + dw_pcie_writeb_dbi(pci, cap + lane_eq_offset + i, presets[i]); +} + +static void dw_pcie_config_presets(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + enum pci_bus_speed speed =3D pcie_link_speed[pci->max_link_speed]; + + /* For data rate of 8 GT/S each lane equalization control is 16bits wide = */ + if (speed >=3D PCIE_SPEED_8_0GT && pp->presets.eq_presets_8gts) + dw_pcie_program_presets(pci, PCI_EXT_CAP_ID_SECPCI, PCI_SECPCI_LE_CTRL, + 0x2, (u8 *)pp->presets.eq_presets_8gts, pci->num_lanes); + + /* For data rate of 16 GT/S each lane equalization control is 8bits wide = */ + if (speed >=3D PCIE_SPEED_16_0GT && pp->presets.eq_presets_16gts) + dw_pcie_program_presets(pci, PCI_EXT_CAP_ID_PL_16GT, PCI_PL_16GT_LE_CTRL, + 0x1, pp->presets.eq_presets_16gts, pci->num_lanes); +} + int dw_pcie_setup_rc(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); @@ -855,6 +893,7 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) PCI_COMMAND_MASTER | PCI_COMMAND_SERR; dw_pcie_writel_dbi(pci, PCI_COMMAND, val); =20 + dw_pcie_config_presets(pp); /* * If the platform provides its own child bus config accesses, it means * the platform uses its own address translation component rather than diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 500e793c9361..b12b33944df4 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -25,6 +25,8 @@ #include #include =20 +#include "../../pci.h" + /* DWC PCIe IP-core versions (native support since v4.70a) */ #define DW_PCIE_VER_365A 0x3336352a #define DW_PCIE_VER_460A 0x3436302a @@ -379,6 +381,7 @@ struct dw_pcie_rp { bool use_atu_msg; int msg_atu_index; struct resource *msg_res; + struct pci_eq_presets presets; }; =20 struct dw_pcie_ep_ops { diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 12323b3334a9..68fc8873bc60 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1118,6 +1118,9 @@ #define PCI_DLF_CAP 0x04 /* Capabilities Register */ #define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange= Enable */ =20 +/* Secondary PCIe Capability 8.0 GT/s */ +#define PCI_SECPCI_LE_CTRL 0x0c /* Lane Equalization Control Register */ + /* Physical Layer 16.0 GT/s */ #define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */ #define PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK 0x0000000F --=20 2.34.1