From nobody Fri Nov 22 17:23:40 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42158191F78; Fri, 15 Nov 2024 22:52:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731711127; cv=none; b=KfZ0G4By7ZmxVbYvlm2rqomtw9AC7GIL4o36PHLbUzxRqn9B5Ghz16K9Ue7JBcywbaEbOK94+h0R0u1z9w+CofM+kbkH7FQ/WgKGL6hvVytxndGABOBANhDQa2p3ebdYjFs666it/9uMudGlufn6oBpU8FCv7Z0N6k87vgGgUb8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731711127; c=relaxed/simple; bh=BT1mbRWFYmZp3485n00ha3pYZJUeChW1ZoyoGNwCC9o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JEq8Rm1WC5Qs0qjUd0zb/PLiRa5P7UAXLXzF+Oy8RSu8PLhy5Ry5lavIHikU/jg0qpqWzfCCjXuWwk72v/ASMq6ivBFTdOlMlLvQMCgGfWBzcR32+b48CSG0gq84vmaGttgORGNcqBKrJkNq0qranvvCw274gWna22cTicdx7Vk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=RoSnD5Jj; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="RoSnD5Jj" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4AFK90Dj024008; Fri, 15 Nov 2024 22:52:01 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=0+ppS/2n5Y/ any/ysRTNoS9tZD6/K9wFUWrrs8QUPiw=; b=RoSnD5JjRdcrby2zMi9K8XblpPW i45MHbQd3+2x13EOISXK1Nb1UJer0S9kBATEiAqOKuN7D74OBbGd+JxjDC/PofJl Gxi6MgfUGBNlkTZ1Ofvy3vqIg67RqiIkGweQMyvlMhYurGbH5yYFqHiVDgBA2hIF qQ4+itIalbuhcvItOLZDyDKopNG2LYrt0u3cHX+GXW1wFBAx+rFE5UY5514+VsY+ Vo9EyZoL6Ls9w/HHKkPmIlIzYEYnxXb1/nVqLW3jvSxFdm3kwidKMKZWJdV64uN1 huNy8yIjpZ4zVCNi4BLaDcJ5IONAMtaSv4tjz+I8P9g2VlnOuJ37B6viK/A== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42x3acj22k-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Nov 2024 22:52:00 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 4AFMpviM020278; Fri, 15 Nov 2024 22:51:57 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 42t0tn65dh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Nov 2024 22:51:57 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 4AFMpung020255; Fri, 15 Nov 2024 22:51:57 GMT Received: from hu-devc-hyd-u22-c.qualcomm.com (hu-wasimn-hyd.qualcomm.com [10.147.246.180]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 4AFMpuMB020245 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Nov 2024 22:51:56 +0000 Received: by hu-devc-hyd-u22-c.qualcomm.com (Postfix, from userid 3944840) id DCA375A8; Sat, 16 Nov 2024 04:21:55 +0530 (+0530) From: Wasim Nazir To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@quicinc.com, Wasim Nazir Subject: [PATCH v2 4/5] arm64: dts: qcom: Add support for QCS9075 RB8 Date: Sat, 16 Nov 2024 04:21:51 +0530 Message-ID: <20241115225152.3264396-5-quic_wasimn@quicinc.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241115225152.3264396-1-quic_wasimn@quicinc.com> References: <20241115225152.3264396-1-quic_wasimn@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: P-6bCVzz2ufIMT2mdWRbuOTjUxKPxYlL X-Proofpoint-ORIG-GUID: P-6bCVzz2ufIMT2mdWRbuOTjUxKPxYlL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 clxscore=1015 bulkscore=0 impostorscore=0 adultscore=0 malwarescore=0 mlxlogscore=999 lowpriorityscore=0 spamscore=0 phishscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411150192 Content-Type: text/plain; charset="utf-8" Add device tree support for the QCS9075-RB8 board. Basic changes are supported for boot to shell. Signed-off-by: Wasim Nazir --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/qcs9075-rb8.dts | 281 +++++++++++++++++++++++ 2 files changed, 282 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs9075-rb8.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 9bb8b191aeb5..5d9847119f2e 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -115,6 +115,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs6490-rb3gen2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8550-aim300-aiot.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D qcs9075-rb8.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs9100-ride.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs9100-ride-r3.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qdu1000-idp.dtb diff --git a/arch/arm64/boot/dts/qcom/qcs9075-rb8.dts b/arch/arm64/boot/dts= /qcom/qcs9075-rb8.dts new file mode 100644 index 000000000000..e4307ff1e2a7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs9075-rb8.dts @@ -0,0 +1,281 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ +/dts-v1/; + +#include +#include + +#include "sa8775p.dtsi" +#include "sa8775p-pmics.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. QCS9075 RB8"; + compatible =3D "qcom,qcs9075-rb8", "qcom,qcs9075", "qcom,sa8775p"; + + aliases { + serial0 =3D &uart10; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id =3D "a"; + + vreg_s4a: smps4 { + regulator-name =3D "vreg_s4a"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1816000>; + regulator-initial-mode =3D ; + }; + + vreg_s5a: smps5 { + regulator-name =3D "vreg_s5a"; + regulator-min-microvolt =3D <1850000>; + regulator-max-microvolt =3D <1996000>; + regulator-initial-mode =3D ; + }; + + vreg_s9a: smps9 { + regulator-name =3D "vreg_s9a"; + regulator-min-microvolt =3D <535000>; + regulator-max-microvolt =3D <1120000>; + regulator-initial-mode =3D ; + }; + + vreg_l4a: ldo4 { + regulator-name =3D "vreg_l4a"; + regulator-min-microvolt =3D <788000>; + regulator-max-microvolt =3D <1050000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l5a: ldo5 { + regulator-name =3D "vreg_l5a"; + regulator-min-microvolt =3D <870000>; + regulator-max-microvolt =3D <950000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6a: ldo6 { + regulator-name =3D "vreg_l6a"; + regulator-min-microvolt =3D <870000>; + regulator-max-microvolt =3D <970000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7a: ldo7 { + regulator-name =3D "vreg_l7a"; + regulator-min-microvolt =3D <720000>; + regulator-max-microvolt =3D <950000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l8a: ldo8 { + regulator-name =3D "vreg_l8a"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l9a: ldo9 { + regulator-name =3D "vreg_l9a"; + regulator-min-microvolt =3D <2970000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vreg_l1c: ldo1 { + regulator-name =3D "vreg_l1c"; + regulator-min-microvolt =3D <1140000>; + regulator-max-microvolt =3D <1260000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2c: ldo2 { + regulator-name =3D "vreg_l2c"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3c: ldo3 { + regulator-name =3D "vreg_l3c"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1300000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4c: ldo4 { + regulator-name =3D "vreg_l4c"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + /* + * FIXME: This should have regulator-allow-set-load but + * we're getting an over-current fault from the PMIC + * when switching to LPM. + */ + }; + + vreg_l5c: ldo5 { + regulator-name =3D "vreg_l5c"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1300000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6c: ldo6 { + regulator-name =3D "vreg_l6c"; + regulator-min-microvolt =3D <1620000>; + regulator-max-microvolt =3D <1980000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7c: ldo7 { + regulator-name =3D "vreg_l7c"; + regulator-min-microvolt =3D <1620000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l8c: ldo8 { + regulator-name =3D "vreg_l8c"; + regulator-min-microvolt =3D <2400000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l9c: ldo9 { + regulator-name =3D "vreg_l9c"; + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <2700000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-2 { + compatible =3D "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id =3D "e"; + + vreg_s4e: smps4 { + regulator-name =3D "vreg_s4e"; + regulator-min-microvolt =3D <970000>; + regulator-max-microvolt =3D <1520000>; + regulator-initial-mode =3D ; + }; + + vreg_s7e: smps7 { + regulator-name =3D "vreg_s7e"; + regulator-min-microvolt =3D <1010000>; + regulator-max-microvolt =3D <1170000>; + regulator-initial-mode =3D ; + }; + + vreg_s9e: smps9 { + regulator-name =3D "vreg_s9e"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <570000>; + regulator-initial-mode =3D ; + }; + + vreg_l6e: ldo6 { + regulator-name =3D "vreg_l6e"; + regulator-min-microvolt =3D <1280000>; + regulator-max-microvolt =3D <1450000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l8e: ldo8 { + regulator-name =3D "vreg_l8e"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1950000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32768>; +}; + +&tlmm { + qup_uart10_default: qup-uart10-state { + pins =3D "gpio46", "gpio47"; + function =3D "qup1_se3"; + }; +}; + +&uart10 { + compatible =3D "qcom,geni-debug-uart"; + pinctrl-0 =3D <&qup_uart10_default>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&xo_board_clk { + clock-frequency =3D <38400000>; +}; -- 2.47.0