From nobody Fri Nov 22 21:28:59 2024 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64B8E1D517F; Fri, 15 Nov 2024 16:21:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731687698; cv=none; b=t0MT0EiGu1UcwVKGMuM5/4JD1NOxDSV/g8ccJa+1qSHcZLX1PC5kMZ8ne4QUgfuLobvjBKA5dwXSH6tNiDPpm1VVqJCPrP/5UsRxCrqoT7aHDHjz/Ji/authmGCCLwuUVOzxBdmisMlB7o3wUjqjkbuhER7dBP3m92kJCqTpXps= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731687698; c=relaxed/simple; bh=t8QOMvicQTdBi3HEc3pXhANKEj297lR7+tmr8+awtJk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jJSoGtQpNsw1Qn4/fwxCMWb7paglYnWOjwKz1vcND2NDtrZd4z2tOdfgsgxU5KDmSBnx7+tPATlX44oZAw3GQWWWhxJK4yPNAhyAIkOyGo9ekbapfJe5uHgHOZMgXhJ1aHRh1zOP3lnFq3YNcC2OVAZclxp71RU4xVFakZ/pnzw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=Ggbk3HKo; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="Ggbk3HKo" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1731687689; bh=t8QOMvicQTdBi3HEc3pXhANKEj297lR7+tmr8+awtJk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ggbk3HKo6LYr9TppFbMl87GhuGstk7MN+7cbv64SY8d0AgULJiOtVrATmrzgtnB2k 790RKIi56ZKOuLQCneAhgucS8gP31bVFm73yMVUDvxzhA64B2XxvzsnpPQUQ1zfyjM rgN0gIRMgi8E4MGuANUsLsCxOtrQSbhNFc62jhmKtbnTsxyMHNAAhwLzzioCJpbBpn NixWT2W91JFLDY3XJ1llXNK3qGJlmgBgNmGpeLKjxjEZAWTwEpvAvKs1e3TbZ9MPp+ ZJlvtJDBD5IB9rFb2GYrIAR/+whOIbcaUvfQShn4NV2Y1ZIdC6Mpn6S/0xrez6ZaZb PCjFXJ3IOepKQ== Received: from bootstrap.mtl.collabora.ca (mtl.collabora.ca [66.171.169.34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: detlev) by bali.collaboradmins.com (Postfix) with ESMTPSA id AB5E817E374C; Fri, 15 Nov 2024 17:21:26 +0100 (CET) From: Detlev Casanova To: linux-kernel@vger.kernel.org Cc: Sandy Huang , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Andy Yan , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Sebastian Reichel , Dragan Simic , Alexey Charkov , Jianfeng Liu , Cristian Ciocaltea , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, kernel@collabora.com, Detlev Casanova , Conor Dooley Subject: [PATCH v4 1/3] dt-bindings: display: vop2: Add VP clock resets Date: Fri, 15 Nov 2024 11:20:40 -0500 Message-ID: <20241115162120.83990-2-detlev.casanova@collabora.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241115162120.83990-1-detlev.casanova@collabora.com> References: <20241115162120.83990-1-detlev.casanova@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the documentation for VOP2 video ports reset clocks. One reset can be set per video port. Reviewed-by: Conor Dooley Signed-off-by: Detlev Casanova --- .../display/rockchip/rockchip-vop2.yaml | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vo= p2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.= yaml index 2531726af306b..5b59d91de47bd 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml @@ -65,6 +65,26 @@ properties: - const: dclk_vp3 - const: pclk_vop =20 + resets: + minItems: 5 + items: + - description: AXI clock reset. + - description: AHB clock reset. + - description: Pixel clock reset for video port 0. + - description: Pixel clock reset for video port 1. + - description: Pixel clock reset for video port 2. + - description: Pixel clock reset for video port 3. + + reset-names: + minItems: 5 + items: + - const: aclk + - const: hclk + - const: dclk_vp0 + - const: dclk_vp1 + - const: dclk_vp2 + - const: dclk_vp3 + rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -128,6 +148,11 @@ allOf: clock-names: minItems: 7 =20 + resets: + minItems: 6 + reset-names: + minItems: 6 + ports: required: - port@0 @@ -152,6 +177,11 @@ allOf: clock-names: maxItems: 5 =20 + resets: + maxItems: 5 + reset-names: + maxItems: 5 + ports: required: - port@0 @@ -183,6 +213,16 @@ examples: "dclk_vp0", "dclk_vp1", "dclk_vp2"; + resets =3D <&cru SRST_A_VOP>, + <&cru SRST_H_VOP>, + <&cru SRST_VOP0>, + <&cru SRST_VOP1>, + <&cru SRST_VOP2>; + reset-names =3D "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2"; power-domains =3D <&power RK3568_PD_VO>; iommus =3D <&vop_mmu>; vop_out: ports { --=20 2.47.0