From nobody Sat Nov 23 02:47:52 2024 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C33F71BDAAF for ; Fri, 15 Nov 2024 13:26:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.200 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731677200; cv=none; b=cfLk3SEt3ac9MPEghTzdpebPFUxHTb9Qcw8Mgjv5/0V4IzMUC3wXV12xT4K7kMp9OjAhTOOxZW7YNN3AfEa0PFxeqWb6o/HqVlNFnzaOywucQ/6OqKHxD3Y1L0pfe11yttQwS5HLP8bY8Tmutk9BE21r7BohlYGmQW510ayUURQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731677200; c=relaxed/simple; bh=TgN/rP+ogIi3zekJr5MEk3znfMU8uUpre/kMfy7h0eA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pL/VmA0YGxqvFwQeitOOKgXxx1fk4/Kat+93F3dLyqGi1h//J8FRmDeqkm8N058lbhyKE7TMAmmArRZYxo0jLM7NylOvcMZ5og+pjZMoWStjRhPagiORQ46CEivOSaogidHYxa7wauz9sAHCJCsMK7mxa/vMb1fnRH5O6Q+n9Gw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=mx41yKQX; arc=none smtp.client-ip=217.70.183.200 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="mx41yKQX" Received: by mail.gandi.net (Postfix) with ESMTPA id BBA2A2000B; Fri, 15 Nov 2024 13:26:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1731677197; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SzNrkuGWKWD55JZM/GQ2t5ynM+4vtrlwykyzhs1qoMU=; b=mx41yKQX45BJTNnKZhaXMXRgXCWImkmlAlVK/L4VG7L8f9jxF7h3FvG4zoBEVNqanqA/dw tEiIKrdyi9tKrgo9uA0A7RRwmGkWUNXtxF0AYeujC2lXQjn0vrvxqFai5IZG8zgUSZs2uv 1VdeUOWdtahTe7SWE0hK+sUtbxsBG4MvwFmv9pugtbIQBcIeh8J+FROpiLb+q4rPRNJWyV +xcKwE+d80/UvTb8WszTe+h3BES4kPRQrcXV6AF80ZXjBHp0WSWK1VuQ1btP64ywjU5itE FGghxwBOXE2rIsi8tL6yzsDWzEIC8pL7yAlkYZK2TVecYgCSJOpRrgluO7BOyQ== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v4 05/10] memory: ti-aemif: Create aemif_set_cs_timings() Date: Fri, 15 Nov 2024 14:26:26 +0100 Message-ID: <20241115132631.264609-6-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241115132631.264609-1-bastien.curutchet@bootlin.com> References: <20241115132631.264609-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" Create an aemif_set_cs_timings() function to isolate the setting of a chip select timing configuration and ease its exportation. Signed-off-by: Bastien Curutchet Reviewed-by: Miquel Raynal --- drivers/memory/ti-aemif.c | 66 +++++++++++++++++++++++++++++---------- 1 file changed, 50 insertions(+), 16 deletions(-) diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index 5c1c6f95185f..dae3441e0cd9 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -69,15 +69,16 @@ #define ACR_SSTROBE_MASK BIT(31) #define ASIZE_16BIT 1 =20 -#define CONFIG_MASK (TA(TA_MAX) | \ - RHOLD(RHOLD_MAX) | \ - RSTROBE(RSTROBE_MAX) | \ - RSETUP(RSETUP_MAX) | \ - WHOLD(WHOLD_MAX) | \ - WSTROBE(WSTROBE_MAX) | \ - WSETUP(WSETUP_MAX) | \ - EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | \ - ASIZE_MAX) +#define TIMINGS_MASK (TA(TA_MAX) | \ + RHOLD(RHOLD_MAX) | \ + RSTROBE(RSTROBE_MAX) | \ + RSETUP(RSETUP_MAX) | \ + WHOLD(WHOLD_MAX) | \ + WSTROBE(WSTROBE_MAX) | \ + WSETUP(WSETUP_MAX)) + +#define CONFIG_MASK (EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | ASIZE_MAX) + /** * struct aemif_cs_timings: structure to hold CS timings * @wstrobe: write strobe width, number of cycles - 1 @@ -164,6 +165,44 @@ static int aemif_check_cs_timings(struct aemif_cs_timi= ngs *timings) return 0; } =20 +/** + * aemif_set_cs_timings - Set the timing configuration of a given chip sel= ect. + * @aemif: aemif device to configure + * @cs: index of the chip select to configure + * @timings: timings configuration to set + * + * @return: 0 on success, else negative errno. + */ +static int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct = aemif_cs_timings *timings) +{ + unsigned int offset; + u32 val, set; + int ret; + + if (!timings || !aemif) + return -EINVAL; + + if (cs > aemif->num_cs) + return -EINVAL; + + ret =3D aemif_check_cs_timings(timings); + if (ret) + return ret; + + set =3D TA(timings->ta) | RHOLD(timings->rhold) | RSTROBE(timings->rstrob= e) | + RSETUP(timings->rsetup) | WHOLD(timings->whold) | + WSTROBE(timings->wstrobe) | WSETUP(timings->wsetup); + + offset =3D A1CR_OFFSET + cs * 4; + + val =3D readl(aemif->base + offset); + val &=3D ~TIMINGS_MASK; + val |=3D set; + writel(val, aemif->base + offset); + + return 0; +} + /** * aemif_calc_rate - calculate timing data. * @pdev: platform device to calculate for @@ -212,12 +251,7 @@ static int aemif_config_abus(struct platform_device *p= dev, int csnum) =20 offset =3D A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4; =20 - set =3D TA(data->timings.ta) | - RHOLD(data->timings.rhold) | RSTROBE(data->timings.rstrobe) | - RSETUP(data->timings.rsetup) | WHOLD(data->timings.whold) | - WSTROBE(data->timings.wstrobe) | WSETUP(data->timings.wsetup); - - set |=3D (data->asize & ACR_ASIZE_MASK); + set =3D (data->asize & ACR_ASIZE_MASK); if (data->enable_ew) set |=3D ACR_EW_MASK; if (data->enable_ss) @@ -228,7 +262,7 @@ static int aemif_config_abus(struct platform_device *pd= ev, int csnum) val |=3D set; writel(val, aemif->base + offset); =20 - return 0; + return aemif_set_cs_timings(aemif, data->cs - aemif->cs_offset, &data->ti= mings); } =20 /** --=20 2.47.0